-/* Target-dependent code for the Acorn Risc Machine (ARM).
- Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995-1999
- Free Software Foundation, Inc.
+/* Common target dependent code for GDB on ARM systems.
+ Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
+ 2001 Free Software Foundation, Inc.
This file is part of GDB.
#include "symfile.h"
#include "gdb_string.h"
#include "coff/internal.h" /* Internal format of COFF symbols in BFD */
+#include "dis-asm.h" /* For register flavors. */
+#include <ctype.h> /* for isupper () */
+#include "regcache.h"
-/*
- The following macros are actually wrong. Neither arm nor thumb can
- or should set the lsb on addr.
- The thumb addresses are mod 2, so (addr & 2) would be a good heuristic
- to use when checking for thumb (see arm_pc_is_thumb() below).
- Unfortunately, something else depends on these (incorrect) macros, so
- fixing them actually breaks gdb. I didn't have time to investigate. Z.R.
- */
-/* Thumb function addresses are odd (bit 0 is set). Here are some
- macros to test, set, or clear bit 0 of addresses. */
+/* Each OS has a different mechanism for accessing the various
+ registers stored in the sigcontext structure.
+
+ SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
+ function pointer) which may be used to determine the addresses
+ of the various saved registers in the sigcontext structure.
+
+ For the ARM target, there are three parameters to this function.
+ The first is the pc value of the frame under consideration, the
+ second the stack pointer of this frame, and the last is the
+ register number to fetch.
+
+ If the tm.h file does not define this macro, then it's assumed that
+ no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
+ be 0.
+
+ When it comes time to multi-arching this code, see the identically
+ named machinery in ia64-tdep.c for an example of how it could be
+ done. It should not be necessary to modify the code below where
+ this macro is used. */
+
+#ifdef SIGCONTEXT_REGISTER_ADDRESS
+#ifndef SIGCONTEXT_REGISTER_ADDRESS_P
+#define SIGCONTEXT_REGISTER_ADDRESS_P() 1
+#endif
+#else
+#define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
+#define SIGCONTEXT_REGISTER_ADDRESS_P() 0
+#endif
+
+extern void _initialize_arm_tdep (void);
+
+/* Number of different reg name sets (options). */
+static int num_flavor_options;
+
+/* We have more registers than the disassembler as gdb can print the value
+ of special registers as well.
+ The general register names are overwritten by whatever is being used by
+ the disassembler at the moment. We also adjust the case of cpsr and fps. */
+
+/* Initial value: Register names used in ARM's ISA documentation. */
+static char * arm_register_name_strings[] =
+{"r0", "r1", "r2", "r3", /* 0 1 2 3 */
+ "r4", "r5", "r6", "r7", /* 4 5 6 7 */
+ "r8", "r9", "r10", "r11", /* 8 9 10 11 */
+ "r12", "sp", "lr", "pc", /* 12 13 14 15 */
+ "f0", "f1", "f2", "f3", /* 16 17 18 19 */
+ "f4", "f5", "f6", "f7", /* 20 21 22 23 */
+ "fps", "cpsr" }; /* 24 25 */
+char **arm_register_names = arm_register_name_strings;
+
+/* Valid register name flavors. */
+static const char **valid_flavors;
+
+/* Disassembly flavor to use. Default to "std" register names. */
+static const char *disassembly_flavor;
+static int current_option; /* Index to that option in the opcodes table. */
+
+/* This is used to keep the bfd arch_info in sync with the disassembly
+ flavor. */
+static void set_disassembly_flavor_sfunc(char *, int,
+ struct cmd_list_element *);
+static void set_disassembly_flavor (void);
+
+static void convert_from_extended (void *ptr, void *dbl);
+
+/* Define other aspects of the stack frame. We keep the offsets of
+ all saved registers, 'cause we need 'em a lot! We also keep the
+ current size of the stack frame, and the offset of the frame
+ pointer from the stack pointer (for frameless functions, and when
+ we're still in the prologue of a function with a frame) */
+
+struct frame_extra_info
+ {
+ struct frame_saved_regs fsr;
+ int framesize;
+ int frameoffset;
+ int framereg;
+ };
+
+/* Addresses for calling Thumb functions have the bit 0 set.
+ Here are some macros to test, set, or clear bit 0 of addresses. */
#define IS_THUMB_ADDR(addr) ((addr) & 1)
#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
-/* Macros to round N up or down to the next A boundary; A must be
- a power of two. */
-#define ROUND_DOWN(n,a) ((n) & ~((a) - 1))
-#define ROUND_UP(n,a) (((n) + (a) - 1) & ~((a) - 1))
-
-static char *apcs_register_names[] =
-{ "a1", "a2", "a3", "a4", /* 0 1 2 3 */
- "v1", "v2", "v3", "v4", /* 4 5 6 7 */
- "v5", "v6", "sl", "fp", /* 8 9 10 11 */
- "ip", "sp", "lr", "pc", /* 12 13 14 15 */
- "f0", "f1", "f2", "f3", /* 16 17 18 19 */
- "f4", "f5", "f6", "f7", /* 20 21 22 23 */
- "fps","ps" } /* 24 25 */;
-
-/* These names are the ones which gcc emits, and
- I find them less confusing. Toggle between them
- using the `othernames' command. */
-static char *additional_register_names[] =
-{ "r0", "r1", "r2", "r3", /* 0 1 2 3 */
- "r4", "r5", "r6", "r7", /* 4 5 6 7 */
- "r8", "r9", "r10", "r11", /* 8 9 10 11 */
- "r12", "r13", "r14", "pc", /* 12 13 14 15 */
- "f0", "f1", "f2", "f3", /* 16 17 18 19 */
- "f4", "f5", "f6", "f7", /* 20 21 22 23 */
- "fps","ps" } /* 24 25 */;
-
-/* By default use the APCS registers names */
-
-char **arm_register_names = apcs_register_names;
-/* This is the variable the is set with "set disassembly-flavor",
- and its legitimate values. */
-static char apcs_flavor[] = "apcs";
-static char r_prefix_flavor[] = "r-prefix";
-static char *valid_flavors[] = {
- apcs_flavor,
- r_prefix_flavor,
- NULL
-};
-static char *disassembly_flavor = apcs_flavor;
-
-/* This is used to keep the bfd arch_info in sync with the disassembly flavor. */
-static void set_disassembly_flavor_sfunc PARAMS ((char *, int, \
- struct cmd_list_element *));
-static void set_disassembly_flavor ();
-
-/* Should call_function allocate stack space for a struct return? */
-/* The system C compiler uses a similar structure return convention to gcc */
+#define SWAP_TARGET_AND_HOST(buffer,len) \
+ do \
+ { \
+ if (TARGET_BYTE_ORDER != HOST_BYTE_ORDER) \
+ { \
+ char tmp; \
+ char *p = (char *)(buffer); \
+ char *q = ((char *)(buffer)) + len - 1; \
+ for (; p < q; p++, q--) \
+ { \
+ tmp = *q; \
+ *q = *p; \
+ *p = tmp; \
+ } \
+ } \
+ } \
+ while (0)
+
+/* Will a function return an aggregate type in memory or in a
+ register? Return 0 if an aggregate type can be returned in a
+ register, 1 if it must be returned in memory. */
+
int
-arm_use_struct_convention (gcc_p, type)
- int gcc_p;
- struct type *type;
+arm_use_struct_convention (int gcc_p, struct type *type)
{
- return (TYPE_LENGTH (type) > 4);
+ int nRc;
+ register enum type_code code;
+
+ /* In the ARM ABI, "integer" like aggregate types are returned in
+ registers. For an aggregate type to be integer like, its size
+ must be less than or equal to REGISTER_SIZE and the offset of
+ each addressable subfield must be zero. Note that bit fields are
+ not addressable, and all addressable subfields of unions always
+ start at offset zero.
+
+ This function is based on the behaviour of GCC 2.95.1.
+ See: gcc/arm.c: arm_return_in_memory() for details.
+
+ Note: All versions of GCC before GCC 2.95.2 do not set up the
+ parameters correctly for a function returning the following
+ structure: struct { float f;}; This should be returned in memory,
+ not a register. Richard Earnshaw sent me a patch, but I do not
+ know of any way to detect if a function like the above has been
+ compiled with the correct calling convention. */
+
+ /* All aggregate types that won't fit in a register must be returned
+ in memory. */
+ if (TYPE_LENGTH (type) > REGISTER_SIZE)
+ {
+ return 1;
+ }
+
+ /* The only aggregate types that can be returned in a register are
+ structs and unions. Arrays must be returned in memory. */
+ code = TYPE_CODE (type);
+ if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
+ {
+ return 1;
+ }
+
+ /* Assume all other aggregate types can be returned in a register.
+ Run a check for structures, unions and arrays. */
+ nRc = 0;
+
+ if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
+ {
+ int i;
+ /* Need to check if this struct/union is "integer" like. For
+ this to be true, its size must be less than or equal to
+ REGISTER_SIZE and the offset of each addressable subfield
+ must be zero. Note that bit fields are not addressable, and
+ unions always start at offset zero. If any of the subfields
+ is a floating point type, the struct/union cannot be an
+ integer type. */
+
+ /* For each field in the object, check:
+ 1) Is it FP? --> yes, nRc = 1;
+ 2) Is it addressable (bitpos != 0) and
+ not packed (bitsize == 0)?
+ --> yes, nRc = 1
+ */
+
+ for (i = 0; i < TYPE_NFIELDS (type); i++)
+ {
+ enum type_code field_type_code;
+ field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
+
+ /* Is it a floating point type field? */
+ if (field_type_code == TYPE_CODE_FLT)
+ {
+ nRc = 1;
+ break;
+ }
+
+ /* If bitpos != 0, then we have to care about it. */
+ if (TYPE_FIELD_BITPOS (type, i) != 0)
+ {
+ /* Bitfields are not addressable. If the field bitsize is
+ zero, then the field is not packed. Hence it cannot be
+ a bitfield or any other packed type. */
+ if (TYPE_FIELD_BITSIZE (type, i) == 0)
+ {
+ nRc = 1;
+ break;
+ }
+ }
+ }
+ }
+
+ return nRc;
}
int
-arm_frame_chain_valid (chain, thisframe)
- CORE_ADDR chain;
- struct frame_info *thisframe;
+arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
{
-#define LOWEST_PC 0x20 /* the first 0x20 bytes are the trap vectors. */
return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC));
}
int arm_apcs_32 = 1;
-/* Flag set by arm_fix_call_dummy that tells whether the target function
- is a Thumb function. This flag is checked by arm_push_arguments.
- FIXME: Change the PUSH_ARGUMENTS macro (and its use in valops.c) to
- pass the function address as an additional parameter. */
+/* Flag set by arm_fix_call_dummy that tells whether the target
+ function is a Thumb function. This flag is checked by
+ arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
+ its use in valops.c) to pass the function address as an additional
+ parameter. */
static int target_is_thumb;
-/* Flag set by arm_fix_call_dummy that tells whether the calling function
- is a Thumb function. This flag is checked by arm_pc_is_thumb
- and arm_call_dummy_breakpoint_offset. */
+/* Flag set by arm_fix_call_dummy that tells whether the calling
+ function is a Thumb function. This flag is checked by
+ arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
static int caller_is_thumb;
-/* Tell if the program counter value in MEMADDR is in a Thumb function. */
+/* Determine if the program counter specified in MEMADDR is in a Thumb
+ function. */
int
-arm_pc_is_thumb (memaddr)
- bfd_vma memaddr;
+arm_pc_is_thumb (CORE_ADDR memaddr)
{
struct minimal_symbol *sym;
- CORE_ADDR sp;
- /* If bit 0 of the address is set, assume this is a Thumb address. */
+ /* If bit 0 of the address is set, assume this is a Thumb address. */
if (IS_THUMB_ADDR (memaddr))
return 1;
- /* Thumb function have a "special" bit set in minimal symbols */
+ /* Thumb functions have a "special" bit set in minimal symbols. */
sym = lookup_minimal_symbol_by_pc (memaddr);
if (sym)
{
return (MSYMBOL_IS_SPECIAL (sym));
}
else
- return 0;
+ {
+ return 0;
+ }
}
-/* Tell if the program counter value in MEMADDR is in a call dummy that
- is being called from a Thumb function. */
+/* Determine if the program counter specified in MEMADDR is in a call
+ dummy being called from a Thumb function. */
int
-arm_pc_is_thumb_dummy (memaddr)
- bfd_vma memaddr;
+arm_pc_is_thumb_dummy (CORE_ADDR memaddr)
{
CORE_ADDR sp = read_sp ();
- if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 64))
+ /* FIXME: Until we switch for the new call dummy macros, this heuristic
+ is the best we can do. We are trying to determine if the pc is on
+ the stack, which (hopefully) will only happen in a call dummy.
+ We hope the current stack pointer is not so far alway from the dummy
+ frame location (true if we have not pushed large data structures or
+ gone too many levels deep) and that our 1024 is not enough to consider
+ code regions as part of the stack (true for most practical purposes) */
+ if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
return caller_is_thumb;
else
return 0;
}
CORE_ADDR
-arm_addr_bits_remove (val)
- CORE_ADDR val;
+arm_addr_bits_remove (CORE_ADDR val)
{
if (arm_pc_is_thumb (val))
return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe));
}
CORE_ADDR
-arm_saved_pc_after_call (frame)
- struct frame_info *frame;
+arm_saved_pc_after_call (struct frame_info *frame)
{
return ADDR_BITS_REMOVE (read_register (LR_REGNUM));
}
int
-arm_frameless_function_invocation (fi)
- struct frame_info *fi;
+arm_frameless_function_invocation (struct frame_info *fi)
{
CORE_ADDR func_start, after_prologue;
int frameless;
-
+
func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET);
after_prologue = SKIP_PROLOGUE (func_start);
-
+
/* There are some frameless functions whose first two instructions
- follow the standard APCS form, in which case after_prologue
- will be func_start + 8. */
-
+ follow the standard APCS form, in which case after_prologue will
+ be func_start + 8. */
+
frameless = (after_prologue < func_start + 12);
return frameless;
}
add sp, sp, #-28
add r7, sp, #12
Sometimes the latter instruction may be replaced by:
- mov r7, sp
- */
+ mov r7, sp
+
+ or like this:
+ push {r7, lr}
+ mov r7, sp
+ sub sp, #12
+
+ or, on tpcs, like this:
+ sub sp,#16
+ push {r7, lr}
+ (many instructions)
+ mov r7, sp
+ sub sp, #12
+
+ There is always one instruction of three classes:
+ 1 - push
+ 2 - setting of r7
+ 3 - adjusting of sp
+
+ When we have found at least one of each class we are done with the prolog.
+ Note that the "sub sp, #NN" before the push does not count.
+ */
static CORE_ADDR
-thumb_skip_prologue (pc)
- CORE_ADDR pc;
+thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
{
CORE_ADDR current_pc;
+ int findmask = 0; /* findmask:
+ bit 0 - push { rlist }
+ bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
+ bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
+ */
- for (current_pc = pc; current_pc < pc + 20; current_pc += 2)
+ for (current_pc = pc; current_pc + 2 < func_end && current_pc < pc + 40; current_pc += 2)
{
unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
- if ((insn & 0xfe00) != 0xb400 /* push {..., r7, lr} */
- && (insn & 0xff00) != 0xb000 /* add sp, #simm */
- && (insn & 0xff00) != 0xaf00 /* add r7, sp, #imm */
- && insn != 0x466f /* mov r7, sp */
- && (insn & 0xffc0) != 0x4640) /* mov r0-r7, r8-r15 */
- break;
+ if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
+ {
+ findmask |= 1; /* push found */
+ }
+ else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
+ {
+ if ((findmask & 1) == 0) /* before push ? */
+ continue;
+ else
+ findmask |= 4; /* add/sub sp found */
+ }
+ else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
+ {
+ findmask |= 2; /* setting of r7 found */
+ }
+ else if (insn == 0x466f) /* mov r7, sp */
+ {
+ findmask |= 2; /* setting of r7 found */
+ }
+ else
+ continue; /* something in the prolog that we don't care about or some
+ instruction from outside the prolog scheduled here for optimization */
}
return current_pc;
}
-/* APCS (ARM procedure call standard) defines the following prologue:
+/* The APCS (ARM Procedure Call Standard) defines the following
+ prologue:
mov ip, sp
[stmfd sp!, {a1,a2,a3,a4}]
stmfd sp!, {...,fp,ip,lr,pc}
- [stfe f7, [sp, #-12]!]
- [stfe f6, [sp, #-12]!]
- [stfe f5, [sp, #-12]!]
- [stfe f4, [sp, #-12]!]
- sub fp, ip, #nn // nn == 20 or 4 depending on second ins
- */
+ [stfe f7, [sp, #-12]!]
+ [stfe f6, [sp, #-12]!]
+ [stfe f5, [sp, #-12]!]
+ [stfe f4, [sp, #-12]!]
+ sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
CORE_ADDR
-arm_skip_prologue (pc)
- CORE_ADDR pc;
+arm_skip_prologue (CORE_ADDR pc)
{
unsigned long inst;
CORE_ADDR skip_pc;
struct symtab_and_line sal;
/* See what the symbol table says. */
-
+
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
{
sal = find_pc_line (func_addr, 0);
/* Check if this is Thumb code. */
if (arm_pc_is_thumb (pc))
- return thumb_skip_prologue (pc);
+ return thumb_skip_prologue (pc, func_end);
/* Can't find the prologue end in the symbol table, try it the hard way
by disassembling the instructions. */
inst = read_memory_integer (skip_pc, 4);
/* Any insns after this point may float into the code, if it makes
- for better instruction scheduling, so we skip them only if
- we find them, but still consdier the function to be frame-ful */
+ for better instruction scheduling, so we skip them only if we
+ find them, but still consdier the function to be frame-ful. */
- /* We may have either one sfmfd instruction here, or several stfe insns,
- depending on the version of floating point code we support. */
+ /* We may have either one sfmfd instruction here, or several stfe
+ insns, depending on the version of floating point code we
+ support. */
if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
{
skip_pc += 4;
4) the offset from the stack pointer to the frame pointer
This information is stored in the "extra" fields of the frame_info.
- A typical Thumb function prologue might look like this:
- push {r7, lr}
- sub sp, #28,
- add r7, sp, #12
- Which would create this stack frame (offsets relative to FP)
+ A typical Thumb function prologue would create this stack frame
+ (offsets relative to FP)
old SP -> 24 stack parameters
20 LR
16 R7
R7 -> 0 local variables (16 bytes)
SP -> -12 additional stack space (12 bytes)
The frame size would thus be 36 bytes, and the frame offset would be
- 12 bytes. The frame register is R7. */
+ 12 bytes. The frame register is R7.
+
+ The comments for thumb_skip_prolog() describe the algorithm we use to detect
+ the end of the prolog */
/* *INDENT-ON* */
-
-
-
static void
-thumb_scan_prologue (fi)
- struct frame_info *fi;
+thumb_scan_prologue (struct frame_info *fi)
{
CORE_ADDR prologue_start;
CORE_ADDR prologue_end;
CORE_ADDR current_pc;
int saved_reg[16]; /* which register has been copied to register n? */
+ int findmask = 0; /* findmask:
+ bit 0 - push { rlist }
+ bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
+ bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
+ */
int i;
if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
saved_reg[i] = i;
/* Search the prologue looking for instructions that set up the
- frame pointer, adjust the stack pointer, and save registers. */
+ frame pointer, adjust the stack pointer, and save registers.
+ Do this until all basic prolog instructions are found. */
fi->framesize = 0;
- for (current_pc = prologue_start; current_pc < prologue_end; current_pc += 2)
+ for (current_pc = prologue_start;
+ (current_pc < prologue_end) && ((findmask & 7) != 7);
+ current_pc += 2)
{
unsigned short insn;
int regno;
if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
{
+ int mask;
+ findmask |= 1; /* push found */
/* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
whether to save LR (R14). */
- int mask = (insn & 0xff) | ((insn & 0x100) << 6);
+ mask = (insn & 0xff) | ((insn & 0x100) << 6);
/* Calculate offsets of saved R0-R7 and LR. */
for (regno = LR_REGNUM; regno >= 0; regno--)
saved_reg[regno] = regno; /* reset saved register map */
}
}
- else if ((insn & 0xff00) == 0xb000) /* add sp, #simm */
+ else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
{
+ if ((findmask & 1) == 0) /* before push ? */
+ continue;
+ else
+ findmask |= 4; /* add/sub sp found */
+
offset = (insn & 0x7f) << 2; /* get scaled offset */
- if (insn & 0x80) /* is it signed? */
- offset = -offset;
+ if (insn & 0x80) /* is it signed? (==subtracting) */
+ {
+ fi->frameoffset += offset;
+ offset = -offset;
+ }
fi->framesize -= offset;
}
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
{
+ findmask |= 2; /* setting of r7 found */
fi->framereg = THUMB_FP_REGNUM;
fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */
}
- else if (insn == 0x466f) /* mov r7, sp */
+ else if (insn == 0x466f) /* mov r7, sp */
{
+ findmask |= 2; /* setting of r7 found */
fi->framereg = THUMB_FP_REGNUM;
fi->frameoffset = 0;
saved_reg[THUMB_FP_REGNUM] = SP_REGNUM;
saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
}
else
- break; /* anything else isn't prologue */
+ continue; /* something in the prolog that we don't care about or some
+ instruction from outside the prolog scheduled here for optimization */
}
}
-/* Function: check_prologue_cache
- Check if prologue for this frame's PC has already been scanned.
- If it has, copy the relevant information about that prologue and
+/* Check if prologue for this frame's PC has already been scanned. If
+ it has, copy the relevant information about that prologue and
return non-zero. Otherwise do not copy anything and return zero.
The information saved in the cache includes:
* the offsets of saved regs (relative to the old SP); and
* the offset from the stack pointer to the frame pointer
- The cache contains only one entry, since this is adequate
- for the typical sequence of prologue scan requests we get.
- When performing a backtrace, GDB will usually ask to scan
- the same function twice in a row (once to get the frame chain,
- and once to fill in the extra frame information).
- */
+ The cache contains only one entry, since this is adequate for the
+ typical sequence of prologue scan requests we get. When performing
+ a backtrace, GDB will usually ask to scan the same function twice
+ in a row (once to get the frame chain, and once to fill in the
+ extra frame information). */
static struct frame_info prologue_cache;
static int
-check_prologue_cache (fi)
- struct frame_info *fi;
+check_prologue_cache (struct frame_info *fi)
{
int i;
fi->framereg = prologue_cache.framereg;
fi->framesize = prologue_cache.framesize;
fi->frameoffset = prologue_cache.frameoffset;
- for (i = 0; i <= NUM_REGS; i++)
+ for (i = 0; i < NUM_REGS; i++)
fi->fsr.regs[i] = prologue_cache.fsr.regs[i];
return 1;
}
}
-/* Function: save_prologue_cache
- Copy the prologue information from fi to the prologue cache.
- */
+/* Copy the prologue information from fi to the prologue cache. */
static void
-save_prologue_cache (fi)
- struct frame_info *fi;
+save_prologue_cache (struct frame_info *fi)
{
int i;
prologue_cache.framesize = fi->framesize;
prologue_cache.frameoffset = fi->frameoffset;
- for (i = 0; i <= NUM_REGS; i++)
+ for (i = 0; i < NUM_REGS; i++)
prologue_cache.fsr.regs[i] = fi->fsr.regs[i];
}
-/* Function: arm_scan_prologue
- This function decodes an ARM function prologue to determine:
+/* This function decodes an ARM function prologue to determine:
1) the size of the stack frame
2) which registers are saved on it
3) the offsets of saved regs
There are two basic forms for the ARM prologue. The fixed argument
function call will look like:
-
- mov ip, sp
- stmfd sp!, {fp, ip, lr, pc}
- sub fp, ip, #4
- [sub sp, sp, #4]
+
+ mov ip, sp
+ stmfd sp!, {fp, ip, lr, pc}
+ sub fp, ip, #4
+ [sub sp, sp, #4]
Which would create this stack frame (offsets relative to FP):
- IP -> 4 (caller's stack)
- FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
- -4 LR (return address in caller)
- -8 IP (copy of caller's SP)
- -12 FP (caller's FP)
- SP -> -28 Local variables
-
+ IP -> 4 (caller's stack)
+ FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
+ -4 LR (return address in caller)
+ -8 IP (copy of caller's SP)
+ -12 FP (caller's FP)
+ SP -> -28 Local variables
+
The frame size would thus be 32 bytes, and the frame offset would be
28 bytes. The stmfd call can also save any of the vN registers it
plans to use, which increases the frame size accordingly.
Note: The stored PC is 8 off of the STMFD instruction that stored it
because the ARM Store instructions always store PC + 8 when you read
the PC register.
-
+
A variable argument function call will look like:
- mov ip, sp
- stmfd sp!, {a1, a2, a3, a4}
- stmfd sp!, {fp, ip, lr, pc}
- sub fp, ip, #20
-
+ mov ip, sp
+ stmfd sp!, {a1, a2, a3, a4}
+ stmfd sp!, {fp, ip, lr, pc}
+ sub fp, ip, #20
+
Which would create this stack frame (offsets relative to FP):
- IP -> 20 (caller's stack)
- 16 A4
- 12 A3
- 8 A2
- 4 A1
- FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
- -4 LR (return address in caller)
- -8 IP (copy of caller's SP)
- -12 FP (caller's FP)
- SP -> -28 Local variables
+ IP -> 20 (caller's stack)
+ 16 A4
+ 12 A3
+ 8 A2
+ 4 A1
+ FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
+ -4 LR (return address in caller)
+ -8 IP (copy of caller's SP)
+ -12 FP (caller's FP)
+ SP -> -28 Local variables
The frame size would thus be 48 bytes, and the frame offset would be
28 bytes.
instruction at the end of the prologue. I have never seen GCC produce
this, and the ARM docs don't mention it. We still test for it below in
case it happens...
-
-*/
+
+ */
static void
-arm_scan_prologue (fi)
- struct frame_info *fi;
+arm_scan_prologue (struct frame_info *fi)
{
int regno, sp_offset, fp_offset;
CORE_ADDR prologue_start, prologue_end, current_pc;
the symbol table, peek in the stack frame to find the PC. */
if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
{
- /* Assume the prologue is everything between the first instruction
- in the function and the first source line. */
- struct symtab_and_line sal = find_pc_line (prologue_start, 0);
-
- if (sal.line == 0) /* no line info, use current PC */
- prologue_end = fi->pc;
- else if (sal.end < prologue_end) /* next line begins after fn end */
- prologue_end = sal.end; /* (probably means no prologue) */
+ /* One way to find the end of the prologue (which works well
+ for unoptimized code) is to do the following:
+
+ struct symtab_and_line sal = find_pc_line (prologue_start, 0);
+
+ if (sal.line == 0)
+ prologue_end = fi->pc;
+ else if (sal.end < prologue_end)
+ prologue_end = sal.end;
+
+ This mechanism is very accurate so long as the optimizer
+ doesn't move any instructions from the function body into the
+ prologue. If this happens, sal.end will be the last
+ instruction in the first hunk of prologue code just before
+ the first instruction that the scheduler has moved from
+ the body to the prologue.
+
+ In order to make sure that we scan all of the prologue
+ instructions, we use a slightly less accurate mechanism which
+ may scan more than necessary. To help compensate for this
+ lack of accuracy, the prologue scanning loop below contains
+ several clauses which'll cause the loop to terminate early if
+ an implausible prologue instruction is encountered.
+
+ The expression
+
+ prologue_start + 64
+
+ is a suitable endpoint since it accounts for the largest
+ possible prologue plus up to five instructions inserted by
+ the scheduler. */
+
+ if (prologue_end > prologue_start + 64)
+ {
+ prologue_end = prologue_start + 64; /* See above. */
+ }
}
else
{
/* Get address of the stmfd in the prologue of the callee; the saved
PC is the address of the stmfd + 8. */
- prologue_start = ADDR_BITS_REMOVE(read_memory_integer (fi->frame, 4))
+ prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4))
- 8;
- prologue_end = prologue_start + 64; /* This is all the insn's
- that could be in the prologue,
- plus room for 5 insn's inserted
- by the scheduler. */
+ prologue_end = prologue_start + 64; /* See above. */
}
/* Now search the prologue looking for instructions that set up the
frame pointer, adjust the stack pointer, and save registers.
-
+
Be careful, however, and if it doesn't look like a prologue,
don't try to scan it. If, for instance, a frameless function
begins with stmfd sp!, then we will tell ourselves there is
sp_offset = fp_offset = 0;
- if (read_memory_unsigned_integer (prologue_start, 4)
- == 0xe1a0c00d) /* mov ip, sp */
+ if (read_memory_unsigned_integer (prologue_start, 4)
+ == 0xe1a0c00d) /* mov ip, sp */
{
- for (current_pc = prologue_start +4; current_pc < prologue_end;
+ for (current_pc = prologue_start + 4; current_pc < prologue_end;
current_pc += 4)
{
unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
-
+
if ((insn & 0xffff0000) == 0xe92d0000)
/* stmfd sp!, {..., fp, ip, lr, pc}
or
stmfd sp!, {a1, a2, a3, a4} */
{
int mask = insn & 0xffff;
-
+
/* Calculate offsets of saved registers. */
for (regno = PC_REGNUM; regno >= 0; regno--)
if (mask & (1 << regno))
fi->fsr.regs[regno] = sp_offset;
}
}
- else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
+ else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
{
- unsigned imm = insn & 0xff; /* immediate value */
- unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
- imm = (imm >> rot) | (imm << (32-rot));
+ unsigned imm = insn & 0xff; /* immediate value */
+ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
+ imm = (imm >> rot) | (imm << (32 - rot));
fp_offset = -imm;
fi->framereg = FP_REGNUM;
}
- else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
+ else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
{
- unsigned imm = insn & 0xff; /* immediate value */
- unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
- imm = (imm >> rot) | (imm << (32-rot));
+ unsigned imm = insn & 0xff; /* immediate value */
+ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
+ imm = (imm >> rot) | (imm << (32 - rot));
sp_offset -= imm;
}
- else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
+ else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
{
sp_offset -= 12;
regno = F0_REGNUM + ((insn >> 12) & 0x07);
fi->fsr.regs[regno] = sp_offset;
}
- else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
+ else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
{
- int n_saved_fp_regs, i;
+ int n_saved_fp_regs;
unsigned int fp_start_reg, fp_bound_reg;
-
- if ((insn & 0x800) == 0x800) /* N0 is set */
- {
- if ((insn & 0x40000) == 0x40000) /* N1 is set */
+
+ if ((insn & 0x800) == 0x800) /* N0 is set */
+ {
+ if ((insn & 0x40000) == 0x40000) /* N1 is set */
n_saved_fp_regs = 3;
else
n_saved_fp_regs = 1;
}
else
- {
- if ((insn & 0x40000) == 0x40000) /* N1 is set */
+ {
+ if ((insn & 0x40000) == 0x40000) /* N1 is set */
n_saved_fp_regs = 2;
else
n_saved_fp_regs = 4;
}
-
+
fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7);
fp_bound_reg = fp_start_reg + n_saved_fp_regs;
for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
fi->fsr.regs[fp_start_reg++] = sp_offset;
}
}
+ else if ((insn & 0xf0000000) != 0xe0000000)
+ break; /* Condition not true, exit early */
+ else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
+ break; /* Don't scan past a block load */
else
- continue; /* The optimizer might shove anything into the
- prologue, so we just skip what we don't recognize. */
+ /* The optimizer might shove anything into the prologue,
+ so we just skip what we don't recognize. */
+ continue;
}
}
[new FP] - [new SP]. */
fi->framesize = -sp_offset;
fi->frameoffset = fp_offset - sp_offset;
-
+
save_prologue_cache (fi);
}
-
-/* Function: find_callers_reg
- Find REGNUM on the stack. Otherwise, it's in an active register. One thing
- we might want to do here is to check REGNUM against the clobber mask, and
- somehow flag it as invalid if it isn't saved on the stack somewhere. This
- would provide a graceful failure mode when trying to get the value of
- caller-saves registers for an inner frame. */
+/* Find REGNUM on the stack. Otherwise, it's in an active register.
+ One thing we might want to do here is to check REGNUM against the
+ clobber mask, and somehow flag it as invalid if it isn't saved on
+ the stack somewhere. This would provide a graceful failure mode
+ when trying to get the value of caller-saves registers for an inner
+ frame. */
static CORE_ADDR
-arm_find_callers_reg (fi, regnum)
- struct frame_info *fi;
- int regnum;
+arm_find_callers_reg (struct frame_info *fi, int regnum)
{
for (; fi; fi = fi->next)
*/
/* *INDENT-ON* */
-
-
-
CORE_ADDR
-arm_frame_chain (fi)
- struct frame_info *fi;
+arm_frame_chain (struct frame_info *fi)
{
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
CORE_ADDR fn_start, callers_pc, fp;
return fi->frame + fi->framesize;
}
-/* Function: init_extra_frame_info
- This function actually figures out the frame address for a given pc and
- sp. This is tricky because we sometimes don't use an explicit
- frame pointer, and the previous stack pointer isn't necessarily recorded
- on the stack. The only reliable way to get this info is to
- examine the prologue.
- FROMLEAF is a little confusing, it means this is the next frame up
- the chain AFTER a frameless function. If this is true, then the
- frame value for this frame is still in the fp register. */
+/* This function actually figures out the frame address for a given pc
+ and sp. This is tricky because we sometimes don't use an explicit
+ frame pointer, and the previous stack pointer isn't necessarily
+ recorded on the stack. The only reliable way to get this info is
+ to examine the prologue. FROMLEAF is a little confusing, it means
+ this is the next frame up the chain AFTER a frameless function. If
+ this is true, then the frame value for this frame is still in the
+ fp register. */
void
-arm_init_extra_frame_info (fromleaf, fi)
- int fromleaf;
- struct frame_info * fi;
+arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
{
int reg;
}
else
#endif
+
+ /* Determine whether or not we're in a sigtramp frame.
+ Unfortunately, it isn't sufficient to test
+ fi->signal_handler_caller because this value is sometimes set
+ after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
+ fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
+ to use the sigcontext addresses for the saved registers.
+
+ Note: If an ARM IN_SIGTRAMP method ever needs to compare against
+ the name of the function, the code below will have to be changed
+ to first fetch the name of the function and then pass this name
+ to IN_SIGTRAMP. */
+
+ if (SIGCONTEXT_REGISTER_ADDRESS_P ()
+ && (fi->signal_handler_caller || IN_SIGTRAMP (fi->pc, 0)))
+ {
+ CORE_ADDR sp;
+
+ if (!fi->next)
+ sp = read_sp();
+ else
+ sp = fi->next->frame - fi->next->frameoffset + fi->next->framesize;
+
+ for (reg = 0; reg < NUM_REGS; reg++)
+ fi->fsr.regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg);
+
+ /* FIXME: What about thumb mode? */
+ fi->framereg = SP_REGNUM;
+ fi->frame = read_memory_integer (fi->fsr.regs[fi->framereg], 4);
+ fi->framesize = 0;
+ fi->frameoffset = 0;
+
+ }
+ else
{
arm_scan_prologue (fi);
if (!fi->next)
/* this is the innermost frame? */
fi->frame = read_register (fi->framereg);
- else
- /* not the innermost frame */
- /* If we have an FP, the callee saved it. */
- if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM)
- {
- if (fi->next->fsr.regs[fi->framereg] != 0)
- fi->frame =
- read_memory_integer (fi->next->fsr.regs[fi->framereg], 4);
- else if (fromleaf)
- /* If we were called by a frameless fn. then our frame
- is still in the frame pointer register on the
- board... */
- fi->frame = read_fp ();
- }
+ else if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM)
+ {
+ /* not the innermost frame */
+ /* If we have an FP, the callee saved it. */
+ if (fi->next->fsr.regs[fi->framereg] != 0)
+ fi->frame =
+ read_memory_integer (fi->next->fsr.regs[fi->framereg], 4);
+ else if (fromleaf)
+ /* If we were called by a frameless fn. then our frame is
+ still in the frame pointer register on the board... */
+ fi->frame = read_fp ();
+ }
- /* Calculate actual addresses of saved registers using offsets determined
- by arm_scan_prologue. */
+ /* Calculate actual addresses of saved registers using offsets
+ determined by arm_scan_prologue. */
for (reg = 0; reg < NUM_REGS; reg++)
if (fi->fsr.regs[reg] != 0)
fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset;
}
-/* Function: frame_saved_pc
- Find the caller of this frame. We do this by seeing if LR_REGNUM is saved
- in the stack anywhere, otherwise we get it from the registers.
+/* Find the caller of this frame. We do this by seeing if LR_REGNUM
+ is saved in the stack anywhere, otherwise we get it from the
+ registers.
The old definition of this function was a macro:
#define FRAME_SAVED_PC(FRAME) \
- ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4))
- */
+ ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
CORE_ADDR
-arm_frame_saved_pc (fi)
- struct frame_info *fi;
+arm_frame_saved_pc (struct frame_info *fi)
{
#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
}
}
-
/* Return the frame address. On ARM, it is R11; on Thumb it is R7.
Examine the Program Status Register to decide which state we're in. */
CORE_ADDR
-arm_target_read_fp ()
+arm_target_read_fp (void)
{
if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
return read_register (FP_REGNUM); /* R11 if ARM */
}
+/* Calculate the frame offsets of the saved registers (ARM version). */
-/* Calculate the frame offsets of the saved registers (ARM version). */
void
-arm_frame_find_saved_regs (fi, regaddr)
- struct frame_info *fi;
- struct frame_saved_regs *regaddr;
+arm_frame_find_saved_regs (struct frame_info *fi,
+ struct frame_saved_regs *regaddr)
{
memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs));
}
-
void
-arm_push_dummy_frame ()
+arm_push_dummy_frame (void)
{
CORE_ADDR old_sp = read_register (SP_REGNUM);
CORE_ADDR sp = old_sp;
/* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
prologue_start = sp = push_word (sp, 0xe92ddfff);
- /* push a pointer to the dummy prologue + 12, because when
- stm instruction stores the PC, it stores the address of the stm
+ /* Push a pointer to the dummy prologue + 12, because when stm
+ instruction stores the PC, it stores the address of the stm
instruction itself plus 12. */
fp = sp = push_word (sp, prologue_start + 12);
sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */
}
/* Fix up the call dummy, based on whether the processor is currently
- in Thumb or ARM mode, and whether the target function is Thumb
- or ARM. There are three different situations requiring three
+ in Thumb or ARM mode, and whether the target function is Thumb or
+ ARM. There are three different situations requiring three
different dummies:
* ARM calling ARM: uses the call dummy in tm-arm.h, which has already
* Thumb calling anything: uses the Thumb dummy defined below, which
works for calling both ARM and Thumb functions.
- All three call dummies expect to receive the target function address
- in R4, with the low bit set if it's a Thumb function.
- */
+ All three call dummies expect to receive the target function
+ address in R4, with the low bit set if it's a Thumb function. */
void
-arm_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p)
- char *dummy;
- CORE_ADDR pc;
- CORE_ADDR fun;
- int nargs;
- value_ptr *args;
- struct type *type;
- int gcc_p;
+arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
+ value_ptr *args, struct type *type, int gcc_p)
{
static short thumb_dummy[4] =
{
/* Set flag indicating whether the current PC is in a Thumb function. */
caller_is_thumb = arm_pc_is_thumb (read_pc ());
- /* If the target function is Thumb, set the low bit of the function address.
- And if the CPU is currently in ARM mode, patch the second instruction
- of call dummy to use a BX instruction to switch to Thumb mode. */
+ /* If the target function is Thumb, set the low bit of the function
+ address. And if the CPU is currently in ARM mode, patch the
+ second instruction of call dummy to use a BX instruction to
+ switch to Thumb mode. */
target_is_thumb = arm_pc_is_thumb (fun);
if (target_is_thumb)
{
}
}
- /* Put the target address in r4; the call dummy will copy this to the PC. */
+ /* Put the target address in r4; the call dummy will copy this to
+ the PC. */
write_register (4, fun);
}
-
/* Return the offset in the call dummy of the instruction that needs
- to have a breakpoint placed on it. This is the offset of the 'swi 24'
- instruction, which is no longer actually used, but simply acts
+ to have a breakpoint placed on it. This is the offset of the 'swi
+ 24' instruction, which is no longer actually used, but simply acts
as a place-holder now.
- This implements the CALL_DUMMY_BREAK_OFFSET macro.
- */
+ This implements the CALL_DUMMY_BREAK_OFFSET macro. */
int
-arm_call_dummy_breakpoint_offset ()
+arm_call_dummy_breakpoint_offset (void)
{
if (caller_is_thumb)
return 4;
return 8;
}
+/* Note: ScottB
+
+ This function does not support passing parameters using the FPA
+ variant of the APCS. It passes any floating point arguments in the
+ general registers and/or on the stack. */
CORE_ADDR
-arm_push_arguments (nargs, args, sp, struct_return, struct_addr)
- int nargs;
- value_ptr *args;
- CORE_ADDR sp;
- int struct_return;
- CORE_ADDR struct_addr;
+arm_push_arguments (int nargs, value_ptr * args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
{
- int argreg;
- int float_argreg;
- int argnum;
- int stack_offset;
- struct stack_arg
+ char *fp;
+ int argnum, argreg, nstack_size;
+
+ /* Walk through the list of args and determine how large a temporary
+ stack is required. Need to take care here as structs may be
+ passed on the stack, and we have to to push them. */
+ nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */
+ if (struct_return) /* The struct address goes in A1. */
+ nstack_size += REGISTER_SIZE;
+
+ /* Walk through the arguments and add their size to nstack_size. */
+ for (argnum = 0; argnum < nargs; argnum++)
{
- char *val;
int len;
- int offset;
- };
- struct stack_arg *stack_args =
- (struct stack_arg *) alloca (nargs * sizeof (struct stack_arg));
- int nstack_args = 0;
+ struct type *arg_type;
+
+ arg_type = check_typedef (VALUE_TYPE (args[argnum]));
+ len = TYPE_LENGTH (arg_type);
+
+ /* ANSI C code passes float arguments as integers, K&R code
+ passes float arguments as doubles. Correct for this here. */
+ if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len)
+ nstack_size += FP_REGISTER_VIRTUAL_SIZE;
+ else
+ nstack_size += len;
+ }
+ /* Allocate room on the stack, and initialize our stack frame
+ pointer. */
+ fp = NULL;
+ if (nstack_size > 0)
+ {
+ sp -= nstack_size;
+ fp = (char *) sp;
+ }
- /* Initialize the integer and float register pointers. */
+ /* Initialize the integer argument register pointer. */
argreg = A1_REGNUM;
- float_argreg = F0_REGNUM;
- /* the struct_return pointer occupies the first parameter-passing reg */
+ /* The struct_return pointer occupies the first parameter passing
+ register. */
if (struct_return)
write_register (argreg++, struct_addr);
- /* The offset onto the stack at which we will start copying parameters
- (after the registers are used up) begins at 16 in the old ABI.
- This leaves room for the "home" area for register parameters. */
- stack_offset = REGISTER_SIZE * 4;
-
- /* Process args from left to right. Store as many as allowed in
- registers, save the rest to be pushed on the stack */
+ /* Process arguments from left to right. Store as many as allowed
+ in the parameter passing registers (A1-A4), and save the rest on
+ the temporary stack. */
for (argnum = 0; argnum < nargs; argnum++)
{
+ int len;
char *val;
- value_ptr arg = args[argnum];
- struct type *arg_type = check_typedef (VALUE_TYPE (arg));
- struct type *target_type = TYPE_TARGET_TYPE (arg_type);
- int len = TYPE_LENGTH (arg_type);
- enum type_code typecode = TYPE_CODE (arg_type);
+ double dbl_arg;
CORE_ADDR regval;
- int newarg;
-
- val = (char *) VALUE_CONTENTS (arg);
-
- /* If the argument is a pointer to a function, and it's a Thumb
+ enum type_code typecode;
+ struct type *arg_type, *target_type;
+
+ arg_type = check_typedef (VALUE_TYPE (args[argnum]));
+ target_type = TYPE_TARGET_TYPE (arg_type);
+ len = TYPE_LENGTH (arg_type);
+ typecode = TYPE_CODE (arg_type);
+ val = (char *) VALUE_CONTENTS (args[argnum]);
+
+ /* ANSI C code passes float arguments as integers, K&R code
+ passes float arguments as doubles. The .stabs record for
+ for ANSI prototype floating point arguments records the
+ type as FP_INTEGER, while a K&R style (no prototype)
+ .stabs records the type as FP_FLOAT. In this latter case
+ the compiler converts the float arguments to double before
+ calling the function. */
+ if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len)
+ {
+ float f;
+ double d;
+ char * bufo = (char *) &d;
+ char * bufd = (char *) &dbl_arg;
+
+ len = sizeof (double);
+ f = *(float *) val;
+ SWAP_TARGET_AND_HOST (&f, sizeof (float)); /* adjust endianess */
+ d = f;
+ /* We must revert the longwords so they get loaded into the
+ the right registers. */
+ memcpy (bufd, bufo + len / 2, len / 2);
+ SWAP_TARGET_AND_HOST (bufd, len / 2); /* adjust endianess */
+ memcpy (bufd + len / 2, bufo, len / 2);
+ SWAP_TARGET_AND_HOST (bufd + len / 2, len / 2); /* adjust endianess */
+ val = (char *) &dbl_arg;
+ }
+#if 1
+ /* I don't know why this code was disable. The only logical use
+ for a function pointer is to call that function, so setting
+ the mode bit is perfectly fine. FN */
+ /* If the argument is a pointer to a function, and it is a Thumb
function, set the low bit of the pointer. */
- if (typecode == TYPE_CODE_PTR
- && target_type != NULL
- && TYPE_CODE (target_type) == TYPE_CODE_FUNC)
+ if (TYPE_CODE_PTR == typecode
+ && NULL != target_type
+ && TYPE_CODE_FUNC == TYPE_CODE (target_type))
{
- regval = extract_address (val, len);
+ CORE_ADDR regval = extract_address (val, len);
if (arm_pc_is_thumb (regval))
store_address (val, len, MAKE_THUMB_ADDR (regval));
}
-
-#define MAPCS_FLOAT 0 /* --mapcs-float not implemented by the compiler yet */
-#if MAPCS_FLOAT
- /* Up to four floating point arguments can be passed in floating
- point registers on ARM (not on Thumb). */
- if (typecode == TYPE_CODE_FLT
- && float_argreg <= ARM_LAST_FP_ARG_REGNUM
- && !target_is_thumb)
- {
- /* This is a floating point value that fits entirely
- in a single register. */
- regval = extract_address (val, len);
- write_register (float_argreg++, regval);
- }
- else
#endif
+ /* Copy the argument to general registers or the stack in
+ register-sized pieces. Large arguments are split between
+ registers and stack. */
+ while (len > 0)
{
- /* Copy the argument to general registers or the stack in
- register-sized pieces. Large arguments are split between
- registers and stack. */
- while (len > 0)
+ int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
+
+ if (argreg <= ARM_LAST_ARG_REGNUM)
{
- if (argreg <= ARM_LAST_ARG_REGNUM)
- {
- int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
- regval = extract_address (val, partial_len);
-
- /* It's a simple argument being passed in a general
- register. */
- write_register (argreg, regval);
- argreg++;
- len -= partial_len;
- val += partial_len;
- }
- else
- {
- /* keep for later pushing */
- stack_args[nstack_args].val = val;
- stack_args[nstack_args++].len = len;
- break;
- }
+ /* It's an argument being passed in a general register. */
+ regval = extract_address (val, partial_len);
+ write_register (argreg++, regval);
}
+ else
+ {
+ /* Push the arguments onto the stack. */
+ write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE);
+ fp += REGISTER_SIZE;
+ }
+
+ len -= partial_len;
+ val += partial_len;
}
}
- /* now do the real stack pushing, process args right to left */
- while (nstack_args--)
- {
- sp -= stack_args[nstack_args].len;
- write_memory (sp, stack_args[nstack_args].val,
- stack_args[nstack_args].len);
- }
/* Return adjusted stack pointer. */
return sp;
}
void
-arm_pop_frame ()
+arm_pop_frame (void)
{
- struct frame_info *frame = get_current_frame ();
int regnum;
- CORE_ADDR old_SP;
+ struct frame_info *frame = get_current_frame ();
- old_SP = read_register (frame->framereg);
- for (regnum = 0; regnum < NUM_REGS; regnum++)
- if (frame->fsr.regs[regnum] != 0)
- write_register (regnum,
+ if (!PC_IN_CALL_DUMMY(frame->pc, frame->frame, read_fp()))
+ {
+ CORE_ADDR old_SP;
+
+ old_SP = read_register (frame->framereg);
+ for (regnum = 0; regnum < NUM_REGS; regnum++)
+ if (frame->fsr.regs[regnum] != 0)
+ write_register (regnum,
read_memory_integer (frame->fsr.regs[regnum], 4));
- write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
- write_register (SP_REGNUM, old_SP);
+ write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
+ write_register (SP_REGNUM, old_SP);
+ }
+ else
+ {
+ CORE_ADDR sp;
+
+ sp = read_register (FP_REGNUM);
+ sp -= sizeof(CORE_ADDR); /* we don't care about this first word */
+
+ write_register (PC_REGNUM, read_memory_integer (sp, 4));
+ sp -= sizeof(CORE_ADDR);
+ write_register (SP_REGNUM, read_memory_integer (sp, 4));
+ sp -= sizeof(CORE_ADDR);
+ write_register (FP_REGNUM, read_memory_integer (sp, 4));
+ sp -= sizeof(CORE_ADDR);
+
+ for (regnum = 10; regnum >= 0; regnum--)
+ {
+ write_register (regnum, read_memory_integer (sp, 4));
+ sp -= sizeof(CORE_ADDR);
+ }
+ }
flush_cached_frames ();
}
static void
-print_fpu_flags (flags)
- int flags;
+print_fpu_flags (int flags)
{
if (flags & (1 << 0))
fputs ("IVO ", stdout);
}
void
-arm_float_info ()
+arm_float_info (void)
{
register unsigned long status = read_register (FPS_REGNUM);
int type;
type = (status >> 24) & 127;
printf ("%s FPU type %d\n",
- (status & (1<<31)) ? "Hardware" : "Software",
+ (status & (1 << 31)) ? "Hardware" : "Software",
type);
fputs ("mask: ", stdout);
print_fpu_flags (status >> 16);
print_fpu_flags (status);
}
-/* If the disassembly mode is APCS, we have to also switch the
- bfd mach_type. This function is run in the set disassembly_flavor
- command, and does that. */
+#if 0
+/* FIXME: The generated assembler works but sucks. Instead of using
+ r0, r1 it pushes them on the stack, then loads them into r3, r4 and
+ uses those registers. I must be missing something. ScottB */
-static void
-set_disassembly_flavor_sfunc (args, from_tty, c)
- char *args;
- int from_tty;
- struct cmd_list_element *c;
+void
+convert_from_extended (void *ptr, void *dbl)
{
- set_disassembly_flavor ();
+ __asm__ ("
+ ldfe f0,[%0]
+ stfd f0,[%1] "
+: /* no output */
+: "r" (ptr), "r" (dbl));
}
+void
+convert_to_extended (void *dbl, void *ptr)
+{
+ __asm__ ("
+ ldfd f0,[%0]
+ stfe f0,[%1] "
+: /* no output */
+: "r" (dbl), "r" (ptr));
+}
+#else
static void
-set_disassembly_flavor ()
+convert_from_extended (void *ptr, void *dbl)
{
- if (disassembly_flavor == apcs_flavor)
- {
- if (arm_toggle_regnames () == 0)
- arm_toggle_regnames ();
- arm_register_names = apcs_register_names;
- }
- else if (disassembly_flavor == r_prefix_flavor)
- {
- if (arm_toggle_regnames () == 1)
- arm_toggle_regnames ();
- arm_register_names = additional_register_names;
- }
+ *(double *) dbl = *(double *) ptr;
+}
+
+void
+convert_to_extended (void *dbl, void *ptr)
+{
+ *(double *) ptr = *(double *) dbl;
}
+#endif
-/* arm_othernames implements the "othernames" command. This is kind of
- hacky, and I prefer the set-show disassembly-flavor which is also used
- for the x86 gdb. I will keep this around, however, in case anyone is
- actually using it. */
+/* Nonzero if register N requires conversion from raw format to
+ virtual format. */
-static void
-arm_othernames ()
+int
+arm_register_convertible (unsigned int regnum)
{
- if (disassembly_flavor == r_prefix_flavor)
- {
- disassembly_flavor = apcs_flavor;
- set_disassembly_flavor ();
- }
- else
- {
- disassembly_flavor = r_prefix_flavor;
- set_disassembly_flavor ();
- }
+ return ((regnum - F0_REGNUM) < 8);
}
-/* FIXME: Fill in with the 'right thing', see asm
- template in arm-convert.s */
+/* Convert data from raw format for register REGNUM in buffer FROM to
+ virtual format with type TYPE in buffer TO. */
void
-convert_from_extended (ptr, dbl)
- void *ptr;
- void *dbl;
+arm_register_convert_to_virtual (unsigned int regnum, struct type *type,
+ void *from, void *to)
{
- *(double *) dbl = *(double *) ptr;
+ double val;
+
+ convert_from_extended (from, &val);
+ store_floating (to, TYPE_LENGTH (type), val);
}
+/* Convert data from virtual format with type TYPE in buffer FROM to
+ raw format for register REGNUM in buffer TO. */
+
void
-convert_to_extended (dbl, ptr)
- void *ptr;
- void *dbl;
+arm_register_convert_to_raw (unsigned int regnum, struct type *type,
+ void *from, void *to)
{
- *(double *) ptr = *(double *) dbl;
+ double val = extract_floating (from, TYPE_LENGTH (type));
+
+ convert_to_extended (&val, to);
}
static int
-condition_true (cond, status_reg)
- unsigned long cond;
- unsigned long status_reg;
+condition_true (unsigned long cond, unsigned long status_reg)
{
if (cond == INST_AL || cond == INST_NV)
return 1;
return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
case INST_GT:
return (((status_reg & FLAG_Z) == 0) &&
- (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
+ (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
case INST_LE:
return (((status_reg & FLAG_Z) != 0) ||
- (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
+ (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
}
return 1;
}
#define ARM_PC_32 1
static unsigned long
-shifted_reg_val (inst, carry, pc_val, status_reg)
- unsigned long inst;
- int carry;
- unsigned long pc_val;
- unsigned long status_reg;
+shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
+ unsigned long status_reg)
{
unsigned long res, shift;
int rm = bits (inst, 0, 3);
return res & 0xffffffff;
}
-
/* Return number of 1-bits in VAL. */
static int
-bitcount (val)
- unsigned long val;
+bitcount (unsigned long val)
{
int nbits;
for (nbits = 0; val != 0; nbits++)
return nbits;
}
-
static CORE_ADDR
-thumb_get_next_pc (pc)
- CORE_ADDR pc;
+thumb_get_next_pc (CORE_ADDR pc)
{
unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
unsigned short inst1 = read_memory_integer (pc, 2);
return nextpc;
}
-
CORE_ADDR
-arm_get_next_pc (pc)
- CORE_ADDR pc;
+arm_get_next_pc (CORE_ADDR pc)
{
unsigned long pc_val;
unsigned long this_instr;
int c = (status & FLAG_C) ? 1 : 0;
unsigned long offset =
(bit (this_instr, 25)
- ? shifted_reg_val (this_instr, c, pc_val)
+ ? shifted_reg_val (this_instr, c, pc_val, status)
: bits (this_instr, 0, 11));
if (bit (this_instr, 23))
#include "libcoff.h"
static int
-gdb_print_insn_arm (memaddr, info)
- bfd_vma memaddr;
- disassemble_info *info;
+gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
{
if (arm_pc_is_thumb (memaddr))
{
return print_insn_little_arm (memaddr, info);
}
-/* Sequence of bytes for breakpoint instruction. */
-#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} /* Recognized illegal opcodes */
-#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
-#define THUMB_LE_BREAKPOINT {0xbe,0xbe}
-#define THUMB_BE_BREAKPOINT {0xbe,0xbe}
-
-/* The following has been superseded by BREAKPOINT_FOR_PC, but
- is defined merely to keep mem-break.c happy. */
-#define LITTLE_BREAKPOINT ARM_LE_BREAKPOINT
-#define BIG_BREAKPOINT ARM_BE_BREAKPOINT
-
-/* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
- counter value to determine whether a 16- or 32-bit breakpoint should be
- used. It returns a pointer to a string of bytes that encode a breakpoint
- instruction, stores the length of the string to *lenptr, and adjusts pc
- (if necessary) to point to the actual memory location where the
+/* This function implements the BREAKPOINT_FROM_PC macro. It uses the
+ program counter value to determine whether a 16-bit or 32-bit
+ breakpoint should be used. It returns a pointer to a string of
+ bytes that encode a breakpoint instruction, stores the length of
+ the string to *lenptr, and adjusts the program counter (if
+ necessary) to point to the actual memory location where the
breakpoint should be inserted. */
unsigned char *
-arm_breakpoint_from_pc (pcptr, lenptr)
- CORE_ADDR *pcptr;
- int *lenptr;
+arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
{
if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
{
}
}
}
-/* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
- This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
+
+/* Extract from an array REGBUF containing the (raw) register state a
+ function return value of type TYPE, and copy that, in virtual
+ format, into VALBUF. */
+
+void
+arm_extract_return_value (struct type *type,
+ char regbuf[REGISTER_BYTES],
+ char *valbuf)
+{
+ if (TYPE_CODE_FLT == TYPE_CODE (type))
+ convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf);
+ else
+ memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type));
+}
+
+/* Return non-zero if the PC is inside a thumb call thunk. */
int
-arm_in_call_stub (pc, name)
- CORE_ADDR pc;
- char *name;
+arm_in_call_stub (CORE_ADDR pc, char *name)
{
CORE_ADDR start_addr;
- /* Find the starting address of the function containing the PC. If the
- caller didn't give us a name, look it up at the same time. */
+ /* Find the starting address of the function containing the PC. If
+ the caller didn't give us a name, look it up at the same time. */
if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
return 0;
return strncmp (name, "_call_via_r", 11) == 0;
}
-
-/* If PC is in a Thumb call or return stub, return the address of the target
- PC, which is in a register. The thunk functions are called _called_via_xx,
- where x is the register name. The possible names are r0-r9, sl, fp, ip,
- sp, and lr. */
+/* If PC is in a Thumb call or return stub, return the address of the
+ target PC, which is in a register. The thunk functions are called
+ _called_via_xx, where x is the register name. The possible names
+ are r0-r9, sl, fp, ip, sp, and lr. */
CORE_ADDR
-arm_skip_stub (pc)
- CORE_ADDR pc;
+arm_skip_stub (CORE_ADDR pc)
{
char *name;
CORE_ADDR start_addr;
/* Call thunks always start with "_call_via_". */
if (strncmp (name, "_call_via_", 10) == 0)
{
- /* Use the name suffix to determine which register contains
- the target PC. */
+ /* Use the name suffix to determine which register contains the
+ target PC. */
static char *table[15] =
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "sl", "fp", "ip", "sp", "lr"
if (strcmp (&name[10], table[regno]) == 0)
return read_register (regno);
}
+
return 0; /* not a stub */
}
+/* If the user changes the register disassembly flavor used for info register
+ and other commands, we have to also switch the flavor used in opcodes
+ for disassembly output.
+ This function is run in the set disassembly_flavor command, and does that. */
+
+static void
+set_disassembly_flavor_sfunc (char *args, int from_tty,
+ struct cmd_list_element *c)
+{
+ set_disassembly_flavor ();
+}
+\f
+static void
+set_disassembly_flavor (void)
+{
+ const char *setname, *setdesc, **regnames;
+ int numregs, j;
+
+ /* Find the flavor that the user wants in the opcodes table. */
+ int current = 0;
+ numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
+ while ((disassembly_flavor != setname)
+ && (current < num_flavor_options))
+ get_arm_regnames (++current, &setname, &setdesc, ®names);
+ current_option = current;
+
+ /* Fill our copy. */
+ for (j = 0; j < numregs; j++)
+ arm_register_names[j] = (char *) regnames[j];
+
+ /* Adjust case. */
+ if (isupper (*regnames[PC_REGNUM]))
+ {
+ arm_register_names[FPS_REGNUM] = "FPS";
+ arm_register_names[PS_REGNUM] = "CPSR";
+ }
+ else
+ {
+ arm_register_names[FPS_REGNUM] = "fps";
+ arm_register_names[PS_REGNUM] = "cpsr";
+ }
+
+ /* Synchronize the disassembler. */
+ set_arm_regname_option (current);
+}
+
+/* arm_othernames implements the "othernames" command. This is kind
+ of hacky, and I prefer the set-show disassembly-flavor which is
+ also used for the x86 gdb. I will keep this around, however, in
+ case anyone is actually using it. */
+
+static void
+arm_othernames (char *names, int n)
+{
+ /* Circle through the various flavors. */
+ current_option = (current_option + 1) % num_flavor_options;
+
+ disassembly_flavor = valid_flavors[current_option];
+ set_disassembly_flavor ();
+}
void
-_initialize_arm_tdep ()
+_initialize_arm_tdep (void)
{
+ struct ui_file *stb;
+ long length;
struct cmd_list_element *new_cmd;
+ const char *setname;
+ const char *setdesc;
+ const char **regnames;
+ int numregs, i, j;
+ static char *helptext;
tm_print_insn = gdb_print_insn_arm;
-
+
+ /* Get the number of possible sets of register names defined in opcodes. */
+ num_flavor_options = get_arm_regname_num_options ();
+
/* Sync the opcode insn printer with our register viewer: */
+ parse_arm_disassembler_option ("reg-names-std");
- if (arm_toggle_regnames () != 1)
- arm_toggle_regnames ();
+ /* Begin creating the help text. */
+ stb = mem_fileopen ();
+ fprintf_unfiltered (stb, "Set the disassembly flavor.\n\
+The valid values are:\n");
- /* Add the deprecated "othernames" command */
-
- add_com ("othernames", class_obscure, arm_othernames,
- "Switch to the other set of register names.");
+ /* Initialize the array that will be passed to add_set_enum_cmd(). */
+ valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *));
+ for (i = 0; i < num_flavor_options; i++)
+ {
+ numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
+ valid_flavors[i] = setname;
+ fprintf_unfiltered (stb, "%s - %s\n", setname,
+ setdesc);
+ /* Copy the default names (if found) and synchronize disassembler. */
+ if (!strcmp (setname, "std"))
+ {
+ disassembly_flavor = setname;
+ current_option = i;
+ for (j = 0; j < numregs; j++)
+ arm_register_names[j] = (char *) regnames[j];
+ set_arm_regname_option (i);
+ }
+ }
+ /* Mark the end of valid options. */
+ valid_flavors[num_flavor_options] = NULL;
+
+ /* Finish the creation of the help text. */
+ fprintf_unfiltered (stb, "The default is \"std\".");
+ helptext = ui_file_xstrdup (stb, &length);
+ ui_file_delete (stb);
/* Add the disassembly-flavor command */
-
new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
- valid_flavors,
- (char *) &disassembly_flavor,
- "Set the disassembly flavor, \
-the valid values are \"apcs\" and \"r-prefix\", \
-and the default value is \"apcs\".",
- &setlist);
+ valid_flavors,
+ &disassembly_flavor,
+ helptext,
+ &setlist);
new_cmd->function.sfunc = set_disassembly_flavor_sfunc;
- add_show_from_set(new_cmd, &showlist);
-
+ add_show_from_set (new_cmd, &showlist);
+
/* ??? Maybe this should be a boolean. */
add_show_from_set (add_set_cmd ("apcs32", no_class,
- var_zinteger, (char *)&arm_apcs_32,
+ var_zinteger, (char *) &arm_apcs_32,
"Set usage of ARM 32-bit mode.\n", &setlist),
- & showlist);
+ &showlist);
+ /* Add the deprecated "othernames" command */
+
+ add_com ("othernames", class_obscure, arm_othernames,
+ "Switch to the next set of register names.");
}
-/* Test whether the coff symbol specific value corresponds to a Thumb function */
+/* Test whether the coff symbol specific value corresponds to a Thumb
+ function. */
+
int
coff_sym_is_thumb (int val)
{
projects / deliverable / binutils-gdb.git / blobdiff