/* Common target dependent code for GDB on ARM systems.
Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
- 2001, 2002 Free Software Foundation, Inc.
+ 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
This file is part of GDB.
#include "inferior.h"
#include "gdbcmd.h"
#include "gdbcore.h"
-#include "symfile.h"
#include "gdb_string.h"
-#include "dis-asm.h" /* For register flavors. */
+#include "dis-asm.h" /* For register styles. */
#include "regcache.h"
#include "doublest.h"
#include "value.h"
#include "arch-utils.h"
-#include "solib-svr4.h"
+#include "osabi.h"
+#include "frame-unwind.h"
+#include "frame-base.h"
+#include "trad-frame.h"
#include "arm-tdep.h"
+#include "gdb/sim-arm.h"
#include "elf-bfd.h"
#include "coff/internal.h"
+#include "elf/arm.h"
+
+#include "gdb_assert.h"
+
+static int arm_debug;
/* Each OS has a different mechanism for accessing the various
registers stored in the sigcontext structure.
/* Macros for setting and testing a bit in a minimal symbol that marks
it as Thumb function. The MSB of the minimal symbol's "info" field
- is used for this purpose. This field is already being used to store
- the symbol size, so the assumption is that the symbol size cannot
- exceed 2^31.
+ is used for this purpose.
MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
- MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
- MSYMBOL_SIZE Returns the size of the minimal symbol,
- i.e. the "info" field with the "special" bit
- masked out. */
+ MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
#define MSYMBOL_SET_SPECIAL(msym) \
MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
#define MSYMBOL_IS_SPECIAL(msym) \
(((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
-#define MSYMBOL_SIZE(msym) \
- ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
+/* The list of available "set arm ..." and "show arm ..." commands. */
+static struct cmd_list_element *setarmcmdlist = NULL;
+static struct cmd_list_element *showarmcmdlist = NULL;
+
+/* The type of floating-point to use. Keep this in sync with enum
+ arm_float_model, and the help string in _initialize_arm_tdep. */
+static const char *fp_model_strings[] =
+{
+ "auto",
+ "softfpa",
+ "fpa",
+ "softvfp",
+ "vfp"
+};
+
+/* A variable that can be configured by the user. */
+static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
+static const char *current_fp_model = "auto";
-/* Number of different reg name sets (options). */
-static int num_flavor_options;
+/* Number of different reg name sets (options). */
+static int num_disassembly_options;
/* We have more registers than the disassembler as gdb can print the value
of special registers as well.
The general register names are overwritten by whatever is being used by
- the disassembler at the moment. We also adjust the case of cpsr and fps. */
+ the disassembler at the moment. We also adjust the case of cpsr and fps. */
-/* Initial value: Register names used in ARM's ISA documentation. */
+/* Initial value: Register names used in ARM's ISA documentation. */
static char * arm_register_name_strings[] =
{"r0", "r1", "r2", "r3", /* 0 1 2 3 */
"r4", "r5", "r6", "r7", /* 4 5 6 7 */
"r12", "sp", "lr", "pc", /* 12 13 14 15 */
"f0", "f1", "f2", "f3", /* 16 17 18 19 */
"f4", "f5", "f6", "f7", /* 20 21 22 23 */
- "fps", "cpsr" }; /* 24 25 */
+ "fps", "cpsr" }; /* 24 25 */
static char **arm_register_names = arm_register_name_strings;
-/* Valid register name flavors. */
-static const char **valid_flavors;
+/* Valid register name styles. */
+static const char **valid_disassembly_styles;
-/* Disassembly flavor to use. Default to "std" register names. */
-static const char *disassembly_flavor;
-static int current_option; /* Index to that option in the opcodes table. */
+/* Disassembly style to use. Default to "std" register names. */
+static const char *disassembly_style;
+/* Index to that option in the opcodes table. */
+static int current_option;
/* This is used to keep the bfd arch_info in sync with the disassembly
- flavor. */
-static void set_disassembly_flavor_sfunc(char *, int,
+ style. */
+static void set_disassembly_style_sfunc(char *, int,
struct cmd_list_element *);
-static void set_disassembly_flavor (void);
+static void set_disassembly_style (void);
-static void convert_from_extended (void *ptr, void *dbl);
+static void convert_from_extended (const struct floatformat *, const void *,
+ void *);
+static void convert_to_extended (const struct floatformat *, void *,
+ const void *);
-/* Define other aspects of the stack frame. We keep the offsets of
- all saved registers, 'cause we need 'em a lot! We also keep the
- current size of the stack frame, and the offset of the frame
- pointer from the stack pointer (for frameless functions, and when
- we're still in the prologue of a function with a frame) */
-
-struct frame_extra_info
+struct arm_prologue_cache
{
+ /* The stack pointer at the time this frame was created; i.e. the
+ caller's stack pointer when this function was called. It is used
+ to identify this frame. */
+ CORE_ADDR prev_sp;
+
+ /* The frame base for this frame is just prev_sp + frame offset -
+ frame size. FRAMESIZE is the size of this stack frame, and
+ FRAMEOFFSET if the initial offset from the stack pointer (this
+ frame's stack pointer, not PREV_SP) to the frame base. */
+
int framesize;
int frameoffset;
+
+ /* The register used to hold the frame pointer for this frame. */
int framereg;
+
+ /* Saved register offsets. */
+ struct trad_frame_saved_reg *saved_regs;
};
/* Addresses for calling Thumb functions have the bit 0 set.
#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
-/* Will a function return an aggregate type in memory or in a
- register? Return 0 if an aggregate type can be returned in a
- register, 1 if it must be returned in memory. */
-
-int
-arm_use_struct_convention (int gcc_p, struct type *type)
-{
- int nRc;
- register enum type_code code;
-
- /* In the ARM ABI, "integer" like aggregate types are returned in
- registers. For an aggregate type to be integer like, its size
- must be less than or equal to REGISTER_SIZE and the offset of
- each addressable subfield must be zero. Note that bit fields are
- not addressable, and all addressable subfields of unions always
- start at offset zero.
-
- This function is based on the behaviour of GCC 2.95.1.
- See: gcc/arm.c: arm_return_in_memory() for details.
-
- Note: All versions of GCC before GCC 2.95.2 do not set up the
- parameters correctly for a function returning the following
- structure: struct { float f;}; This should be returned in memory,
- not a register. Richard Earnshaw sent me a patch, but I do not
- know of any way to detect if a function like the above has been
- compiled with the correct calling convention. */
-
- /* All aggregate types that won't fit in a register must be returned
- in memory. */
- if (TYPE_LENGTH (type) > REGISTER_SIZE)
- {
- return 1;
- }
-
- /* The only aggregate types that can be returned in a register are
- structs and unions. Arrays must be returned in memory. */
- code = TYPE_CODE (type);
- if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
- {
- return 1;
- }
-
- /* Assume all other aggregate types can be returned in a register.
- Run a check for structures, unions and arrays. */
- nRc = 0;
-
- if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
- {
- int i;
- /* Need to check if this struct/union is "integer" like. For
- this to be true, its size must be less than or equal to
- REGISTER_SIZE and the offset of each addressable subfield
- must be zero. Note that bit fields are not addressable, and
- unions always start at offset zero. If any of the subfields
- is a floating point type, the struct/union cannot be an
- integer type. */
-
- /* For each field in the object, check:
- 1) Is it FP? --> yes, nRc = 1;
- 2) Is it addressable (bitpos != 0) and
- not packed (bitsize == 0)?
- --> yes, nRc = 1
- */
-
- for (i = 0; i < TYPE_NFIELDS (type); i++)
- {
- enum type_code field_type_code;
- field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
-
- /* Is it a floating point type field? */
- if (field_type_code == TYPE_CODE_FLT)
- {
- nRc = 1;
- break;
- }
-
- /* If bitpos != 0, then we have to care about it. */
- if (TYPE_FIELD_BITPOS (type, i) != 0)
- {
- /* Bitfields are not addressable. If the field bitsize is
- zero, then the field is not packed. Hence it cannot be
- a bitfield or any other packed type. */
- if (TYPE_FIELD_BITSIZE (type, i) == 0)
- {
- nRc = 1;
- break;
- }
- }
- }
- }
-
- return nRc;
-}
-
-static int
-arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
-{
- return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC));
-}
-
-/* Set to true if the 32-bit mode is in use. */
+/* Set to true if the 32-bit mode is in use. */
int arm_apcs_32 = 1;
We hope the current stack pointer is not so far alway from the dummy
frame location (true if we have not pushed large data structures or
gone too many levels deep) and that our 1024 is not enough to consider
- code regions as part of the stack (true for most practical purposes) */
- if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
+ code regions as part of the stack (true for most practical purposes). */
+ if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
return caller_is_thumb;
else
return 0;
static CORE_ADDR
arm_addr_bits_remove (CORE_ADDR val)
{
- if (arm_pc_is_thumb (val))
- return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe));
+ if (arm_apcs_32)
+ return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
else
- return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc));
+ return (val & 0x03fffffc);
}
/* When reading symbols, we need to zap the low bit of the address,
stmdb sp!, {}
sub sp, ip, #4. */
- func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET);
+ func_start = (get_frame_func (fi) + FUNCTION_START_OFFSET);
after_prologue = SKIP_PROLOGUE (func_start);
/* There are some frameless functions whose first two instructions
follow the standard APCS form, in which case after_prologue will
- be func_start + 8. */
+ be func_start + 8. */
frameless = (after_prologue < func_start + 12);
return frameless;
}
-/* The address of the arguments in the frame. */
-static CORE_ADDR
-arm_frame_args_address (struct frame_info *fi)
-{
- return fi->frame;
-}
-
-/* The address of the local variables in the frame. */
-static CORE_ADDR
-arm_frame_locals_address (struct frame_info *fi)
-{
- return fi->frame;
-}
-
-/* The number of arguments being passed in the frame. */
-static int
-arm_frame_num_args (struct frame_info *fi)
-{
- /* We have no way of knowing. */
- return -1;
-}
-
/* A typical Thumb prologue looks like this:
push {r7, lr}
add sp, sp, #-28
thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
{
CORE_ADDR current_pc;
- int findmask = 0; /* findmask:
- bit 0 - push { rlist }
- bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
- bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
- */
-
- for (current_pc = pc; current_pc + 2 < func_end && current_pc < pc + 40; current_pc += 2)
+ /* findmask:
+ bit 0 - push { rlist }
+ bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
+ bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
+ */
+ int findmask = 0;
+
+ for (current_pc = pc;
+ current_pc + 2 < func_end && current_pc < pc + 40;
+ current_pc += 2)
{
unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
- if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
+ if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
{
- findmask |= 1; /* push found */
+ findmask |= 1; /* push found */
}
- else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
+ else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
+ sub sp, #simm */
{
- if ((findmask & 1) == 0) /* before push ? */
+ if ((findmask & 1) == 0) /* before push ? */
continue;
else
- findmask |= 4; /* add/sub sp found */
+ findmask |= 4; /* add/sub sp found */
}
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
{
- findmask |= 2; /* setting of r7 found */
+ findmask |= 2; /* setting of r7 found */
}
else if (insn == 0x466f) /* mov r7, sp */
{
- findmask |= 2; /* setting of r7 found */
+ findmask |= 2; /* setting of r7 found */
}
else if (findmask == (4+2+1))
{
- break; /* We have found one of each type of prologue instruction */
+ /* We have found one of each type of prologue instruction */
+ break;
}
else
- continue; /* something in the prolog that we don't care about or some
- instruction from outside the prolog scheduled here for optimization */
+ /* Something in the prolog that we don't care about or some
+ instruction from outside the prolog scheduled here for
+ optimization. */
+ continue;
}
return current_pc;
}
-/* Advance the PC across any function entry prologue instructions to reach
- some "real" code.
+/* Advance the PC across any function entry prologue instructions to
+ reach some "real" code.
The APCS (ARM Procedure Call Standard) defines the following
prologue:
{
unsigned long inst;
CORE_ADDR skip_pc;
- CORE_ADDR func_addr, func_end;
+ CORE_ADDR func_addr, func_end = 0;
char *func_name;
struct symtab_and_line sal;
+ /* If we're in a dummy frame, don't even try to skip the prologue. */
+ if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
+ return pc;
+
/* See what the symbol table says. */
if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
struct symbol *sym;
/* Found a function. */
- sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL);
+ sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
{
- /* Don't use this trick for assembly source files. */
+ /* Don't use this trick for assembly source files. */
sal = find_pc_line (func_addr, 0);
if ((sal.line != 0) && (sal.end < func_end))
return sal.end;
return thumb_skip_prologue (pc, func_end);
/* Can't find the prologue end in the symbol table, try it the hard way
- by disassembling the instructions. */
- skip_pc = pc;
- inst = read_memory_integer (skip_pc, 4);
- if (inst != 0xe1a0c00d) /* mov ip, sp */
- return pc;
+ by disassembling the instructions. */
- skip_pc += 4;
- inst = read_memory_integer (skip_pc, 4);
- if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
+ /* Like arm_scan_prologue, stop no later than pc + 64. */
+ if (func_end == 0 || func_end > pc + 64)
+ func_end = pc + 64;
+
+ for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
{
- skip_pc += 4;
inst = read_memory_integer (skip_pc, 4);
- }
- if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
- return pc;
+ /* "mov ip, sp" is no longer a required part of the prologue. */
+ if (inst == 0xe1a0c00d) /* mov ip, sp */
+ continue;
- skip_pc += 4;
- inst = read_memory_integer (skip_pc, 4);
+ if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
+ continue;
- /* Any insns after this point may float into the code, if it makes
- for better instruction scheduling, so we skip them only if we
- find them, but still consdier the function to be frame-ful. */
+ if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
+ continue;
- /* We may have either one sfmfd instruction here, or several stfe
- insns, depending on the version of floating point code we
- support. */
- if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
- {
- skip_pc += 4;
- inst = read_memory_integer (skip_pc, 4);
- }
- else
- {
- while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
- {
- skip_pc += 4;
- inst = read_memory_integer (skip_pc, 4);
- }
- }
+ /* Some prologues begin with "str lr, [sp, #-4]!". */
+ if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
+ continue;
+
+ if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
+ continue;
+
+ if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
+ continue;
+
+ /* Any insns after this point may float into the code, if it makes
+ for better instruction scheduling, so we skip them only if we
+ find them, but still consider the function to be frame-ful. */
+
+ /* We may have either one sfmfd instruction here, or several stfe
+ insns, depending on the version of floating point code we
+ support. */
+ if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
+ continue;
+
+ if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
+ continue;
+
+ if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
+ continue;
- if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
- skip_pc += 4;
+ if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
+ continue;
+
+ if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
+ (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
+ (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
+ continue;
+
+ if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
+ (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
+ (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
+ continue;
+
+ /* Un-recognized instruction; stop scanning. */
+ break;
+ }
- return skip_pc;
+ return skip_pc; /* End of prologue */
}
+
/* *INDENT-OFF* */
/* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
This function decodes a Thumb function prologue to determine:
2) which registers are saved on it
3) the offsets of saved regs
4) the offset from the stack pointer to the frame pointer
- This information is stored in the "extra" fields of the frame_info.
A typical Thumb function prologue would create this stack frame
(offsets relative to FP)
The frame size would thus be 36 bytes, and the frame offset would be
12 bytes. The frame register is R7.
- The comments for thumb_skip_prolog() describe the algorithm we use to detect
- the end of the prolog */
+ The comments for thumb_skip_prolog() describe the algorithm we use
+ to detect the end of the prolog. */
/* *INDENT-ON* */
static void
-thumb_scan_prologue (struct frame_info *fi)
+thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
{
CORE_ADDR prologue_start;
CORE_ADDR prologue_end;
CORE_ADDR current_pc;
- int saved_reg[16]; /* which register has been copied to register n? */
- int findmask = 0; /* findmask:
- bit 0 - push { rlist }
- bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
- bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
- */
+ /* Which register has been copied to register n? */
+ int saved_reg[16];
+ /* findmask:
+ bit 0 - push { rlist }
+ bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
+ bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
+ */
+ int findmask = 0;
int i;
- if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
+ if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
{
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
- if (sal.line == 0) /* no line info, use current PC */
- prologue_end = fi->pc;
+ if (sal.line == 0) /* no line info, use current PC */
+ prologue_end = prev_pc;
else if (sal.end < prologue_end) /* next line begins after fn end */
- prologue_end = sal.end; /* (probably means no prologue) */
+ prologue_end = sal.end; /* (probably means no prologue) */
}
else
- prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */
- /* 16 pushes, an add, and "mv fp,sp" */
+ /* We're in the boondocks: allow for
+ 16 pushes, an add, and "mv fp,sp". */
+ prologue_end = prologue_start + 40;
- prologue_end = min (prologue_end, fi->pc);
+ prologue_end = min (prologue_end, prev_pc);
/* Initialize the saved register map. When register H is copied to
register L, we will put H in saved_reg[L]. */
frame pointer, adjust the stack pointer, and save registers.
Do this until all basic prolog instructions are found. */
- fi->extra_info->framesize = 0;
+ cache->framesize = 0;
for (current_pc = prologue_start;
(current_pc < prologue_end) && ((findmask & 7) != 7);
current_pc += 2)
if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
{
int mask;
- findmask |= 1; /* push found */
+ findmask |= 1; /* push found */
/* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
whether to save LR (R14). */
mask = (insn & 0xff) | ((insn & 0x100) << 6);
- /* Calculate offsets of saved R0-R7 and LR. */
+ /* Calculate offsets of saved R0-R7 and LR. */
for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
if (mask & (1 << regno))
{
- fi->extra_info->framesize += 4;
- fi->saved_regs[saved_reg[regno]] =
- -(fi->extra_info->framesize);
- saved_reg[regno] = regno; /* reset saved register map */
+ cache->framesize += 4;
+ cache->saved_regs[saved_reg[regno]].addr = -cache->framesize;
+ /* Reset saved register map. */
+ saved_reg[regno] = regno;
}
}
- else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
+ else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
+ sub sp, #simm */
{
- if ((findmask & 1) == 0) /* before push ? */
+ if ((findmask & 1) == 0) /* before push? */
continue;
else
- findmask |= 4; /* add/sub sp found */
+ findmask |= 4; /* add/sub sp found */
- offset = (insn & 0x7f) << 2; /* get scaled offset */
- if (insn & 0x80) /* is it signed? (==subtracting) */
+ offset = (insn & 0x7f) << 2; /* get scaled offset */
+ if (insn & 0x80) /* is it signed? (==subtracting) */
{
- fi->extra_info->frameoffset += offset;
+ cache->frameoffset += offset;
offset = -offset;
}
- fi->extra_info->framesize -= offset;
+ cache->framesize -= offset;
}
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
{
- findmask |= 2; /* setting of r7 found */
- fi->extra_info->framereg = THUMB_FP_REGNUM;
+ findmask |= 2; /* setting of r7 found */
+ cache->framereg = THUMB_FP_REGNUM;
/* get scaled offset */
- fi->extra_info->frameoffset = (insn & 0xff) << 2;
+ cache->frameoffset = (insn & 0xff) << 2;
}
else if (insn == 0x466f) /* mov r7, sp */
{
- findmask |= 2; /* setting of r7 found */
- fi->extra_info->framereg = THUMB_FP_REGNUM;
- fi->extra_info->frameoffset = 0;
+ findmask |= 2; /* setting of r7 found */
+ cache->framereg = THUMB_FP_REGNUM;
+ cache->frameoffset = 0;
saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
}
else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
{
- int lo_reg = insn & 7; /* dest. register (r0-r7) */
+ int lo_reg = insn & 7; /* dest. register (r0-r7) */
int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
- saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
+ saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
}
else
- continue; /* something in the prolog that we don't care about or some
- instruction from outside the prolog scheduled here for optimization */
- }
-}
-
-/* Check if prologue for this frame's PC has already been scanned. If
- it has, copy the relevant information about that prologue and
- return non-zero. Otherwise do not copy anything and return zero.
-
- The information saved in the cache includes:
- * the frame register number;
- * the size of the stack frame;
- * the offsets of saved regs (relative to the old SP); and
- * the offset from the stack pointer to the frame pointer
-
- The cache contains only one entry, since this is adequate for the
- typical sequence of prologue scan requests we get. When performing
- a backtrace, GDB will usually ask to scan the same function twice
- in a row (once to get the frame chain, and once to fill in the
- extra frame information). */
-
-static struct frame_info prologue_cache;
-
-static int
-check_prologue_cache (struct frame_info *fi)
-{
- int i;
-
- if (fi->pc == prologue_cache.pc)
- {
- fi->extra_info->framereg = prologue_cache.extra_info->framereg;
- fi->extra_info->framesize = prologue_cache.extra_info->framesize;
- fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset;
- for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
- fi->saved_regs[i] = prologue_cache.saved_regs[i];
- return 1;
+ /* Something in the prolog that we don't care about or some
+ instruction from outside the prolog scheduled here for
+ optimization. */
+ continue;
}
- else
- return 0;
-}
-
-
-/* Copy the prologue information from fi to the prologue cache. */
-
-static void
-save_prologue_cache (struct frame_info *fi)
-{
- int i;
-
- prologue_cache.pc = fi->pc;
- prologue_cache.extra_info->framereg = fi->extra_info->framereg;
- prologue_cache.extra_info->framesize = fi->extra_info->framesize;
- prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset;
-
- for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
- prologue_cache.saved_regs[i] = fi->saved_regs[i];
}
-
/* This function decodes an ARM function prologue to determine:
1) the size of the stack frame
2) which registers are saved on it
*/
static void
-arm_scan_prologue (struct frame_info *fi)
+arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache)
{
- int regno, sp_offset, fp_offset;
- LONGEST return_value;
+ int regno, sp_offset, fp_offset, ip_offset;
CORE_ADDR prologue_start, prologue_end, current_pc;
-
- /* Check if this function is already in the cache of frame information. */
- if (check_prologue_cache (fi))
- return;
+ CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
/* Assume there is no frame until proven otherwise. */
- fi->extra_info->framereg = ARM_SP_REGNUM;
- fi->extra_info->framesize = 0;
- fi->extra_info->frameoffset = 0;
+ cache->framereg = ARM_SP_REGNUM;
+ cache->framesize = 0;
+ cache->frameoffset = 0;
/* Check for Thumb prologue. */
- if (arm_pc_is_thumb (fi->pc))
+ if (arm_pc_is_thumb (prev_pc))
{
- thumb_scan_prologue (fi);
- save_prologue_cache (fi);
+ thumb_scan_prologue (prev_pc, cache);
return;
}
/* Find the function prologue. If we can't find the function in
the symbol table, peek in the stack frame to find the PC. */
- if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end))
+ if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
{
/* One way to find the end of the prologue (which works well
for unoptimized code) is to do the following:
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
if (sal.line == 0)
- prologue_end = fi->pc;
+ prologue_end = prev_pc;
else if (sal.end < prologue_end)
prologue_end = sal.end;
is a suitable endpoint since it accounts for the largest
possible prologue plus up to five instructions inserted by
- the scheduler. */
+ the scheduler. */
if (prologue_end > prologue_start + 64)
{
- prologue_end = prologue_start + 64; /* See above. */
+ prologue_end = prologue_start + 64; /* See above. */
}
}
else
{
- /* Get address of the stmfd in the prologue of the callee; the saved
- PC is the address of the stmfd + 8. */
- if (!safe_read_memory_integer (fi->frame, 4, &return_value))
+ /* We have no symbol information. Our only option is to assume this
+ function has a standard stack frame and the normal frame register.
+ Then, we can find the value of our frame pointer on entrance to
+ the callee (or at the present moment if this is the innermost frame).
+ The value stored there should be the address of the stmfd + 8. */
+ CORE_ADDR frame_loc;
+ LONGEST return_value;
+
+ frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
+ if (!safe_read_memory_integer (frame_loc, 4, &return_value))
return;
else
{
prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
- prologue_end = prologue_start + 64; /* See above. */
+ prologue_end = prologue_start + 64; /* See above. */
}
}
+ if (prev_pc < prologue_end)
+ prologue_end = prev_pc;
+
/* Now search the prologue looking for instructions that set up the
frame pointer, adjust the stack pointer, and save registers.
Be careful, however, and if it doesn't look like a prologue,
don't try to scan it. If, for instance, a frameless function
begins with stmfd sp!, then we will tell ourselves there is
- a frame, which will confuse stack traceback, as well ad"finish"
+ a frame, which will confuse stack traceback, as well as "finish"
and other operations that rely on a knowledge of the stack
traceback.
In the APCS, the prologue should start with "mov ip, sp" so
- if we don't see this as the first insn, we will stop. [Note:
- This doesn't seem to be true any longer, so it's now an optional
- part of the prologue. - Kevin Buettner, 2001-11-20] */
+ if we don't see this as the first insn, we will stop.
- sp_offset = fp_offset = 0;
+ [Note: This doesn't seem to be true any longer, so it's now an
+ optional part of the prologue. - Kevin Buettner, 2001-11-20]
- if (read_memory_unsigned_integer (prologue_start, 4)
- == 0xe1a0c00d) /* mov ip, sp */
- current_pc = prologue_start + 4;
- else
- current_pc = prologue_start;
+ [Note further: The "mov ip,sp" only seems to be missing in
+ frameless functions at optimization level "-O2" or above,
+ in which case it is often (but not always) replaced by
+ "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
- for (; current_pc < prologue_end; current_pc += 4)
+ sp_offset = fp_offset = ip_offset = 0;
+
+ for (current_pc = prologue_start;
+ current_pc < prologue_end;
+ current_pc += 4)
{
unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
- if ((insn & 0xffff0000) == 0xe92d0000)
+ if (insn == 0xe1a0c00d) /* mov ip, sp */
+ {
+ ip_offset = 0;
+ continue;
+ }
+ else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
+ {
+ unsigned imm = insn & 0xff; /* immediate value */
+ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
+ imm = (imm >> rot) | (imm << (32 - rot));
+ ip_offset = imm;
+ continue;
+ }
+ else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
+ {
+ unsigned imm = insn & 0xff; /* immediate value */
+ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
+ imm = (imm >> rot) | (imm << (32 - rot));
+ ip_offset = -imm;
+ continue;
+ }
+ else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
+ {
+ sp_offset -= 4;
+ cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
+ continue;
+ }
+ else if ((insn & 0xffff0000) == 0xe92d0000)
/* stmfd sp!, {..., fp, ip, lr, pc}
or
stmfd sp!, {a1, a2, a3, a4} */
{
int mask = insn & 0xffff;
- /* Calculate offsets of saved registers. */
+ /* Calculate offsets of saved registers. */
for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
if (mask & (1 << regno))
{
sp_offset -= 4;
- fi->saved_regs[regno] = sp_offset;
+ cache->saved_regs[regno].addr = sp_offset;
}
}
+ else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
+ (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
+ (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
+ {
+ /* No need to add this to saved_regs -- it's just an arg reg. */
+ continue;
+ }
+ else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
+ (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
+ (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
+ {
+ /* No need to add this to saved_regs -- it's just an arg reg. */
+ continue;
+ }
else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
{
- unsigned imm = insn & 0xff; /* immediate value */
- unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
+ unsigned imm = insn & 0xff; /* immediate value */
+ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
imm = (imm >> rot) | (imm << (32 - rot));
- fp_offset = -imm;
- fi->extra_info->framereg = ARM_FP_REGNUM;
+ fp_offset = -imm + ip_offset;
+ cache->framereg = ARM_FP_REGNUM;
}
else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
{
- unsigned imm = insn & 0xff; /* immediate value */
- unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
+ unsigned imm = insn & 0xff; /* immediate value */
+ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
imm = (imm >> rot) | (imm << (32 - rot));
sp_offset -= imm;
}
{
sp_offset -= 12;
regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
- fi->saved_regs[regno] = sp_offset;
+ cache->saved_regs[regno].addr = sp_offset;
}
else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
{
int n_saved_fp_regs;
unsigned int fp_start_reg, fp_bound_reg;
- if ((insn & 0x800) == 0x800) /* N0 is set */
+ if ((insn & 0x800) == 0x800) /* N0 is set */
{
if ((insn & 0x40000) == 0x40000) /* N1 is set */
n_saved_fp_regs = 3;
for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
{
sp_offset -= 12;
- fi->saved_regs[fp_start_reg++] = sp_offset;
+ cache->saved_regs[fp_start_reg++].addr = sp_offset;
}
}
else if ((insn & 0xf0000000) != 0xe0000000)
- break; /* Condition not true, exit early */
- else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
- break; /* Don't scan past a block load */
+ break; /* Condition not true, exit early */
+ else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
+ break; /* Don't scan past a block load */
else
/* The optimizer might shove anything into the prologue,
- so we just skip what we don't recognize. */
+ so we just skip what we don't recognize. */
continue;
}
- /* The frame size is just the negative of the offset (from the original SP)
- of the last thing thing we pushed on the stack. The frame offset is
- [new FP] - [new SP]. */
- fi->extra_info->framesize = -sp_offset;
- if (fi->extra_info->framereg == ARM_FP_REGNUM)
- fi->extra_info->frameoffset = fp_offset - sp_offset;
+ /* The frame size is just the negative of the offset (from the
+ original SP) of the last thing thing we pushed on the stack.
+ The frame offset is [new FP] - [new SP]. */
+ cache->framesize = -sp_offset;
+ if (cache->framereg == ARM_FP_REGNUM)
+ cache->frameoffset = fp_offset - sp_offset;
else
- fi->extra_info->frameoffset = 0;
-
- save_prologue_cache (fi);
+ cache->frameoffset = 0;
}
-/* Find REGNUM on the stack. Otherwise, it's in an active register.
- One thing we might want to do here is to check REGNUM against the
- clobber mask, and somehow flag it as invalid if it isn't saved on
- the stack somewhere. This would provide a graceful failure mode
- when trying to get the value of caller-saves registers for an inner
- frame. */
-
-static CORE_ADDR
-arm_find_callers_reg (struct frame_info *fi, int regnum)
+static struct arm_prologue_cache *
+arm_make_prologue_cache (struct frame_info *next_frame)
{
- for (; fi; fi = fi->next)
+ int reg;
+ struct arm_prologue_cache *cache;
+ CORE_ADDR unwound_fp;
-#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
- if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
- return generic_read_register_dummy (fi->pc, fi->frame, regnum);
- else
-#endif
- if (fi->saved_regs[regnum] != 0)
- return read_memory_integer (fi->saved_regs[regnum],
- REGISTER_RAW_SIZE (regnum));
- return read_register (regnum);
+ cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
+ cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
+
+ arm_scan_prologue (next_frame, cache);
+
+ unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
+ if (unwound_fp == 0)
+ return cache;
+
+ cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
+
+ /* Calculate actual addresses of saved registers using offsets
+ determined by arm_scan_prologue. */
+ for (reg = 0; reg < NUM_REGS; reg++)
+ if (trad_frame_addr_p (cache->saved_regs, reg))
+ cache->saved_regs[reg].addr += cache->prev_sp;
+
+ return cache;
}
-/* Function: frame_chain Given a GDB frame, determine the address of
- the calling function's frame. This will be used to create a new
- GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
- will be called for the new frame. For ARM, we save the frame size
- when we initialize the frame_info. */
-static CORE_ADDR
-arm_frame_chain (struct frame_info *fi)
+/* Our frame ID for a normal frame is the current function's starting PC
+ and the caller's SP when we were called. */
+
+static void
+arm_prologue_this_id (struct frame_info *next_frame,
+ void **this_cache,
+ struct frame_id *this_id)
{
-#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
- CORE_ADDR fn_start, callers_pc, fp;
+ struct arm_prologue_cache *cache;
+ struct frame_id id;
+ CORE_ADDR func;
- /* is this a dummy frame? */
- if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
- return fi->frame; /* dummy frame same as caller's frame */
+ if (*this_cache == NULL)
+ *this_cache = arm_make_prologue_cache (next_frame);
+ cache = *this_cache;
- /* is caller-of-this a dummy frame? */
- callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */
- fp = arm_find_callers_reg (fi, ARM_FP_REGNUM);
- if (PC_IN_CALL_DUMMY (callers_pc, fp, fp))
- return fp; /* dummy frame's frame may bear no relation to ours */
+ func = frame_func_unwind (next_frame);
- if (find_pc_partial_function (fi->pc, 0, &fn_start, 0))
- if (fn_start == entry_point_address ())
- return 0; /* in _start fn, don't chain further */
-#endif
- CORE_ADDR caller_pc, fn_start;
- int framereg = fi->extra_info->framereg;
+ /* This is meant to halt the backtrace at "_start". Make sure we
+ don't halt it at a generic dummy frame. */
+ if (func <= LOWEST_PC)
+ return;
- if (fi->pc < LOWEST_PC)
- return 0;
+ /* If we've hit a wall, stop. */
+ if (cache->prev_sp == 0)
+ return;
- /* If the caller is the startup code, we're at the end of the chain. */
- caller_pc = FRAME_SAVED_PC (fi);
- if (find_pc_partial_function (caller_pc, 0, &fn_start, 0))
- if (fn_start == entry_point_address ())
- return 0;
+ id = frame_id_build (cache->prev_sp, func);
- /* If the caller is Thumb and the caller is ARM, or vice versa,
- the frame register of the caller is different from ours.
- So we must scan the prologue of the caller to determine its
- frame register number. */
- /* XXX Fixme, we should try to do this without creating a temporary
- caller_fi. */
- if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc))
- {
- struct frame_info caller_fi;
- struct cleanup *old_chain;
-
- /* Create a temporary frame suitable for scanning the caller's
- prologue. (Ugh.) */
- memset (&caller_fi, 0, sizeof (caller_fi));
- caller_fi.extra_info = (struct frame_extra_info *)
- xcalloc (1, sizeof (struct frame_extra_info));
- old_chain = make_cleanup (xfree, caller_fi.extra_info);
- caller_fi.saved_regs = (CORE_ADDR *)
- xcalloc (1, SIZEOF_FRAME_SAVED_REGS);
- make_cleanup (xfree, caller_fi.saved_regs);
-
- /* Now, scan the prologue and obtain the frame register. */
- caller_fi.pc = caller_pc;
- arm_scan_prologue (&caller_fi);
- framereg = caller_fi.extra_info->framereg;
-
- /* Deallocate the storage associated with the temporary frame
- created above. */
- do_cleanups (old_chain);
- }
+ /* Check that we're not going round in circles with the same frame
+ ID (but avoid applying the test to sentinel frames which do go
+ round in circles). */
+ if (frame_relative_level (next_frame) >= 0
+ && get_frame_type (next_frame) == NORMAL_FRAME
+ && frame_id_eq (get_frame_id (next_frame), id))
+ return;
- /* If the caller used a frame register, return its value.
- Otherwise, return the caller's stack pointer. */
- if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM)
- return arm_find_callers_reg (fi, framereg);
- else
- return fi->frame + fi->extra_info->framesize;
+ *this_id = id;
}
-/* This function actually figures out the frame address for a given pc
- and sp. This is tricky because we sometimes don't use an explicit
- frame pointer, and the previous stack pointer isn't necessarily
- recorded on the stack. The only reliable way to get this info is
- to examine the prologue. FROMLEAF is a little confusing, it means
- this is the next frame up the chain AFTER a frameless function. If
- this is true, then the frame value for this frame is still in the
- fp register. */
-
static void
-arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
+arm_prologue_prev_register (struct frame_info *next_frame,
+ void **this_cache,
+ int prev_regnum,
+ int *optimized,
+ enum lval_type *lvalp,
+ CORE_ADDR *addrp,
+ int *realnump,
+ void *valuep)
{
- int reg;
- CORE_ADDR sp;
+ struct arm_prologue_cache *cache;
+
+ if (*this_cache == NULL)
+ *this_cache = arm_make_prologue_cache (next_frame);
+ cache = *this_cache;
+
+ /* If we are asked to unwind the PC, then we need to return the LR
+ instead. The saved value of PC points into this frame's
+ prologue, not the next frame's resume location. */
+ if (prev_regnum == ARM_PC_REGNUM)
+ prev_regnum = ARM_LR_REGNUM;
+
+ /* SP is generally not saved to the stack, but this frame is
+ identified by NEXT_FRAME's stack pointer at the time of the call.
+ The value was already reconstructed into PREV_SP. */
+ if (prev_regnum == ARM_SP_REGNUM)
+ {
+ *lvalp = not_lval;
+ if (valuep)
+ store_unsigned_integer (valuep, 4, cache->prev_sp);
+ return;
+ }
- if (fi->saved_regs == NULL)
- frame_saved_regs_zalloc (fi);
+ trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum,
+ optimized, lvalp, addrp, realnump, valuep);
+}
- fi->extra_info = (struct frame_extra_info *)
- frame_obstack_alloc (sizeof (struct frame_extra_info));
+struct frame_unwind arm_prologue_unwind = {
+ NORMAL_FRAME,
+ arm_prologue_this_id,
+ arm_prologue_prev_register
+};
- fi->extra_info->framesize = 0;
- fi->extra_info->frameoffset = 0;
- fi->extra_info->framereg = 0;
+static const struct frame_unwind *
+arm_prologue_unwind_sniffer (struct frame_info *next_frame)
+{
+ return &arm_prologue_unwind;
+}
- if (fi->next)
- fi->pc = FRAME_SAVED_PC (fi->next);
+static CORE_ADDR
+arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
+{
+ struct arm_prologue_cache *cache;
- memset (fi->saved_regs, '\000', sizeof fi->saved_regs);
+ if (*this_cache == NULL)
+ *this_cache = arm_make_prologue_cache (next_frame);
+ cache = *this_cache;
-#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
- if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
- {
- /* We need to setup fi->frame here because run_stack_dummy gets it wrong
- by assuming it's always FP. */
- fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
- ARM_SP_REGNUM);
- fi->extra_info->framesize = 0;
- fi->extra_info->frameoffset = 0;
- return;
- }
- else
-#endif
+ return cache->prev_sp + cache->frameoffset - cache->framesize;
+}
- /* Compute stack pointer for this frame. We use this value for both the
- sigtramp and call dummy cases. */
- if (!fi->next)
- sp = read_sp();
- else
- sp = (fi->next->frame - fi->next->extra_info->frameoffset
- + fi->next->extra_info->framesize);
-
- /* Determine whether or not we're in a sigtramp frame.
- Unfortunately, it isn't sufficient to test
- fi->signal_handler_caller because this value is sometimes set
- after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
- fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
- to use the sigcontext addresses for the saved registers.
-
- Note: If an ARM IN_SIGTRAMP method ever needs to compare against
- the name of the function, the code below will have to be changed
- to first fetch the name of the function and then pass this name
- to IN_SIGTRAMP. */
-
- if (SIGCONTEXT_REGISTER_ADDRESS_P ()
- && (fi->signal_handler_caller || IN_SIGTRAMP (fi->pc, (char *)0)))
- {
- for (reg = 0; reg < NUM_REGS; reg++)
- fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg);
+struct frame_base arm_normal_base = {
+ &arm_prologue_unwind,
+ arm_normal_frame_base,
+ arm_normal_frame_base,
+ arm_normal_frame_base
+};
- /* FIXME: What about thumb mode? */
- fi->extra_info->framereg = ARM_SP_REGNUM;
- fi->frame =
- read_memory_integer (fi->saved_regs[fi->extra_info->framereg],
- REGISTER_RAW_SIZE (fi->extra_info->framereg));
- fi->extra_info->framesize = 0;
- fi->extra_info->frameoffset = 0;
+static struct arm_prologue_cache *
+arm_make_sigtramp_cache (struct frame_info *next_frame)
+{
+ struct arm_prologue_cache *cache;
+ int reg;
- }
- else if (PC_IN_CALL_DUMMY (fi->pc, sp, fi->frame))
- {
- CORE_ADDR rp;
- CORE_ADDR callers_sp;
+ cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
- /* Set rp point at the high end of the saved registers. */
- rp = fi->frame - REGISTER_SIZE;
+ cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
- /* Fill in addresses of saved registers. */
- fi->saved_regs[ARM_PS_REGNUM] = rp;
- rp -= REGISTER_RAW_SIZE (ARM_PS_REGNUM);
- for (reg = ARM_PC_REGNUM; reg >= 0; reg--)
- {
- fi->saved_regs[reg] = rp;
- rp -= REGISTER_RAW_SIZE (reg);
- }
+ cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
- callers_sp = read_memory_integer (fi->saved_regs[ARM_SP_REGNUM],
- REGISTER_RAW_SIZE (ARM_SP_REGNUM));
- fi->extra_info->framereg = ARM_FP_REGNUM;
- fi->extra_info->framesize = callers_sp - sp;
- fi->extra_info->frameoffset = fi->frame - sp;
- }
- else
- {
- arm_scan_prologue (fi);
+ for (reg = 0; reg < NUM_REGS; reg++)
+ cache->saved_regs[reg].addr
+ = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp,
+ frame_pc_unwind (next_frame), reg);
- if (!fi->next)
- /* this is the innermost frame? */
- fi->frame = read_register (fi->extra_info->framereg);
- else if (fi->extra_info->framereg == ARM_FP_REGNUM
- || fi->extra_info->framereg == THUMB_FP_REGNUM)
- {
- /* not the innermost frame */
- /* If we have an FP, the callee saved it. */
- if (fi->next->saved_regs[fi->extra_info->framereg] != 0)
- fi->frame =
- read_memory_integer (fi->next
- ->saved_regs[fi->extra_info->framereg], 4);
- else if (fromleaf)
- /* If we were called by a frameless fn. then our frame is
- still in the frame pointer register on the board... */
- fi->frame = read_fp ();
- }
+ /* FIXME: What about thumb mode? */
+ cache->framereg = ARM_SP_REGNUM;
+ cache->prev_sp
+ = read_memory_integer (cache->saved_regs[cache->framereg].addr,
+ DEPRECATED_REGISTER_RAW_SIZE (cache->framereg));
- /* Calculate actual addresses of saved registers using offsets
- determined by arm_scan_prologue. */
- for (reg = 0; reg < NUM_REGS; reg++)
- if (fi->saved_regs[reg] != 0)
- fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize
- - fi->extra_info->frameoffset);
- }
+ return cache;
}
+static void
+arm_sigtramp_this_id (struct frame_info *next_frame,
+ void **this_cache,
+ struct frame_id *this_id)
+{
+ struct arm_prologue_cache *cache;
-/* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
- is saved in the stack anywhere, otherwise we get it from the
- registers.
+ if (*this_cache == NULL)
+ *this_cache = arm_make_sigtramp_cache (next_frame);
+ cache = *this_cache;
- The old definition of this function was a macro:
- #define FRAME_SAVED_PC(FRAME) \
- ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
+ /* FIXME drow/2003-07-07: This isn't right if we single-step within
+ the sigtramp frame; the PC should be the beginning of the trampoline. */
+ *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame));
+}
-static CORE_ADDR
-arm_frame_saved_pc (struct frame_info *fi)
+static void
+arm_sigtramp_prev_register (struct frame_info *next_frame,
+ void **this_cache,
+ int prev_regnum,
+ int *optimized,
+ enum lval_type *lvalp,
+ CORE_ADDR *addrp,
+ int *realnump,
+ void *valuep)
{
-#if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
- if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
- return generic_read_register_dummy (fi->pc, fi->frame, ARM_PC_REGNUM);
- else
-#endif
- if (PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset,
- fi->frame))
- {
- return read_memory_integer (fi->saved_regs[ARM_PC_REGNUM],
- REGISTER_RAW_SIZE (ARM_PC_REGNUM));
- }
- else
- {
- CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM);
- return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
- }
-}
+ struct arm_prologue_cache *cache;
-/* Return the frame address. On ARM, it is R11; on Thumb it is R7.
- Examine the Program Status Register to decide which state we're in. */
+ if (*this_cache == NULL)
+ *this_cache = arm_make_sigtramp_cache (next_frame);
+ cache = *this_cache;
-static CORE_ADDR
-arm_read_fp (void)
-{
- if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
- return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
- else
- return read_register (ARM_FP_REGNUM); /* R11 if ARM */
+ trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum,
+ optimized, lvalp, addrp, realnump, valuep);
}
-/* Store into a struct frame_saved_regs the addresses of the saved
- registers of frame described by FRAME_INFO. This includes special
- registers such as PC and FP saved in special ways in the stack
- frame. SP is even more special: the address we return for it IS
- the sp for the next frame. */
+struct frame_unwind arm_sigtramp_unwind = {
+ SIGTRAMP_FRAME,
+ arm_sigtramp_this_id,
+ arm_sigtramp_prev_register
+};
-static void
-arm_frame_init_saved_regs (struct frame_info *fip)
+static const struct frame_unwind *
+arm_sigtramp_unwind_sniffer (struct frame_info *next_frame)
{
+ /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
+ against the name of the function, the code below will have to be
+ changed to first fetch the name of the function and then pass
+ this name to PC_IN_SIGTRAMP. */
- if (fip->saved_regs)
- return;
+ if (SIGCONTEXT_REGISTER_ADDRESS_P ()
+ && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame), (char *) 0))
+ return &arm_sigtramp_unwind;
- arm_init_extra_frame_info (0, fip);
+ return NULL;
}
-/* Push an empty stack frame, to record the current PC, etc. */
+/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
+ dummy frame. The frame ID's base needs to match the TOS value
+ saved by save_dummy_frame_tos() and returned from
+ arm_push_dummy_call, and the PC needs to match the dummy frame's
+ breakpoint. */
-static void
-arm_push_dummy_frame (void)
+static struct frame_id
+arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
- CORE_ADDR old_sp = read_register (ARM_SP_REGNUM);
- CORE_ADDR sp = old_sp;
- CORE_ADDR fp, prologue_start;
- int regnum;
-
- /* Push the two dummy prologue instructions in reverse order,
- so that they'll be in the correct low-to-high order in memory. */
- /* sub fp, ip, #4 */
- sp = push_word (sp, 0xe24cb004);
- /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
- prologue_start = sp = push_word (sp, 0xe92ddfff);
-
- /* Push a pointer to the dummy prologue + 12, because when stm
- instruction stores the PC, it stores the address of the stm
- instruction itself plus 12. */
- fp = sp = push_word (sp, prologue_start + 12);
+ return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
+ frame_pc_unwind (next_frame));
+}
- /* Push the processor status. */
- sp = push_word (sp, read_register (ARM_PS_REGNUM));
+/* Given THIS_FRAME, find the previous frame's resume PC (which will
+ be used to construct the previous frame's ID, after looking up the
+ containing function). */
- /* Push all 16 registers starting with r15. */
- for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--)
- sp = push_word (sp, read_register (regnum));
+static CORE_ADDR
+arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
+{
+ CORE_ADDR pc;
+ pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
+ return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
+}
- /* Update fp (for both Thumb and ARM) and sp. */
- write_register (ARM_FP_REGNUM, fp);
- write_register (THUMB_FP_REGNUM, fp);
- write_register (ARM_SP_REGNUM, sp);
+static CORE_ADDR
+arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
+{
+ return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
}
-/* CALL_DUMMY_WORDS:
+/* DEPRECATED_CALL_DUMMY_WORDS:
This sequence of words is the instructions
mov lr,pc
0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
};
-/* Fix up the call dummy, based on whether the processor is currently
- in Thumb or ARM mode, and whether the target function is Thumb or
- ARM. There are three different situations requiring three
- different dummies:
+/* When arguments must be pushed onto the stack, they go on in reverse
+ order. The code below implements a FILO (stack) to do this. */
- * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
- been copied into the dummy parameter to this function.
- * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
- "mov pc,r4" instruction patched to be a "bx r4" instead.
- * Thumb calling anything: uses the Thumb dummy defined below, which
- works for calling both ARM and Thumb functions.
-
- All three call dummies expect to receive the target function
- address in R4, with the low bit set if it's a Thumb function. */
-
-static void
-arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
- struct value **args, struct type *type, int gcc_p)
-{
- static short thumb_dummy[4] =
- {
- 0xf000, 0xf801, /* bl label */
- 0xdf18, /* swi 24 */
- 0x4720, /* label: bx r4 */
- };
- static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
-
- /* Set flag indicating whether the current PC is in a Thumb function. */
- caller_is_thumb = arm_pc_is_thumb (read_pc ());
-
- /* If the target function is Thumb, set the low bit of the function
- address. And if the CPU is currently in ARM mode, patch the
- second instruction of call dummy to use a BX instruction to
- switch to Thumb mode. */
- target_is_thumb = arm_pc_is_thumb (fun);
- if (target_is_thumb)
- {
- fun |= 1;
- if (!caller_is_thumb)
- store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
- }
-
- /* If the CPU is currently in Thumb mode, use the Thumb call dummy
- instead of the ARM one that's already been copied. This will
- work for both Thumb and ARM target functions. */
- if (caller_is_thumb)
- {
- int i;
- char *p = dummy;
- int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
-
- for (i = 0; i < len; i++)
- {
- store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
- p += sizeof (thumb_dummy[0]);
- }
- }
+struct stack_item
+{
+ int len;
+ struct stack_item *prev;
+ void *data;
+};
- /* Put the target address in r4; the call dummy will copy this to
- the PC. */
- write_register (4, fun);
+static struct stack_item *
+push_stack_item (struct stack_item *prev, void *contents, int len)
+{
+ struct stack_item *si;
+ si = xmalloc (sizeof (struct stack_item));
+ si->data = xmalloc (len);
+ si->len = len;
+ si->prev = prev;
+ memcpy (si->data, contents, len);
+ return si;
}
-/* Return the offset in the call dummy of the instruction that needs
- to have a breakpoint placed on it. This is the offset of the 'swi
- 24' instruction, which is no longer actually used, but simply acts
- as a place-holder now.
-
- This implements the CALL_DUMMY_BREAK_OFFSET macro. */
-
-int
-arm_call_dummy_breakpoint_offset (void)
+static struct stack_item *
+pop_stack_item (struct stack_item *si)
{
- if (caller_is_thumb)
- return 4;
- else
- return 8;
+ struct stack_item *dead = si;
+ si = si->prev;
+ xfree (dead->data);
+ xfree (dead);
+ return si;
}
-/* Note: ScottB
-
- This function does not support passing parameters using the FPA
- variant of the APCS. It passes any floating point arguments in the
- general registers and/or on the stack. */
+/* We currently only support passing parameters in integer registers. This
+ conforms with GCC's default model. Several other variants exist and
+ we should probably support some of them based on the selected ABI. */
static CORE_ADDR
-arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
- int struct_return, CORE_ADDR struct_addr)
+arm_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
+ struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
+ struct value **args, CORE_ADDR sp, int struct_return,
+ CORE_ADDR struct_addr)
{
- char *fp;
- int argnum, argreg, nstack_size;
+ int argnum;
+ int argreg;
+ int nstack;
+ struct stack_item *si = NULL;
+
+ /* Set the return address. For the ARM, the return breakpoint is
+ always at BP_ADDR. */
+ /* XXX Fix for Thumb. */
+ regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
/* Walk through the list of args and determine how large a temporary
stack is required. Need to take care here as structs may be
passed on the stack, and we have to to push them. */
- nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */
- if (struct_return) /* The struct address goes in A1. */
- nstack_size += REGISTER_SIZE;
-
- /* Walk through the arguments and add their size to nstack_size. */
- for (argnum = 0; argnum < nargs; argnum++)
- {
- int len;
- struct type *arg_type;
+ nstack = 0;
- arg_type = check_typedef (VALUE_TYPE (args[argnum]));
- len = TYPE_LENGTH (arg_type);
+ argreg = ARM_A1_REGNUM;
+ nstack = 0;
- /* ANSI C code passes float arguments as integers, K&R code
- passes float arguments as doubles. Correct for this here. */
- if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len)
- nstack_size += FP_REGISTER_VIRTUAL_SIZE;
- else
- nstack_size += len;
- }
+ /* Some platforms require a double-word aligned stack. Make sure sp
+ is correctly aligned before we start. We always do this even if
+ it isn't really needed -- it can never hurt things. */
+ sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1);
- /* Allocate room on the stack, and initialize our stack frame
- pointer. */
- fp = NULL;
- if (nstack_size > 0)
+ /* The struct_return pointer occupies the first parameter
+ passing register. */
+ if (struct_return)
{
- sp -= nstack_size;
- fp = (char *) sp;
+ if (arm_debug)
+ fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
+ REGISTER_NAME (argreg), paddr (struct_addr));
+ regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
+ argreg++;
}
- /* Initialize the integer argument register pointer. */
- argreg = ARM_A1_REGNUM;
-
- /* The struct_return pointer occupies the first parameter passing
- register. */
- if (struct_return)
- write_register (argreg++, struct_addr);
-
- /* Process arguments from left to right. Store as many as allowed
- in the parameter passing registers (A1-A4), and save the rest on
- the temporary stack. */
for (argnum = 0; argnum < nargs; argnum++)
{
int len;
- char *val;
- CORE_ADDR regval;
+ struct type *arg_type;
+ struct type *target_type;
enum type_code typecode;
- struct type *arg_type, *target_type;
+ char *val;
arg_type = check_typedef (VALUE_TYPE (args[argnum]));
- target_type = TYPE_TARGET_TYPE (arg_type);
len = TYPE_LENGTH (arg_type);
+ target_type = TYPE_TARGET_TYPE (arg_type);
typecode = TYPE_CODE (arg_type);
- val = (char *) VALUE_CONTENTS (args[argnum]);
-
- /* ANSI C code passes float arguments as integers, K&R code
- passes float arguments as doubles. The .stabs record for
- for ANSI prototype floating point arguments records the
- type as FP_INTEGER, while a K&R style (no prototype)
- .stabs records the type as FP_FLOAT. In this latter case
- the compiler converts the float arguments to double before
- calling the function. */
- if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len)
- {
- DOUBLEST dblval;
- dblval = extract_floating (val, len);
- len = TARGET_DOUBLE_BIT / TARGET_CHAR_BIT;
- val = alloca (len);
- store_floating (val, len, dblval);
- }
-#if 1
- /* I don't know why this code was disable. The only logical use
- for a function pointer is to call that function, so setting
- the mode bit is perfectly fine. FN */
- /* If the argument is a pointer to a function, and it is a Thumb
- function, set the low bit of the pointer. */
+ val = VALUE_CONTENTS (args[argnum]);
+
+ /* If the argument is a pointer to a function, and it is a
+ Thumb function, create a LOCAL copy of the value and set
+ the THUMB bit in it. */
if (TYPE_CODE_PTR == typecode
- && NULL != target_type
+ && target_type != NULL
&& TYPE_CODE_FUNC == TYPE_CODE (target_type))
{
- CORE_ADDR regval = extract_address (val, len);
+ CORE_ADDR regval = extract_unsigned_integer (val, len);
if (arm_pc_is_thumb (regval))
- store_address (val, len, MAKE_THUMB_ADDR (regval));
+ {
+ val = alloca (len);
+ store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
+ }
}
-#endif
+
/* Copy the argument to general registers or the stack in
- register-sized pieces. Large arguments are split between
- registers and stack. */
+ register-sized pieces. Large arguments are split between
+ registers and stack. */
while (len > 0)
{
- int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
+ int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE;
if (argreg <= ARM_LAST_ARG_REGNUM)
{
- /* It's an argument being passed in a general register. */
- regval = extract_address (val, partial_len);
- write_register (argreg++, regval);
+ /* The argument is being passed in a general purpose
+ register. */
+ CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
+ if (arm_debug)
+ fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
+ argnum, REGISTER_NAME (argreg),
+ phex (regval, DEPRECATED_REGISTER_SIZE));
+ regcache_cooked_write_unsigned (regcache, argreg, regval);
+ argreg++;
}
else
{
/* Push the arguments onto the stack. */
- write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE);
- fp += REGISTER_SIZE;
+ if (arm_debug)
+ fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
+ argnum, nstack);
+ si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE);
+ nstack += DEPRECATED_REGISTER_SIZE;
}
-
+
len -= partial_len;
val += partial_len;
}
}
+ /* If we have an odd number of words to push, then decrement the stack
+ by one word now, so first stack argument will be dword aligned. */
+ if (nstack & 4)
+ sp -= 4;
- /* Return adjusted stack pointer. */
- return sp;
-}
-
-/* Pop the current frame. So long as the frame info has been initialized
- properly (see arm_init_extra_frame_info), this code works for dummy frames
- as well as regular frames. I.e, there's no need to have a special case
- for dummy frames. */
-static void
-arm_pop_frame (void)
-{
- int regnum;
- struct frame_info *frame = get_current_frame ();
- CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset
- + frame->extra_info->framesize);
-
- for (regnum = 0; regnum < NUM_REGS; regnum++)
- if (frame->saved_regs[regnum] != 0)
- write_register (regnum,
- read_memory_integer (frame->saved_regs[regnum],
- REGISTER_RAW_SIZE (regnum)));
+ while (si)
+ {
+ sp -= si->len;
+ write_memory (sp, si->data, si->len);
+ si = pop_stack_item (si);
+ }
- write_register (ARM_PC_REGNUM, FRAME_SAVED_PC (frame));
- write_register (ARM_SP_REGNUM, old_SP);
+ /* Finally, update teh SP register. */
+ regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
- flush_cached_frames ();
+ return sp;
}
static void
/* Print interesting information about the floating point processor
(if present) or emulator. */
static void
-arm_print_float_info (void)
+arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
+ struct frame_info *frame, const char *args)
{
- register unsigned long status = read_register (ARM_FPS_REGNUM);
+ unsigned long status = read_register (ARM_FPS_REGNUM);
int type;
type = (status >> 24) & 127;
return STATUS_REGISTER_SIZE;
}
+/* Map GDB internal REGNUM onto the Arm simulator register numbers. */
+static int
+arm_register_sim_regno (int regnum)
+{
+ int reg = regnum;
+ gdb_assert (reg >= 0 && reg < NUM_REGS);
+
+ if (reg < NUM_GREGS)
+ return SIM_ARM_R0_REGNUM + reg;
+ reg -= NUM_GREGS;
+
+ if (reg < NUM_FREGS)
+ return SIM_ARM_FP0_REGNUM + reg;
+ reg -= NUM_FREGS;
+
+ if (reg < NUM_SREGS)
+ return SIM_ARM_FPS_REGNUM + reg;
+ reg -= NUM_SREGS;
+
+ internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum);
+}
/* NOTE: cagney/2001-08-20: Both convert_from_extended() and
convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
little-endian systems. */
static void
-convert_from_extended (void *ptr, void *dbl)
+convert_from_extended (const struct floatformat *fmt, const void *ptr,
+ void *dbl)
{
DOUBLEST d;
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
else
floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
ptr, &d);
- floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl);
+ floatformat_from_doublest (fmt, &d, dbl);
}
static void
-convert_to_extended (void *dbl, void *ptr)
+convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
{
DOUBLEST d;
- floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d);
+ floatformat_to_doublest (fmt, ptr, &d);
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
else
{
unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
unsigned short inst1 = read_memory_integer (pc, 2);
- CORE_ADDR nextpc = pc + 2; /* default is next instruction */
+ CORE_ADDR nextpc = pc + 2; /* default is next instruction */
unsigned long offset;
if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
/* Fetch the saved PC from the stack. It's stored above
all of the other registers. */
- offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
+ offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE;
sp = read_register (ARM_SP_REGNUM);
nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
nextpc = ADDR_BITS_REMOVE (nextpc);
{
unsigned long status = read_register (ARM_PS_REGNUM);
unsigned long cond = bits (inst1, 8, 11);
- if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
+ if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
}
else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
switch (bits (this_instr, 24, 27))
{
case 0x0:
- case 0x1: /* data processing */
+ case 0x1: /* data processing */
case 0x2:
case 0x3:
{
break;
default:
- fprintf (stderr, "Bad bit-field extraction\n");
+ fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n");
return (pc);
}
}
single-step support. We find the target of the coming instruction
and breakpoint it.
- single_step is also called just after the inferior stops. If we had
- set up a simulated single-step, we undo our damage. */
+ single_step() is also called just after the inferior stops. If we
+ had set up a simulated single-step, we undo our damage. */
static void
arm_software_single_step (enum target_signal sig, int insert_bpt)
{
- static int next_pc; /* State between setting and unsetting. */
+ static int next_pc; /* State between setting and unsetting. */
static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
if (insert_bpt)
static asymbol *asym;
static combined_entry_type ce;
static struct coff_symbol_struct csym;
- static struct _bfd fake_bfd;
+ static struct bfd fake_bfd;
static bfd_target fake_target;
if (csym.native == NULL)
{
- /* Create a fake symbol vector containing a Thumb symbol. This is
- solely so that the code in print_insn_little_arm() and
- print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
- of a Thumb symbol and switch to decoding Thumb instructions. */
+ /* Create a fake symbol vector containing a Thumb symbol.
+ This is solely so that the code in print_insn_little_arm()
+ and print_insn_big_arm() in opcodes/arm-dis.c will detect
+ the presence of a Thumb symbol and switch to decoding
+ Thumb instructions. */
fake_target.flavour = bfd_target_coff_flavour;
fake_bfd.xvec = &fake_target;
return print_insn_little_arm (memaddr, info);
}
+/* The following define instruction sequences that will cause ARM
+ cpu's to take an undefined instruction trap. These are used to
+ signal a breakpoint to GDB.
+
+ The newer ARMv4T cpu's are capable of operating in ARM or Thumb
+ modes. A different instruction is required for each mode. The ARM
+ cpu's can also be big or little endian. Thus four different
+ instructions are needed to support all cases.
+
+ Note: ARMv4 defines several new instructions that will take the
+ undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
+ not in fact add the new instructions. The new undefined
+ instructions in ARMv4 are all instructions that had no defined
+ behaviour in earlier chips. There is no guarantee that they will
+ raise an exception, but may be treated as NOP's. In practice, it
+ may only safe to rely on instructions matching:
+
+ 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
+
+ Even this may only true if the condition predicate is true. The
+ following use a condition predicate of ALWAYS so it is always TRUE.
+
+ There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
+ and NetBSD all use a software interrupt rather than an undefined
+ instruction to force a trap. This can be handled by by the
+ abi-specific code during establishment of the gdbarch vector. */
+
+
+/* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
+ override these definitions. */
+#ifndef ARM_LE_BREAKPOINT
+#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
+#endif
+#ifndef ARM_BE_BREAKPOINT
+#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
+#endif
+#ifndef THUMB_LE_BREAKPOINT
+#define THUMB_LE_BREAKPOINT {0xfe,0xdf}
+#endif
+#ifndef THUMB_BE_BREAKPOINT
+#define THUMB_BE_BREAKPOINT {0xdf,0xfe}
+#endif
+
+static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
+static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
+static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
+static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
+
/* Determine the type and size of breakpoint to insert at PCPTR. Uses
the program counter value to determine whether a 16-bit or 32-bit
breakpoint should be used. It returns a pointer to a string of
/* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
breakpoints and storing their handles instread of what was in
memory. It is nice that this is the same size as a handle -
- otherwise remote-rdp will have to change. */
+ otherwise remote-rdp will have to change. */
-unsigned char *
+static const unsigned char *
arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
{
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- {
- static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT;
- *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
- *lenptr = sizeof (thumb_breakpoint);
- return thumb_breakpoint;
- }
- else
- {
- static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT;
- *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
- *lenptr = sizeof (thumb_breakpoint);
- return thumb_breakpoint;
- }
+ *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
+ *lenptr = tdep->thumb_breakpoint_size;
+ return tdep->thumb_breakpoint;
}
else
{
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- {
- static char arm_breakpoint[] = ARM_BE_BREAKPOINT;
- *lenptr = sizeof (arm_breakpoint);
- return arm_breakpoint;
- }
- else
- {
- static char arm_breakpoint[] = ARM_LE_BREAKPOINT;
- *lenptr = sizeof (arm_breakpoint);
- return arm_breakpoint;
- }
+ *lenptr = tdep->arm_breakpoint_size;
+ return tdep->arm_breakpoint;
}
}
static void
arm_extract_return_value (struct type *type,
- char regbuf[REGISTER_BYTES],
- char *valbuf)
+ struct regcache *regs,
+ void *dst)
{
+ bfd_byte *valbuf = dst;
+
if (TYPE_CODE_FLT == TYPE_CODE (type))
- convert_from_extended (®buf[REGISTER_BYTE (ARM_F0_REGNUM)], valbuf);
+ {
+ switch (arm_get_fp_model (current_gdbarch))
+ {
+ case ARM_FLOAT_FPA:
+ {
+ /* The value is in register F0 in internal format. We need to
+ extract the raw value and then convert it to the desired
+ internal type. */
+ bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE];
+
+ regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
+ convert_from_extended (floatformat_from_type (type), tmpbuf,
+ valbuf);
+ }
+ break;
+
+ case ARM_FLOAT_SOFT_FPA:
+ case ARM_FLOAT_SOFT_VFP:
+ regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
+ if (TYPE_LENGTH (type) > 4)
+ regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
+ valbuf + INT_REGISTER_RAW_SIZE);
+ break;
+
+ default:
+ internal_error
+ (__FILE__, __LINE__,
+ "arm_extract_return_value: Floating point model not supported");
+ break;
+ }
+ }
+ else if (TYPE_CODE (type) == TYPE_CODE_INT
+ || TYPE_CODE (type) == TYPE_CODE_CHAR
+ || TYPE_CODE (type) == TYPE_CODE_BOOL
+ || TYPE_CODE (type) == TYPE_CODE_PTR
+ || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_CODE (type) == TYPE_CODE_ENUM)
+ {
+ /* If the the type is a plain integer, then the access is
+ straight-forward. Otherwise we have to play around a bit more. */
+ int len = TYPE_LENGTH (type);
+ int regno = ARM_A1_REGNUM;
+ ULONGEST tmp;
+
+ while (len > 0)
+ {
+ /* By using store_unsigned_integer we avoid having to do
+ anything special for small big-endian values. */
+ regcache_cooked_read_unsigned (regs, regno++, &tmp);
+ store_unsigned_integer (valbuf,
+ (len > INT_REGISTER_RAW_SIZE
+ ? INT_REGISTER_RAW_SIZE : len),
+ tmp);
+ len -= INT_REGISTER_RAW_SIZE;
+ valbuf += INT_REGISTER_RAW_SIZE;
+ }
+ }
else
- memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)],
- TYPE_LENGTH (type));
+ {
+ /* For a structure or union the behaviour is as if the value had
+ been stored to word-aligned memory and then loaded into
+ registers with 32-bit load instruction(s). */
+ int len = TYPE_LENGTH (type);
+ int regno = ARM_A1_REGNUM;
+ bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
+
+ while (len > 0)
+ {
+ regcache_cooked_read (regs, regno++, tmpbuf);
+ memcpy (valbuf, tmpbuf,
+ len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len);
+ len -= INT_REGISTER_RAW_SIZE;
+ valbuf += INT_REGISTER_RAW_SIZE;
+ }
+ }
+}
+
+/* Extract from an array REGBUF containing the (raw) register state
+ the address in which a function should return its structure value. */
+
+static CORE_ADDR
+arm_extract_struct_value_address (struct regcache *regcache)
+{
+ ULONGEST ret;
+
+ regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret);
+ return ret;
+}
+
+/* Will a function return an aggregate type in memory or in a
+ register? Return 0 if an aggregate type can be returned in a
+ register, 1 if it must be returned in memory. */
+
+static int
+arm_use_struct_convention (int gcc_p, struct type *type)
+{
+ int nRc;
+ enum type_code code;
+
+ /* In the ARM ABI, "integer" like aggregate types are returned in
+ registers. For an aggregate type to be integer like, its size
+ must be less than or equal to DEPRECATED_REGISTER_SIZE and the
+ offset of each addressable subfield must be zero. Note that bit
+ fields are not addressable, and all addressable subfields of
+ unions always start at offset zero.
+
+ This function is based on the behaviour of GCC 2.95.1.
+ See: gcc/arm.c: arm_return_in_memory() for details.
+
+ Note: All versions of GCC before GCC 2.95.2 do not set up the
+ parameters correctly for a function returning the following
+ structure: struct { float f;}; This should be returned in memory,
+ not a register. Richard Earnshaw sent me a patch, but I do not
+ know of any way to detect if a function like the above has been
+ compiled with the correct calling convention. */
+
+ /* All aggregate types that won't fit in a register must be returned
+ in memory. */
+ if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE)
+ {
+ return 1;
+ }
+
+ /* The only aggregate types that can be returned in a register are
+ structs and unions. Arrays must be returned in memory. */
+ code = TYPE_CODE (type);
+ if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
+ {
+ return 1;
+ }
+
+ /* Assume all other aggregate types can be returned in a register.
+ Run a check for structures, unions and arrays. */
+ nRc = 0;
+
+ if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
+ {
+ int i;
+ /* Need to check if this struct/union is "integer" like. For
+ this to be true, its size must be less than or equal to
+ DEPRECATED_REGISTER_SIZE and the offset of each addressable
+ subfield must be zero. Note that bit fields are not
+ addressable, and unions always start at offset zero. If any
+ of the subfields is a floating point type, the struct/union
+ cannot be an integer type. */
+
+ /* For each field in the object, check:
+ 1) Is it FP? --> yes, nRc = 1;
+ 2) Is it addressable (bitpos != 0) and
+ not packed (bitsize == 0)?
+ --> yes, nRc = 1
+ */
+
+ for (i = 0; i < TYPE_NFIELDS (type); i++)
+ {
+ enum type_code field_type_code;
+ field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
+
+ /* Is it a floating point type field? */
+ if (field_type_code == TYPE_CODE_FLT)
+ {
+ nRc = 1;
+ break;
+ }
+
+ /* If bitpos != 0, then we have to care about it. */
+ if (TYPE_FIELD_BITPOS (type, i) != 0)
+ {
+ /* Bitfields are not addressable. If the field bitsize is
+ zero, then the field is not packed. Hence it cannot be
+ a bitfield or any other packed type. */
+ if (TYPE_FIELD_BITSIZE (type, i) == 0)
+ {
+ nRc = 1;
+ break;
+ }
+ }
+ }
+ }
+
+ return nRc;
}
/* Write into appropriate registers a function return value of type
TYPE, given in virtual format. */
static void
-arm_store_return_value (struct type *type, char *valbuf)
+arm_store_return_value (struct type *type, struct regcache *regs,
+ const void *src)
{
+ const bfd_byte *valbuf = src;
+
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- char buf[MAX_REGISTER_RAW_SIZE];
+ char buf[ARM_MAX_REGISTER_RAW_SIZE];
+
+ switch (arm_get_fp_model (current_gdbarch))
+ {
+ case ARM_FLOAT_FPA:
+
+ convert_to_extended (floatformat_from_type (type), buf, valbuf);
+ regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
+ break;
+
+ case ARM_FLOAT_SOFT_FPA:
+ case ARM_FLOAT_SOFT_VFP:
+ regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
+ if (TYPE_LENGTH (type) > 4)
+ regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
+ valbuf + INT_REGISTER_RAW_SIZE);
+ break;
+
+ default:
+ internal_error
+ (__FILE__, __LINE__,
+ "arm_store_return_value: Floating point model not supported");
+ break;
+ }
+ }
+ else if (TYPE_CODE (type) == TYPE_CODE_INT
+ || TYPE_CODE (type) == TYPE_CODE_CHAR
+ || TYPE_CODE (type) == TYPE_CODE_BOOL
+ || TYPE_CODE (type) == TYPE_CODE_PTR
+ || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_CODE (type) == TYPE_CODE_ENUM)
+ {
+ if (TYPE_LENGTH (type) <= 4)
+ {
+ /* Values of one word or less are zero/sign-extended and
+ returned in r0. */
+ bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
+ LONGEST val = unpack_long (type, valbuf);
+
+ store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val);
+ regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
+ }
+ else
+ {
+ /* Integral values greater than one word are stored in consecutive
+ registers starting with r0. This will always be a multiple of
+ the regiser size. */
+ int len = TYPE_LENGTH (type);
+ int regno = ARM_A1_REGNUM;
- convert_to_extended (valbuf, buf);
- /* XXX Is this correct for soft-float? */
- write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM), buf,
- MAX_REGISTER_RAW_SIZE);
+ while (len > 0)
+ {
+ regcache_cooked_write (regs, regno++, valbuf);
+ len -= INT_REGISTER_RAW_SIZE;
+ valbuf += INT_REGISTER_RAW_SIZE;
+ }
+ }
}
else
- write_register_bytes (0, valbuf, TYPE_LENGTH (type));
-}
+ {
+ /* For a structure or union the behaviour is as if the value had
+ been stored to word-aligned memory and then loaded into
+ registers with 32-bit load instruction(s). */
+ int len = TYPE_LENGTH (type);
+ int regno = ARM_A1_REGNUM;
+ bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
-/* Store the address of the place in which to copy the structure the
- subroutine will return. This is called from call_function. */
+ while (len > 0)
+ {
+ memcpy (tmpbuf, valbuf,
+ len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len);
+ regcache_cooked_write (regs, regno++, tmpbuf);
+ len -= INT_REGISTER_RAW_SIZE;
+ valbuf += INT_REGISTER_RAW_SIZE;
+ }
+ }
+}
-static void
-arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
+static int
+arm_get_longjmp_target (CORE_ADDR *pc)
{
- write_register (ARM_A1_REGNUM, addr);
+ CORE_ADDR jb_addr;
+ char buf[INT_REGISTER_RAW_SIZE];
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ jb_addr = read_register (ARM_A1_REGNUM);
+
+ if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
+ INT_REGISTER_RAW_SIZE))
+ return 0;
+
+ *pc = extract_unsigned_integer (buf, INT_REGISTER_RAW_SIZE);
+ return 1;
}
/* Return non-zero if the PC is inside a thumb call thunk. */
/* Find the starting address of the function containing the PC. If
the caller didn't give us a name, look it up at the same time. */
- if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
+ if (0 == find_pc_partial_function (pc, name ? NULL : &name,
+ &start_addr, NULL))
return 0;
return strncmp (name, "_call_via_r", 11) == 0;
return 0; /* not a stub */
}
-/* If the user changes the register disassembly flavor used for info register
- and other commands, we have to also switch the flavor used in opcodes
- for disassembly output.
- This function is run in the set disassembly_flavor command, and does that. */
+static void
+set_arm_command (char *args, int from_tty)
+{
+ printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
+ help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
+}
+
+static void
+show_arm_command (char *args, int from_tty)
+{
+ cmd_show_list (showarmcmdlist, from_tty, "");
+}
+
+enum arm_float_model
+arm_get_fp_model (struct gdbarch *gdbarch)
+{
+ if (arm_fp_model == ARM_FLOAT_AUTO)
+ return gdbarch_tdep (gdbarch)->fp_model;
+
+ return arm_fp_model;
+}
+
+static void
+arm_set_fp (struct gdbarch *gdbarch)
+{
+ enum arm_float_model fp_model = arm_get_fp_model (gdbarch);
+
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
+ && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA))
+ {
+ set_gdbarch_double_format (gdbarch,
+ &floatformat_ieee_double_littlebyte_bigword);
+ set_gdbarch_long_double_format
+ (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
+ }
+ else
+ {
+ set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
+ set_gdbarch_long_double_format (gdbarch,
+ &floatformat_ieee_double_little);
+ }
+}
+
+static void
+set_fp_model_sfunc (char *args, int from_tty,
+ struct cmd_list_element *c)
+{
+ enum arm_float_model fp_model;
+
+ for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
+ if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
+ {
+ arm_fp_model = fp_model;
+ break;
+ }
+
+ if (fp_model == ARM_FLOAT_LAST)
+ internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.",
+ current_fp_model);
+
+ if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
+ arm_set_fp (current_gdbarch);
+}
static void
-set_disassembly_flavor_sfunc (char *args, int from_tty,
+show_fp_model (char *args, int from_tty,
+ struct cmd_list_element *c)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (arm_fp_model == ARM_FLOAT_AUTO
+ && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
+ printf_filtered (" - the default for the current ABI is \"%s\".\n",
+ fp_model_strings[tdep->fp_model]);
+}
+
+/* If the user changes the register disassembly style used for info
+ register and other commands, we have to also switch the style used
+ in opcodes for disassembly output. This function is run in the "set
+ arm disassembly" command, and does that. */
+
+static void
+set_disassembly_style_sfunc (char *args, int from_tty,
struct cmd_list_element *c)
{
- set_disassembly_flavor ();
+ set_disassembly_style ();
}
\f
/* Return the ARM register name corresponding to register I. */
-static char *
+static const char *
arm_register_name (int i)
{
return arm_register_names[i];
}
static void
-set_disassembly_flavor (void)
+set_disassembly_style (void)
{
const char *setname, *setdesc, **regnames;
int numregs, j;
- /* Find the flavor that the user wants in the opcodes table. */
+ /* Find the style that the user wants in the opcodes table. */
int current = 0;
numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
- while ((disassembly_flavor != setname)
- && (current < num_flavor_options))
+ while ((disassembly_style != setname)
+ && (current < num_disassembly_options))
get_arm_regnames (++current, &setname, &setdesc, ®names);
current_option = current;
- /* Fill our copy. */
+ /* Fill our copy. */
for (j = 0; j < numregs; j++)
arm_register_names[j] = (char *) regnames[j];
- /* Adjust case. */
+ /* Adjust case. */
if (isupper (*regnames[ARM_PC_REGNUM]))
{
arm_register_names[ARM_FPS_REGNUM] = "FPS";
arm_register_names[ARM_PS_REGNUM] = "cpsr";
}
- /* Synchronize the disassembler. */
+ /* Synchronize the disassembler. */
set_arm_regname_option (current);
}
-/* arm_othernames implements the "othernames" command. This is kind
- of hacky, and I prefer the set-show disassembly-flavor which is
- also used for the x86 gdb. I will keep this around, however, in
- case anyone is actually using it. */
+/* arm_othernames implements the "othernames" command. This is deprecated
+ by the "set arm disassembly" command. */
static void
arm_othernames (char *names, int n)
{
- /* Circle through the various flavors. */
- current_option = (current_option + 1) % num_flavor_options;
+ /* Circle through the various flavors. */
+ current_option = (current_option + 1) % num_disassembly_options;
- disassembly_flavor = valid_flavors[current_option];
- set_disassembly_flavor ();
-}
-
-/* Fetch, and possibly build, an appropriate link_map_offsets structure
- for ARM linux targets using the struct offsets defined in <link.h>.
- Note, however, that link.h is not actually referred to in this file.
- Instead, the relevant structs offsets were obtained from examining
- link.h. (We can't refer to link.h from this file because the host
- system won't necessarily have it, or if it does, the structs which
- it defines will refer to the host system, not the target.) */
-
-struct link_map_offsets *
-arm_linux_svr4_fetch_link_map_offsets (void)
-{
- static struct link_map_offsets lmo;
- static struct link_map_offsets *lmp = 0;
-
- if (lmp == 0)
- {
- lmp = &lmo;
-
- lmo.r_debug_size = 8; /* Actual size is 20, but this is all we
- need. */
-
- lmo.r_map_offset = 4;
- lmo.r_map_size = 4;
-
- lmo.link_map_size = 20; /* Actual size is 552, but this is all we
- need. */
-
- lmo.l_addr_offset = 0;
- lmo.l_addr_size = 4;
-
- lmo.l_name_offset = 4;
- lmo.l_name_size = 4;
-
- lmo.l_next_offset = 12;
- lmo.l_next_size = 4;
-
- lmo.l_prev_offset = 16;
- lmo.l_prev_size = 4;
- }
-
- return lmp;
+ disassembly_style = valid_disassembly_styles[current_option];
+ set_disassembly_style ();
}
/* Test whether the coff symbol specific value corresponds to a Thumb
MSYMBOL_SET_SPECIAL (msym);
}
+static void
+arm_write_pc (CORE_ADDR pc, ptid_t ptid)
+{
+ write_register_pid (ARM_PC_REGNUM, pc, ptid);
+
+ /* If necessary, set the T bit. */
+ if (arm_apcs_32)
+ {
+ CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid);
+ if (arm_pc_is_thumb (pc))
+ write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid);
+ else
+ write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid);
+ }
+}
+\f
+static enum gdb_osabi
+arm_elf_osabi_sniffer (bfd *abfd)
+{
+ unsigned int elfosabi, eflags;
+ enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
+
+ elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
+
+ switch (elfosabi)
+ {
+ case ELFOSABI_NONE:
+ /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
+ file are conforming to the base specification for that machine
+ (there are no OS-specific extensions). In order to determine the
+ real OS in use we must look for OS notes that have been added. */
+ bfd_map_over_sections (abfd,
+ generic_elf_osabi_sniff_abi_tag_sections,
+ &osabi);
+ if (osabi == GDB_OSABI_UNKNOWN)
+ {
+ /* Existing ARM tools don't set this field, so look at the EI_FLAGS
+ field for more information. */
+ eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
+ switch (eflags)
+ {
+ case EF_ARM_EABI_VER1:
+ osabi = GDB_OSABI_ARM_EABI_V1;
+ break;
+
+ case EF_ARM_EABI_VER2:
+ osabi = GDB_OSABI_ARM_EABI_V2;
+ break;
+
+ case EF_ARM_EABI_UNKNOWN:
+ /* Assume GNU tools. */
+ osabi = GDB_OSABI_ARM_APCS;
+ break;
+
+ default:
+ internal_error (__FILE__, __LINE__,
+ "arm_elf_osabi_sniffer: Unknown ARM EABI "
+ "version 0x%x", eflags);
+ }
+ }
+ break;
+
+ case ELFOSABI_ARM:
+ /* GNU tools use this value. Check note sections in this case,
+ as well. */
+ bfd_map_over_sections (abfd,
+ generic_elf_osabi_sniff_abi_tag_sections,
+ &osabi);
+ if (osabi == GDB_OSABI_UNKNOWN)
+ {
+ /* Assume APCS ABI. */
+ osabi = GDB_OSABI_ARM_APCS;
+ }
+ break;
+
+ case ELFOSABI_FREEBSD:
+ osabi = GDB_OSABI_FREEBSD_ELF;
+ break;
+
+ case ELFOSABI_NETBSD:
+ osabi = GDB_OSABI_NETBSD_ELF;
+ break;
+
+ case ELFOSABI_LINUX:
+ osabi = GDB_OSABI_LINUX;
+ break;
+ }
+
+ return osabi;
+}
+
+\f
+/* Initialize the current architecture based on INFO. If possible,
+ re-use an architecture from ARCHES, which is a list of
+ architectures already created during this debugging session.
+
+ Called e.g. at program startup, when reading a core file, and when
+ reading a binary file. */
+
static struct gdbarch *
arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
+ struct gdbarch_tdep *tdep;
struct gdbarch *gdbarch;
+ /* Try to deterimine the ABI of the object we are loading. */
+
+ if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN)
+ {
+ switch (bfd_get_flavour (info.abfd))
+ {
+ case bfd_target_aout_flavour:
+ /* Assume it's an old APCS-style ABI. */
+ info.osabi = GDB_OSABI_ARM_APCS;
+ break;
+
+ case bfd_target_coff_flavour:
+ /* Assume it's an old APCS-style ABI. */
+ /* XXX WinCE? */
+ info.osabi = GDB_OSABI_ARM_APCS;
+ break;
+
+ default:
+ /* Leave it as "unknown". */
+ break;
+ }
+ }
+
+ /* If there is already a candidate, use it. */
+ arches = gdbarch_list_lookup_by_info (arches, &info);
if (arches != NULL)
return arches->gdbarch;
- /* XXX We'll probably need to set the tdep field soon. */
- gdbarch = gdbarch_alloc (&info, NULL);
+ tdep = xmalloc (sizeof (struct gdbarch_tdep));
+ gdbarch = gdbarch_alloc (&info, tdep);
+
+ /* We used to default to FPA for generic ARM, but almost nobody uses that
+ now, and we now provide a way for the user to force the model. So
+ default to the most useful variant. */
+ tdep->fp_model = ARM_FLOAT_SOFT_FPA;
- set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
+ /* Breakpoints. */
+ switch (info.byte_order)
+ {
+ case BFD_ENDIAN_BIG:
+ tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
+ tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
+ tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
+ tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
- /* Call dummy code. */
- set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
- set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
- set_gdbarch_call_dummy_p (gdbarch, 1);
- set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
+ break;
- set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words);
- set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (arm_call_dummy_words));
- set_gdbarch_call_dummy_start_offset (gdbarch, 0);
+ case BFD_ENDIAN_LITTLE:
+ tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
+ tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
+ tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
+ tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
- set_gdbarch_fix_call_dummy (gdbarch, arm_fix_call_dummy);
+ break;
+
+ default:
+ internal_error (__FILE__, __LINE__,
+ "arm_gdbarch_init: bad byte order for float format");
+ }
- set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack);
+ /* On ARM targets char defaults to unsigned. */
+ set_gdbarch_char_signed (gdbarch, 0);
- set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
- set_gdbarch_push_arguments (gdbarch, arm_push_arguments);
+ /* This should be low enough for everything. */
+ tdep->lowest_pc = 0x20;
+ tdep->jb_pc = -1; /* Longjump support not enabled by default. */
+
+ set_gdbarch_deprecated_call_dummy_words (gdbarch, arm_call_dummy_words);
+ set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0);
+
+ set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
+
+ set_gdbarch_write_pc (gdbarch, arm_write_pc);
/* Frame handling. */
- set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid);
- set_gdbarch_init_extra_frame_info (gdbarch, arm_init_extra_frame_info);
- set_gdbarch_read_fp (gdbarch, arm_read_fp);
- set_gdbarch_frame_chain (gdbarch, arm_frame_chain);
+ set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
+ set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
+ set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
+
set_gdbarch_frameless_function_invocation
(gdbarch, arm_frameless_function_invocation);
- set_gdbarch_frame_saved_pc (gdbarch, arm_frame_saved_pc);
- set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address);
- set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address);
- set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args);
- set_gdbarch_frame_args_skip (gdbarch, 0);
- set_gdbarch_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs);
- set_gdbarch_push_dummy_frame (gdbarch, arm_push_dummy_frame);
- set_gdbarch_pop_frame (gdbarch, arm_pop_frame);
+
+ frame_base_set_default (gdbarch, &arm_normal_base);
/* Address manipulation. */
set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
- /* Offset from address of function to start of its code. */
- set_gdbarch_function_start_offset (gdbarch, 0);
-
/* Advance PC across function entry code. */
set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
/* Get the PC when a frame might not be available. */
- set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
/* The stack grows downward. */
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
/* Breakpoint manipulation. */
set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
- set_gdbarch_decr_pc_after_break (gdbarch, 0);
/* Information about registers, etc. */
set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
- set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
+ set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
- set_gdbarch_register_byte (gdbarch, arm_register_byte);
- set_gdbarch_register_bytes (gdbarch,
- (NUM_GREGS * INT_REGISTER_RAW_SIZE
- + NUM_FREGS * FP_REGISTER_RAW_SIZE
- + NUM_SREGS * STATUS_REGISTER_SIZE));
+ set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte);
+ set_gdbarch_deprecated_register_bytes (gdbarch,
+ (NUM_GREGS * INT_REGISTER_RAW_SIZE
+ + NUM_FREGS * FP_REGISTER_RAW_SIZE
+ + NUM_SREGS * STATUS_REGISTER_SIZE));
set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
- set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size);
- set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size);
- set_gdbarch_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE);
- set_gdbarch_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE);
- set_gdbarch_register_virtual_type (gdbarch, arm_register_type);
+ set_gdbarch_deprecated_register_raw_size (gdbarch, arm_register_raw_size);
+ set_gdbarch_deprecated_register_virtual_size (gdbarch, arm_register_virtual_size);
+ set_gdbarch_deprecated_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE);
+ set_gdbarch_deprecated_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE);
+ set_gdbarch_deprecated_register_virtual_type (gdbarch, arm_register_type);
+
+ /* Internal <-> external register number maps. */
+ set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
/* Integer registers are 4 bytes. */
- set_gdbarch_register_size (gdbarch, 4);
+ set_gdbarch_deprecated_register_size (gdbarch, 4);
set_gdbarch_register_name (gdbarch, arm_register_name);
/* Returning results. */
set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value);
set_gdbarch_store_return_value (gdbarch, arm_store_return_value);
- set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return);
+ set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention);
+ set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address);
/* Single stepping. */
/* XXX For an RDI target we should ask the target if it can single-step. */
set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
+ /* Disassembly. */
+ set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
+
/* Minsymbol frobbing. */
set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
set_gdbarch_coff_make_msymbol_special (gdbarch,
arm_coff_make_msymbol_special);
- /* XXX We can't do this until NUM_REGS is set for the architecture.
- Even then, we can't use SIZEOF_FRAME_SAVED_REGS, since that still
- references the old architecture vector, not the one we are
- building here. */
- if (prologue_cache.saved_regs != NULL)
- xfree (prologue_cache.saved_regs);
+ /* Hook in the ABI-specific overrides, if they have been registered. */
+ gdbarch_init_osabi (info, gdbarch);
+
+ /* Add some default predicates. */
+ frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer);
+ frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
+
+ /* Now we have tuned the configuration, set a few final things,
+ based on what the OS ABI has told us. */
- prologue_cache.saved_regs = (CORE_ADDR *)
- xcalloc (1, (sizeof (CORE_ADDR)
- * (NUM_GREGS + NUM_FREGS + NUM_SREGS + NUM_PSEUDO_REGS)));
+ if (tdep->jb_pc >= 0)
+ set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
+
+ /* Floating point sizes and format. */
+ switch (info.byte_order)
+ {
+ case BFD_ENDIAN_BIG:
+ set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
+ set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
+ set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
+
+ break;
+
+ case BFD_ENDIAN_LITTLE:
+ set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
+ arm_set_fp (gdbarch);
+ break;
+
+ default:
+ internal_error (__FILE__, __LINE__,
+ "arm_gdbarch_init: bad byte order for float format");
+ }
return gdbarch;
}
+static void
+arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (tdep == NULL)
+ return;
+
+ fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx",
+ (unsigned long) tdep->lowest_pc);
+}
+
+static void
+arm_init_abi_eabi_v1 (struct gdbarch_info info,
+ struct gdbarch *gdbarch)
+{
+ /* Place-holder. */
+}
+
+static void
+arm_init_abi_eabi_v2 (struct gdbarch_info info,
+ struct gdbarch *gdbarch)
+{
+ /* Place-holder. */
+}
+
+static void
+arm_init_abi_apcs (struct gdbarch_info info,
+ struct gdbarch *gdbarch)
+{
+ /* Place-holder. */
+}
+
+extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
+
void
_initialize_arm_tdep (void)
{
struct ui_file *stb;
long length;
- struct cmd_list_element *new_cmd;
+ struct cmd_list_element *new_set, *new_show;
const char *setname;
const char *setdesc;
const char **regnames;
int numregs, i, j;
static char *helptext;
- if (GDB_MULTI_ARCH)
- register_gdbarch_init (bfd_arch_arm, arm_gdbarch_init);
+ gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
+
+ /* Register an ELF OS ABI sniffer for ARM binaries. */
+ gdbarch_register_osabi_sniffer (bfd_arch_arm,
+ bfd_target_elf_flavour,
+ arm_elf_osabi_sniffer);
- tm_print_insn = gdb_print_insn_arm;
+ /* Register some ABI variants for embedded systems. */
+ gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1,
+ arm_init_abi_eabi_v1);
+ gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2,
+ arm_init_abi_eabi_v2);
+ gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS,
+ arm_init_abi_apcs);
- /* Get the number of possible sets of register names defined in opcodes. */
- num_flavor_options = get_arm_regname_num_options ();
+ /* Get the number of possible sets of register names defined in opcodes. */
+ num_disassembly_options = get_arm_regname_num_options ();
- /* Sync the opcode insn printer with our register viewer: */
+ /* Add root prefix command for all "set arm"/"show arm" commands. */
+ add_prefix_cmd ("arm", no_class, set_arm_command,
+ "Various ARM-specific commands.",
+ &setarmcmdlist, "set arm ", 0, &setlist);
+
+ add_prefix_cmd ("arm", no_class, show_arm_command,
+ "Various ARM-specific commands.",
+ &showarmcmdlist, "show arm ", 0, &showlist);
+
+ /* Sync the opcode insn printer with our register viewer. */
parse_arm_disassembler_option ("reg-names-std");
- /* Begin creating the help text. */
+ /* Begin creating the help text. */
stb = mem_fileopen ();
- fprintf_unfiltered (stb, "Set the disassembly flavor.\n\
-The valid values are:\n");
+ fprintf_unfiltered (stb, "Set the disassembly style.\n"
+ "The valid values are:\n");
- /* Initialize the array that will be passed to add_set_enum_cmd(). */
- valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *));
- for (i = 0; i < num_flavor_options; i++)
+ /* Initialize the array that will be passed to add_set_enum_cmd(). */
+ valid_disassembly_styles
+ = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
+ for (i = 0; i < num_disassembly_options; i++)
{
numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
- valid_flavors[i] = setname;
+ valid_disassembly_styles[i] = setname;
fprintf_unfiltered (stb, "%s - %s\n", setname,
setdesc);
- /* Copy the default names (if found) and synchronize disassembler. */
+ /* Copy the default names (if found) and synchronize disassembler. */
if (!strcmp (setname, "std"))
{
- disassembly_flavor = setname;
+ disassembly_style = setname;
current_option = i;
for (j = 0; j < numregs; j++)
arm_register_names[j] = (char *) regnames[j];
set_arm_regname_option (i);
}
}
- /* Mark the end of valid options. */
- valid_flavors[num_flavor_options] = NULL;
+ /* Mark the end of valid options. */
+ valid_disassembly_styles[num_disassembly_options] = NULL;
- /* Finish the creation of the help text. */
+ /* Finish the creation of the help text. */
fprintf_unfiltered (stb, "The default is \"std\".");
helptext = ui_file_xstrdup (stb, &length);
ui_file_delete (stb);
- /* Add the disassembly-flavor command */
- new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
- valid_flavors,
- &disassembly_flavor,
+ /* Add the deprecated disassembly-flavor command. */
+ new_set = add_set_enum_cmd ("disassembly-flavor", no_class,
+ valid_disassembly_styles,
+ &disassembly_style,
helptext,
&setlist);
- set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc);
- add_show_from_set (new_cmd, &showlist);
-
- /* ??? Maybe this should be a boolean. */
- add_show_from_set (add_set_cmd ("apcs32", no_class,
- var_zinteger, (char *) &arm_apcs_32,
- "Set usage of ARM 32-bit mode.\n", &setlist),
- &showlist);
-
- /* Add the deprecated "othernames" command */
-
- add_com ("othernames", class_obscure, arm_othernames,
- "Switch to the next set of register names.");
-
- /* Fill in the prologue_cache fields. */
- prologue_cache.saved_regs = NULL;
- prologue_cache.extra_info = (struct frame_extra_info *)
- xcalloc (1, sizeof (struct frame_extra_info));
+ set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
+ deprecate_cmd (new_set, "set arm disassembly");
+ deprecate_cmd (add_show_from_set (new_set, &showlist),
+ "show arm disassembly");
+
+ /* And now add the new interface. */
+ new_set = add_set_enum_cmd ("disassembler", no_class,
+ valid_disassembly_styles, &disassembly_style,
+ helptext, &setarmcmdlist);
+
+ set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
+ add_show_from_set (new_set, &showarmcmdlist);
+
+ add_setshow_cmd_full ("apcs32", no_class,
+ var_boolean, (char *) &arm_apcs_32,
+ "Set usage of ARM 32-bit mode.",
+ "Show usage of ARM 32-bit mode.",
+ NULL, NULL,
+ &setlist, &showlist, &new_set, &new_show);
+ deprecate_cmd (new_set, "set arm apcs32");
+ deprecate_cmd (new_show, "show arm apcs32");
+
+ add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
+ "Set usage of ARM 32-bit mode. "
+ "When off, a 26-bit PC will be used.",
+ "Show usage of ARM 32-bit mode. "
+ "When off, a 26-bit PC will be used.",
+ NULL, NULL,
+ &setarmcmdlist, &showarmcmdlist);
+
+ /* Add a command to allow the user to force the FPU model. */
+ new_set = add_set_enum_cmd
+ ("fpu", no_class, fp_model_strings, ¤t_fp_model,
+ "Set the floating point type.\n"
+ "auto - Determine the FP typefrom the OS-ABI.\n"
+ "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
+ "fpa - FPA co-processor (GCC compiled).\n"
+ "softvfp - Software FP with pure-endian doubles.\n"
+ "vfp - VFP co-processor.",
+ &setarmcmdlist);
+ set_cmd_sfunc (new_set, set_fp_model_sfunc);
+ set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model);
+
+ /* Add the deprecated "othernames" command. */
+ deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames,
+ "Switch to the next set of register names."),
+ "set arm disassembly");
+
+ /* Debugging flag. */
+ add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
+ "Set ARM debugging. "
+ "When on, arm-specific debugging is enabled.",
+ "Show ARM debugging. "
+ "When on, arm-specific debugging is enabled.",
+ NULL, NULL,
+ &setdebuglist, &showdebuglist);
}
projects / deliverable / binutils-gdb.git / blobdiff