Add bootstrap-asan.mk

[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index 57762832c757f0837e96e879ce8ae89e44d759c3..97596d5965c44c134002182aa4c7bc0e429a1526 100644 (file)
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -1,6 +1,5 @@
 /* Common target dependent code for GDB on ARM systems.
-   Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010, 2011
-   Free Software Foundation, Inc.
+   Copyright (C) 2002-2003, 2007-2012 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -23,6 +22,7 @@
 /* Forward declarations.  */
 struct gdbarch;
 struct regset;
+struct address_space;
 
 /* Register numbers of various important registers.  */
 
@@ -71,6 +71,10 @@ enum gdb_regnum {
    bits.  DWORD aligned they use 96 bits.  */
 #define FP_REGISTER_SIZE       12
 
+/* Say how long VFP double precision registers are.  Used for documentation
+   purposes and code readability.  These are fixed at 64 bits.  */
+#define VFP_REGISTER_SIZE      8
+
 /* Number of machine registers.  The only define actually required 
    is gdbarch_num_regs.  The other definitions are used for documentation
    purposes and code readability.  */
@@ -181,7 +185,7 @@ struct gdbarch_tdep
   const char *thumb2_breakpoint;
   int thumb2_breakpoint_size;
 
-  int jb_pc;                   /* Offset to PC value in jump buffer. 
+  int jb_pc;                   /* Offset to PC value in jump buffer.
                                   If this is negative, longjmp support
                                   will be disabled.  */
   size_t jb_elt_size;          /* And the size of each entry in the buf.  */
@@ -190,7 +194,7 @@ struct gdbarch_tdep
   enum struct_return struct_return;
 
   /* Cached core file helpers.  */
-  struct regset *gregset, *fpregset;
+  struct regset *gregset, *fpregset, *vfpregset;
 
   /* ISA-specific data types.  */
   struct type *arm_ext_type;
@@ -200,6 +204,9 @@ struct gdbarch_tdep
   /* Return the expected next PC if FRAME is stopped at a syscall
      instruction.  */
   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
+
+   /* Parse swi insn args, sycall record.  */
+  int (*arm_swi_record) (struct regcache *regcache);
 };
 
 /* Structures used for displaced stepping.  */
@@ -257,11 +264,21 @@ struct displaced_step_closure
     {
       /* If non-NULL, override generic SVC handling (e.g. for a particular
          OS).  */
-      int (*copy_svc_os) (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
-                         struct regcache *regs,
+      int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
                          struct displaced_step_closure *dsc);
     } svc;
   } u;
+
+  /* The size of original instruction, 2 or 4.  */
+  unsigned int insn_size;
+  /* True if the original insn (and thus all replacement insns) are Thumb
+     instead of ARM.   */
+  unsigned int is_thumb;
+
+  /* The slots in the array is used in this way below,
+     - ARM instruction occupies one slot,
+     - Thumb 16 bit instruction occupies one slot,
+     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
   unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
   int numinsns;
   CORE_ADDR insn_addr;
@@ -284,15 +301,15 @@ enum pc_write_style
 };
 
 extern void
-  arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn,
-                             CORE_ADDR from, CORE_ADDR to,
-                             struct regcache *regs,
+  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
+                             CORE_ADDR to, struct regcache *regs,
                              struct displaced_step_closure *dsc);
 extern void
   arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
                              CORE_ADDR to, struct displaced_step_closure *dsc);
 extern ULONGEST
-  displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno);
+  displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
+                     int regno);
 extern void
   displaced_write_reg (struct regcache *regs,
                       struct displaced_step_closure *dsc, int regno,
@@ -300,6 +317,9 @@ extern void
 
 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
+void arm_insert_single_step_breakpoint (struct gdbarch *,
+                                       struct address_space *, CORE_ADDR);
+int arm_deal_with_atomic_sequence (struct frame_info *);
 int arm_software_single_step (struct frame_info *);
 int arm_frame_is_thumb (struct frame_info *frame);
 
@@ -310,6 +330,15 @@ extern void arm_displaced_step_fixup (struct gdbarch *,
                                      struct displaced_step_closure *,
                                      CORE_ADDR, CORE_ADDR, struct regcache *);
 
+/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
+extern int arm_psr_thumb_bit (struct gdbarch *);
+
+/* Is the instruction at the given memory address a Thumb or ARM
+   instruction?  */
+extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
+
+extern int arm_process_record (struct gdbarch *gdbarch, 
+                               struct regcache *regcache, CORE_ADDR addr);
 /* Functions exported from armbsd-tdep.h.  */
 
 /* Return the appropriate register set for the core section identified
@@ -319,4 +348,11 @@ extern const struct regset *
   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
                                   const char *sect_name, size_t sect_size);
 
+/* Target descriptions.  */
+extern struct target_desc *tdesc_arm_with_m;
+extern struct target_desc *tdesc_arm_with_iwmmxt;
+extern struct target_desc *tdesc_arm_with_vfpv2;
+extern struct target_desc *tdesc_arm_with_vfpv3;
+extern struct target_desc *tdesc_arm_with_neon;
+
 #endif /* arm-tdep.h */