/* Target-dependent code for QNX Neutrino x86.
- Copyright (C) 2003, 2004, 2007, 2008 Free Software Foundation, Inc.
+ Copyright (C) 2003-2020 Free Software Foundation, Inc.
Contributed by QNX Software Systems Ltd.
#include "regcache.h"
#include "target.h"
-#include "gdb_assert.h"
-#include "gdb_string.h"
-
#include "i386-tdep.h"
#include "i387-tdep.h"
#include "nto-tdep.h"
#include "solib.h"
#include "solib-svr4.h"
-/* Target vector for QNX NTO x86. */
-static struct nto_target_ops i386_nto_target;
-
#ifndef X86_CPU_FXSR
#define X86_CPU_FXSR (1L << 12)
#endif
static void
i386nto_supply_gregset (struct regcache *regcache, char *gpregs)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- if(tdep->gregset == NULL)
- tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
- i386_collect_gregset);
-
gdb_assert (tdep->gregset_reg_offset == i386nto_gregset_reg_offset);
- tdep->gregset->supply_regset (tdep->gregset, regcache, -1,
- gpregs, NUM_GPREGS * 4);
+ i386_gregset.supply_regset (&i386_gregset, regcache, -1,
+ gpregs, NUM_GPREGS * 4);
}
static void
return NTO_REG_END;
else if (regno < I386_NUM_GREGS)
return NTO_REG_GENERAL;
- else if (regno < I386_NUM_GREGS + I386_NUM_FREGS)
+ else if (regno < I386_NUM_GREGS + I387_NUM_REGS)
return NTO_REG_FLOAT;
+ else if (regno < I386_SSE_NUM_REGS)
+ return NTO_REG_FLOAT; /* We store xmm registers in fxsave_area. */
return -1; /* Error. */
}
static int
-i386nto_register_area (int regno, int regset, unsigned *off)
+i386nto_register_area (struct gdbarch *gdbarch,
+ int regno, int regset, unsigned *off)
{
- int len;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
*off = 0;
if (regset == NTO_REG_GENERAL)
}
else if (regset == NTO_REG_FLOAT)
{
- unsigned off_adjust, regsize, regset_size;
+ unsigned off_adjust, regsize, regset_size, regno_base;
+ /* The following are flags indicating number in our fxsave_area. */
+ int first_four = (regno >= I387_FCTRL_REGNUM (tdep)
+ && regno <= I387_FISEG_REGNUM (tdep));
+ int second_four = (regno > I387_FISEG_REGNUM (tdep)
+ && regno <= I387_FOP_REGNUM (tdep));
+ int st_reg = (regno >= I387_ST0_REGNUM (tdep)
+ && regno < I387_ST0_REGNUM (tdep) + 8);
+ int xmm_reg = (regno >= I387_XMM0_REGNUM (tdep)
+ && regno < I387_MXCSR_REGNUM (tdep));
if (nto_cpuinfo_valid && nto_cpuinfo_flags | X86_CPU_FXSR)
{
off_adjust = 32;
regsize = 16;
regset_size = 512;
+ /* fxsave_area structure. */
+ if (first_four)
+ {
+ /* fpu_control_word, fpu_status_word, fpu_tag_word, fpu_operand
+ registers. */
+ regsize = 2; /* Two bytes each. */
+ off_adjust = 0;
+ regno_base = I387_FCTRL_REGNUM (tdep);
+ }
+ else if (second_four)
+ {
+ /* fpu_ip, fpu_cs, fpu_op, fpu_ds registers. */
+ regsize = 4;
+ off_adjust = 8;
+ regno_base = I387_FISEG_REGNUM (tdep) + 1;
+ }
+ else if (st_reg)
+ {
+ /* ST registers. */
+ regsize = 16;
+ off_adjust = 32;
+ regno_base = I387_ST0_REGNUM (tdep);
+ }
+ else if (xmm_reg)
+ {
+ /* XMM registers. */
+ regsize = 16;
+ off_adjust = 160;
+ regno_base = I387_XMM0_REGNUM (tdep);
+ }
+ else if (regno == I387_MXCSR_REGNUM (tdep))
+ {
+ regsize = 4;
+ off_adjust = 24;
+ regno_base = I387_MXCSR_REGNUM (tdep);
+ }
+ else
+ {
+ /* Whole regset. */
+ gdb_assert (regno == -1);
+ off_adjust = 0;
+ regno_base = 0;
+ regsize = regset_size;
+ }
}
else
{
- off_adjust = 28;
- regsize = 10;
- regset_size = 128;
+ regset_size = 108;
+ /* fsave_area structure. */
+ if (first_four || second_four)
+ {
+ /* fpu_control_word, ... , fpu_ds registers. */
+ regsize = 4;
+ off_adjust = 0;
+ regno_base = I387_FCTRL_REGNUM (tdep);
+ }
+ else if (st_reg)
+ {
+ /* One of ST registers. */
+ regsize = 10;
+ off_adjust = 7 * 4;
+ regno_base = I387_ST0_REGNUM (tdep);
+ }
+ else
+ {
+ /* Whole regset. */
+ gdb_assert (regno == -1);
+ off_adjust = 0;
+ regno_base = 0;
+ regsize = regset_size;
+ }
}
- if (regno == -1)
- return regset_size;
-
- *off = (regno - gdbarch_fp0_regnum (current_gdbarch))
- * regsize + off_adjust;
- return 10;
- /* Why 10 instead of regsize? GDB only stores 10 bytes per FP
- register so if we're sending a register back to the target,
- we only want pdebug to write 10 bytes so as not to clobber
- the reserved 6 bytes in the fxsave structure. */
+ if (regno != -1)
+ *off = off_adjust + (regno - regno_base) * regsize;
+ else
+ *off = 0;
+ return regsize;
}
return -1;
}
{
int offset = nto_reg_offset (regno);
if (offset != -1)
- regcache_raw_collect (regcache, regno, data + offset);
+ regcache->raw_collect (regno, data + offset);
}
}
else if (regset == NTO_REG_FLOAT)
return 0;
}
-/* Return whether the frame preceding NEXT_FRAME corresponds to a QNX
- Neutrino sigtramp routine. */
+/* Return whether THIS_FRAME corresponds to a QNX Neutrino sigtramp
+ routine. */
static int
-i386nto_sigtramp_p (struct frame_info *next_frame)
+i386nto_sigtramp_p (struct frame_info *this_frame)
{
- CORE_ADDR pc = frame_pc_unwind (next_frame);
- char *name;
+ CORE_ADDR pc = get_frame_pc (this_frame);
+ const char *name;
find_pc_partial_function (pc, &name, NULL, NULL);
return name && strcmp ("__signalstub", name) == 0;
}
-#define I386_NTO_SIGCONTEXT_OFFSET 136
-
-/* Assuming NEXT_FRAME is a frame following a QNX Neutrino sigtramp
- routine, return the address of the associated sigcontext structure. */
+/* Assuming THIS_FRAME is a QNX Neutrino sigtramp routine, return the
+ address of the associated sigcontext structure. */
static CORE_ADDR
-i386nto_sigcontext_addr (struct frame_info *next_frame)
+i386nto_sigcontext_addr (struct frame_info *this_frame)
{
- char buf[4];
- CORE_ADDR sp;
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ gdb_byte buf[4];
+ CORE_ADDR ptrctx;
- frame_unwind_register (next_frame, I386_ESP_REGNUM, buf);
- sp = extract_unsigned_integer (buf, 4);
+ /* We store __ucontext_t addr in EDI register. */
+ get_frame_register (this_frame, I386_EDI_REGNUM, buf);
+ ptrctx = extract_unsigned_integer (buf, 4, byte_order);
+ ptrctx += 24 /* Context pointer is at this offset. */;
- return sp + I386_NTO_SIGCONTEXT_OFFSET;
+ return ptrctx;
}
static void
init_i386nto_ops (void)
{
- i386_nto_target.regset_id = i386nto_regset_id;
- i386_nto_target.supply_gregset = i386nto_supply_gregset;
- i386_nto_target.supply_fpregset = i386nto_supply_fpregset;
- i386_nto_target.supply_altregset = nto_dummy_supply_regset;
- i386_nto_target.supply_regset = i386nto_supply_regset;
- i386_nto_target.register_area = i386nto_register_area;
- i386_nto_target.regset_fill = i386nto_regset_fill;
- i386_nto_target.fetch_link_map_offsets =
+ nto_regset_id = i386nto_regset_id;
+ nto_supply_gregset = i386nto_supply_gregset;
+ nto_supply_fpregset = i386nto_supply_fpregset;
+ nto_supply_altregset = nto_dummy_supply_regset;
+ nto_supply_regset = i386nto_supply_regset;
+ nto_register_area = i386nto_register_area;
+ nto_regset_fill = i386nto_regset_fill;
+ nto_fetch_link_map_offsets =
svr4_ilp32_fetch_link_map_offsets;
}
tdep->sigtramp_p = i386nto_sigtramp_p;
tdep->sigcontext_addr = i386nto_sigcontext_addr;
- tdep->sc_pc_offset = 56;
- tdep->sc_sp_offset = 68;
+ tdep->sc_reg_offset = i386nto_gregset_reg_offset;
+ tdep->sc_num_regs = ARRAY_SIZE (i386nto_gregset_reg_offset);
/* Setjmp()'s return PC saved in EDX (5). */
tdep->jb_pc_offset = 20; /* 5x32 bit ints in. */
}
set_solib_ops (gdbarch, &nto_svr4_so_ops);
- nto_set_target (&i386_nto_target);
+ set_gdbarch_wchar_bit (gdbarch, 32);
+ set_gdbarch_wchar_signed (gdbarch, 0);
}
void