/* Target-dependent code for GDB, the GNU debugger.
- Copyright 2001
+ Copyright 2001, 2002, 2003
Free Software Foundation, Inc.
This file is part of GDB.
#ifndef I386_TDEP_H
#define I386_TDEP_H
-#if !defined (FPU_REG_RAW_SIZE) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
+struct reggroup;
+struct gdbarch;
+struct frame_info;
+
+/* GDB's i386 target supports both the 32-bit Intel Architecture
+ (IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
+ a similar register layout for both.
+
+ - General purpose registers
+ - FPU data registers
+ - FPU control registers
+ - SSE data registers
+ - SSE control register
+
+ The general purpose registers for the x86-64 architecture are quite
+ different from IA-32. Therefore, the FP0_REGNUM target macro
+ determines the register number at which the FPU data registers
+ start. The number of FPU data and control registers is the same
+ for both architectures. The number of SSE registers however,
+ differs and is determined by the num_xmm_regs member of `struct
+ gdbarch_tdep'. */
+
+/* Convention for returning structures. */
+
+enum struct_return
+{
+ pcc_struct_return, /* Return "short" structures in memory. */
+ reg_struct_return /* Return "short" structures in registers. */
+};
+
+/* i386 architecture specific information. */
+struct gdbarch_tdep
+{
+ /* Number of SSE registers. */
+ int num_xmm_regs;
+
+ /* Offset of saved PC in jmp_buf. */
+ int jb_pc_offset;
+
+ /* Convention for returning structures. */
+ enum struct_return struct_return;
+
+ /* Address range where sigtramp lives. */
+ CORE_ADDR sigtramp_start;
+ CORE_ADDR sigtramp_end;
+
+ /* Get address of sigcontext for sigtramp. */
+ CORE_ADDR (*sigcontext_addr) (struct frame_info *);
+
+ /* Offset of registers in `struct sigcontext'. */
+ int *sc_reg_offset;
+ int sc_num_regs;
+
+ /* Offset of saved PC and SP in `struct sigcontext'. Usage of these
+ is deprecated, please use `sc_reg_offset' instead. */
+ int sc_pc_offset;
+ int sc_sp_offset;
+};
+
+/* Floating-point registers. */
+
#define FPU_REG_RAW_SIZE 10
-#endif
-
-#if !defined (XMM0_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define XMM0_REGNUM FIRST_XMM_REGNUM
-#endif
-#if !defined (FIRST_FPU_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FIRST_FPU_REGNUM FP0_REGNUM
-#endif
-#if !defined (LAST_FPU_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define LAST_FPU_REGNUM (gdbarch_tdep (current_gdbarch)->last_fpu_regnum)
-#endif
-#if !defined (FIRST_XMM_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FIRST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->first_xmm_regnum)
-#endif
-#if !defined (LAST_XMM_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define LAST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->last_xmm_regnum)
-#endif
-#if !defined (MXCSR_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define MXCSR_REGNUM (gdbarch_tdep (current_gdbarch)->mxcsr_regnum)
-#endif
-#if !defined (FIRST_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FIRST_FPU_CTRL_REGNUM (gdbarch_tdep (current_gdbarch)->first_fpu_ctrl_regnum)
-#endif
-#if !defined (LAST_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define LAST_FPU_CTRL_REGNUM (FIRST_FPU_CTRL_REGNUM + 7)
-#endif
-
-/* All of these control registers (except for FCOFF and FDOFF) are
- sixteen bits long (at most) in the FPU, but are zero-extended to
- thirty-two bits in GDB's register file. This makes it easier to
- compute the size of the control register file, and somewhat easier
- to convert to and from the FSAVE instruction's 32-bit format. */
+
+/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
+ (at most) in the FPU, but are zero-extended to 32 bits in GDB's
+ register cache. */
+
+/* "Generic" floating point control register. */
+#define FPC_REGNUM (FP0_REGNUM + 8)
+
/* FPU control word. */
-#if !defined (FCTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FCTRL_REGNUM (FIRST_FPU_CTRL_REGNUM)
-#endif
+#define FCTRL_REGNUM FPC_REGNUM
+
/* FPU status word. */
-#if !defined (FSTAT_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FSTAT_REGNUM (FIRST_FPU_CTRL_REGNUM + 1)
-#endif
+#define FSTAT_REGNUM (FPC_REGNUM + 1)
+
/* FPU register tag word. */
-#if !defined (FTAG_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FTAG_REGNUM (FIRST_FPU_CTRL_REGNUM + 2)
-#endif
-/* FPU instruction's code segment selector 16 bits, called "FPU Instruction
- Pointer Selector" in the x86 manuals. */
-#if !defined (FCS_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FCS_REGNUM (FIRST_FPU_CTRL_REGNUM + 3)
-#endif
-/* FPU instruction's offset within segment ("Fpu Code OFFset"). */
-#if !defined (FCOFF_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FCOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 4)
-#endif
+#define FTAG_REGNUM (FPC_REGNUM + 2)
+
+/* FPU instruction's code segment selector, called "FPU Instruction
+ Pointer Selector" in the IA-32 manuals. */
+#define FISEG_REGNUM (FPC_REGNUM + 3)
+
+/* FPU instruction's offset within segment. */
+#define FIOFF_REGNUM (FPC_REGNUM + 4)
+
/* FPU operand's data segment. */
-#if !defined (FDS_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FDS_REGNUM (FIRST_FPU_CTRL_REGNUM + 5)
-#endif
-/* FPU operand's offset within segment. */
-#if !defined (FDOFF_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FDOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 6)
-#endif
+#define FOSEG_REGNUM (FPC_REGNUM + 5)
+
+/* FPU operand's offset within segment */
+#define FOOFF_REGNUM (FPC_REGNUM + 6)
+
/* FPU opcode, bottom eleven bits. */
-#if !defined (FOP_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define FOP_REGNUM (FIRST_FPU_CTRL_REGNUM + 7)
-#endif
+#define FOP_REGNUM (FPC_REGNUM + 7)
-/* i386 architecture specific information. */
-struct gdbarch_tdep
-{
- int last_fpu_regnum;
- int first_xmm_regnum;
- int last_xmm_regnum;
- int mxcsr_regnum; /* Streaming SIMD Extension control/status. */
- int first_fpu_ctrl_regnum;
-};
+/* Return non-zero if REGNUM matches the FP register and the FP
+ register set is active. */
+extern int i386_fp_regnum_p (int regnum);
+extern int i386_fpc_regnum_p (int regnum);
+
+/* SSE registers. */
+
+/* First SSE data register. */
+#define XMM0_REGNUM (FPC_REGNUM + 8)
+
+/* SSE control/status register. */
+#define MXCSR_REGNUM \
+ (XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs)
+
+/* Return non-zero if REGNUM matches the SSE register and the SSE
+ register set is active. */
+extern int i386_sse_regnum_p (int regnum);
+extern int i386_mxcsr_regnum_p (int regnum);
+
+/* FIXME: kettenis/2001-11-24: Obsolete macro's. */
+#define FCS_REGNUM FISEG_REGNUM
+#define FCOFF_REGNUM FIOFF_REGNUM
+#define FDS_REGNUM FOSEG_REGNUM
+#define FDOFF_REGNUM FOOFF_REGNUM
+
+/* Register numbers of various important registers. */
+
+#define I386_EAX_REGNUM 0 /* %eax */
+#define I386_EDX_REGNUM 2 /* %edx */
+#define I386_ESP_REGNUM 4 /* %esp */
+#define I386_EBP_REGNUM 5 /* %ebp */
+#define I386_EIP_REGNUM 8 /* %eip */
+#define I386_EFLAGS_REGNUM 9 /* %eflags */
+#define I386_ST0_REGNUM 16 /* %st(0) */
+
+#define I386_NUM_GREGS 16
+#define I386_NUM_FREGS 16
+#define I386_NUM_XREGS 9
+
+#define I386_SSE_NUM_REGS (I386_NUM_GREGS + I386_NUM_FREGS \
+ + I386_NUM_XREGS)
+
+/* Size of the largest register. */
+#define I386_MAX_REGISTER_SIZE 16
+
+/* Functions exported from i386-tdep.c. */
+extern CORE_ADDR i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name);
+extern int i386_frameless_signal_p (struct frame_info *frame);
+
+/* Return the name of register REG. */
+extern char const *i386_register_name (int reg);
+
+/* Return non-zero if REGNUM is a member of the specified group. */
+extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
+ struct reggroup *group);
+
+/* Initialize a basic ELF architecture variant. */
+extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);
+
+/* Initialize a SVR4 architecture variant. */
+extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);
+\f
+
+/* Functions and variables exported from i386bsd-tdep.c. */
+
+extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
+extern CORE_ADDR i386fbsd_sigtramp_start;
+extern CORE_ADDR i386fbsd_sigtramp_end;
+extern CORE_ADDR i386obsd_sigtramp_start;
+extern CORE_ADDR i386obsd_sigtramp_end;
+extern int i386fbsd4_sc_reg_offset[];
+extern int i386fbsd_sc_reg_offset[];
+extern int i386nbsd_sc_reg_offset[];
+extern int i386obsd_sc_reg_offset[];
+extern int i386bsd_sc_reg_offset[];
+
+#endif /* i386-tdep.h */
-#if !defined (IS_FP_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define IS_FP_REGNUM(n) (FIRST_FPU_REGNUM <= (n) && (n) <= LAST_FPU_REGNUM)
-#endif
-#if !defined (IS_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define IS_FPU_CTRL_REGNUM(n) (FIRST_FPU_CTRL_REGNUM <= (n) && (n) <= LAST_FPU_CTRL_REGNUM)
-#endif
-#if !defined (IS_SSE_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
-#define IS_SSE_REGNUM(n) (FIRST_XMM_REGNUM <= (n) && (n) <= LAST_XMM_REGNUM)
-#endif
-
-#endif
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