/* Target-dependent code for Xilinx MicroBlaze.
- Copyright (C) 2009-2013 Free Software Foundation, Inc.
+ Copyright (C) 2009-2019 Free Software Foundation, Inc.
This file is part of GDB.
{
};
-struct microblaze_frame_cache
-{
- /* Base address. */
- CORE_ADDR base;
- CORE_ADDR pc;
-
- /* Do we have a frame? */
- int frameless_p;
-
- /* Frame size. */
- int framesize;
-
- /* Frame register. */
- int fp_regnum;
-
- /* Offsets to saved registers. */
- int register_offsets[57]; /* Must match MICROBLAZE_NUM_REGS. */
-
- /* Table of saved registers. */
- struct trad_frame_saved_reg *saved_regs;
-};
-
/* Register numbers. */
-enum microblaze_regnum
+enum microblaze_regnum
{
MICROBLAZE_R0_REGNUM,
MICROBLAZE_R1_REGNUM, MICROBLAZE_SP_REGNUM = MICROBLAZE_R1_REGNUM,
MICROBLAZE_RTLBX_REGNUM,
MICROBLAZE_RTLBSX_REGNUM,
MICROBLAZE_RTLBLO_REGNUM,
- MICROBLAZE_RTLBHI_REGNUM
+ MICROBLAZE_RTLBHI_REGNUM,
+ MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM,
+ MICROBLAZE_SHR_REGNUM,
+ MICROBLAZE_NUM_REGS
};
+struct microblaze_frame_cache
+{
+ /* Base address. */
+ CORE_ADDR base;
+ CORE_ADDR pc;
+
+ /* Do we have a frame? */
+ int frameless_p;
+
+ /* Frame size. */
+ int framesize;
+
+ /* Frame register. */
+ int fp_regnum;
+
+ /* Offsets to saved registers. */
+ int register_offsets[MICROBLAZE_NUM_REGS];
+
+ /* Table of saved registers. */
+ struct trad_frame_saved_reg *saved_regs;
+};
/* All registers are 32 bits. */
#define MICROBLAZE_REGISTER_SIZE 4