struct target_desc *mips_tdesc_gp32;
struct target_desc *mips_tdesc_gp64;
+/* The current set of options to be passed to the disassembler. */
+static char *mips_disassembler_options;
+
+/* Implicit disassembler options for individual ABIs. These tell
+ libopcodes to use general-purpose register names corresponding
+ to the ABI we have selected, perhaps via a `set mips abi ...'
+ override, rather than ones inferred from the ABI set in the ELF
+ headers of the binary file selected for debugging. */
+static const char mips_disassembler_options_o32[] = "gpr-names=32";
+static const char mips_disassembler_options_n32[] = "gpr-names=n32";
+static const char mips_disassembler_options_n64[] = "gpr-names=64";
+
const struct mips_regnum *
mips_regnum (struct gdbarch *gdbarch)
{
fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
}
if (in != NULL)
- regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
- in + buf_offset);
+ regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset);
if (out != NULL)
- regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
- out + buf_offset);
+ regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset);
if (mips_debug && in != NULL)
{
int i;
gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
&& cookednum < 2 * gdbarch_num_regs (gdbarch));
if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
- regcache_raw_write (regcache, rawnum, buf);
+ regcache->raw_write (rawnum, buf);
else if (register_size (gdbarch, rawnum) >
register_size (gdbarch, cookednum))
{
if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
- regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
+ regcache->raw_write_part (rawnum, 0, 4, buf);
else
{
/* Sign extend the shortened version of the register prior
}
/* Should the upper word of 64-bit addresses be zeroed? */
-enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
+static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
static int
mips_mask_address_p (struct gdbarch_tdep *tdep)
switch (micromips_op (insn >> 16))
{
case 0x00: /* POOL32A: bits 000000 */
- if (b0s6_op (insn) == 0x3c
- /* POOL32Axf: bits 000000 ... 111100 */
- && (b6s10_ext (insn) & 0x2bf) == 0x3c)
- /* JALR, JALR.HB: 000000 000x111100 111100 */
- /* JALRS, JALRS.HB: 000000 010x111100 111100 */
- pc = regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16));
+ switch (b0s6_op (insn))
+ {
+ case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
+ switch (b6s10_ext (insn))
+ {
+ case 0x3c: /* JALR: 000000 0000111100 111100 */
+ case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
+ case 0x13c: /* JALRS: 000000 0100111100 111100 */
+ case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
+ pc = regcache_raw_get_signed (regcache,
+ b0s5_reg (insn >> 16));
+ break;
+ case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
+ {
+ struct gdbarch_tdep *tdep;
+
+ tdep = gdbarch_tdep (gdbarch);
+ if (tdep->syscall_next_pc != NULL)
+ pc = tdep->syscall_next_pc (get_current_frame ());
+ }
+ break;
+ }
+ break;
+ }
break;
case 0x10: /* POOL32I: bits 010000 */
static std::vector<CORE_ADDR>
mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
{
- CORE_ADDR breaks[2] = {-1, -1};
+ CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX};
CORE_ADDR loc = pc;
CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
ULONGEST insn;
{
const int atomic_sequence_length = 16; /* Instruction sequence length. */
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
- CORE_ADDR breaks[2] = {-1, -1};
+ CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX};
CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's
destination. */
CORE_ADDR loc = pc;
memaddr &= (info->mach == bfd_mach_mips16
|| info->mach == bfd_mach_mips_micromips) ? ~1 : ~3;
- /* Set the disassembler options. */
- if (!info->disassembler_options)
- /* This string is not recognized explicitly by the disassembler,
- but it tells the disassembler to not try to guess the ABI from
- the bfd elf headers, such that, if the user overrides the ABI
- of a program linked as NewABI, the disassembly will follow the
- register naming conventions specified by the user. */
- info->disassembler_options = "gpr-names=32";
-
return default_print_insn (memaddr, info);
}
-static int
-gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
-{
- /* Set up the disassembler info, so that we get the right
- register names from libopcodes. */
- info->disassembler_options = "gpr-names=n32";
- info->flavour = bfd_target_elf_flavour;
-
- return gdb_print_insn_mips (memaddr, info);
-}
-
-static int
-gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
-{
- /* Set up the disassembler info, so that we get the right
- register names from libopcodes. */
- info->disassembler_options = "gpr-names=64";
- info->flavour = bfd_target_elf_flavour;
-
- return gdb_print_insn_mips (memaddr, info);
-}
-
/* Implement the breakpoint_kind_from_pc gdbarch method. */
static int
fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
mips_abi);
+ /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
+ if (mips_abi != MIPS_ABI_EABI32
+ && mips_abi != MIPS_ABI_O32
+ && info.bfd_arch_info != NULL
+ && info.bfd_arch_info->arch == bfd_arch_mips
+ && info.bfd_arch_info->bits_per_word < 64)
+ info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000);
+
/* Determine the default compressed ISA. */
if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0
&& (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0)
set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
- if (mips_abi == MIPS_ABI_N32)
- set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
- else if (mips_abi == MIPS_ABI_N64)
- set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
+ set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
+ if (mips_abi == MIPS_ABI_N64)
+ set_gdbarch_disassembler_options_implicit
+ (gdbarch, (const char *) mips_disassembler_options_n64);
+ else if (mips_abi == MIPS_ABI_N32)
+ set_gdbarch_disassembler_options_implicit
+ (gdbarch, (const char *) mips_disassembler_options_n32);
else
- set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
+ set_gdbarch_disassembler_options_implicit
+ (gdbarch, (const char *) mips_disassembler_options_o32);
+ set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options);
+ set_gdbarch_valid_disassembler_options (gdbarch,
+ disassembler_options_mips ());
/* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
projects / deliverable / binutils-gdb.git / blobdiff