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[deliverable/binutils-gdb.git] / gdb / ppc-linux-nat.c

diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
index 02095e992f7e48593438bd492e48fabb37118ca4..90a99192864401932cef2c498e3be72550369d2d 100644 (file)
--- a/gdb/ppc-linux-nat.c
+++ b/gdb/ppc-linux-nat.c
@@ -212,8 +212,19 @@ ppc_register_u_addr (int regno)
     u_addr = PT_MSR * wordsize;
   if (tdep->ppc_fpscr_regnum >= 0
       && regno == tdep->ppc_fpscr_regnum)
-    u_addr = PT_FPSCR * wordsize;
-
+    {
+      /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
+        kernel headers incorrectly contained the 32-bit definition of
+        PT_FPSCR.  For the 32-bit definition, floating-point
+        registers occupy two 32-bit "slots", and the FPSCR lives in
+        the secondhalf of such a slot-pair (hence +1).  For 64-bit,
+        the FPSCR instead occupies the full 64-bit 2-word-slot and
+        hence no adjustment is necessary.  Hack around this.  */
+      if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
+       u_addr = (48 + 32) * wordsize;
+      else
+       u_addr = PT_FPSCR * wordsize;
+    }
   return u_addr;
 }
 
@@ -237,7 +248,7 @@ fetch_altivec_register (int tid, int regno)
           have_ptrace_getvrregs = 0;
           return;
         }
-      perror_with_name ("Unable to fetch AltiVec register");
+      perror_with_name (_("Unable to fetch AltiVec register"));
     }
  
   /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
@@ -274,7 +285,7 @@ get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
             have_ptrace_getsetevrregs = 0;
           else
             /* Anything else needs to be reported.  */
-            perror_with_name ("Unable to fetch SPE registers");
+            perror_with_name (_("Unable to fetch SPE registers"));
         }
     }
 
@@ -399,7 +410,9 @@ fetch_register (int tid, int regno)
       regcache_raw_supply (current_regcache, regno, buf + padding);
     }
   else 
-    gdb_assert (0);
+    internal_error (__FILE__, __LINE__,
+                    _("fetch_register: unexpected byte order: %d"),
+                    gdbarch_byte_order (current_gdbarch));
 }
 
 static void
@@ -440,7 +453,7 @@ fetch_altivec_registers (int tid)
           have_ptrace_getvrregs = 0;
          return;
        }
-      perror_with_name ("Unable to fetch AltiVec registers");
+      perror_with_name (_("Unable to fetch AltiVec registers"));
     }
   supply_vrregset (&regs);
 }
@@ -515,7 +528,7 @@ store_altivec_register (int tid, int regno)
           have_ptrace_getvrregs = 0;
           return;
         }
-      perror_with_name ("Unable to fetch AltiVec register");
+      perror_with_name (_("Unable to fetch AltiVec register"));
     }
 
   /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
@@ -528,7 +541,7 @@ store_altivec_register (int tid, int regno)
 
   ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
   if (ret < 0)
-    perror_with_name ("Unable to store AltiVec register");
+    perror_with_name (_("Unable to store AltiVec register"));
 }
 
 /* Assuming TID referrs to an SPE process, set the top halves of TID's
@@ -555,7 +568,7 @@ set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
             have_ptrace_getsetevrregs = 0;
           else
             /* Anything else needs to be reported.  */
-            perror_with_name ("Unable to set SPE registers");
+            perror_with_name (_("Unable to set SPE registers"));
         }
     }
 }
@@ -720,13 +733,13 @@ store_altivec_registers (int tid)
           have_ptrace_getvrregs = 0;
           return;
         }
-      perror_with_name ("Couldn't get AltiVec registers");
+      perror_with_name (_("Couldn't get AltiVec registers"));
     }
 
   fill_vrregset (&regs);
   
   if (ptrace (PTRACE_SETVRREGS, tid, 0, &regs) < 0)
-    perror_with_name ("Couldn't write AltiVec registers");
+    perror_with_name (_("Couldn't write AltiVec registers"));
 }
 
 static void