Enable support for the AArch64 dot-prod instruction in the Cortex A55 and A75 cpus.

[deliverable/binutils-gdb.git] / gdb / ppc-tdep.h

diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index 11d505c0e508009ba2bc7c57a6566c9b77760ddb..4ae5c7f66e60ce91af583947cecbd0ba80ec094e 100644 (file)
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -1,6 +1,6 @@
 /* Target-dependent code for GDB, the GNU debugger.
 
-   Copyright (C) 2000-2015 Free Software Foundation, Inc.
+   Copyright (C) 2000-2017 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -76,7 +76,8 @@ int ppc_altivec_support_p (struct gdbarch *gdbarch);
 /* Return non-zero if the architecture described by GDBARCH has
    VSX registers (vsr0 --- vsr63).  */
 int vsx_support_p (struct gdbarch *gdbarch);
-int ppc_deal_with_atomic_sequence (struct frame_info *frame);
+std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
+  (struct regcache *regcache);
 
 
 /* Register set description.  */
@@ -259,6 +260,8 @@ struct gdbarch_tdep
     /* ISA-specific types.  */
     struct type *ppc_builtin_type_vec64;
     struct type *ppc_builtin_type_vec128;
+
+    int (*ppc_syscall_record) (struct regcache *regcache);
 };
 
 
@@ -302,6 +305,9 @@ enum {
   PPC_NUM_REGS
 };
 
+/* Big enough to hold the size of the largest register in bytes.  */
+#define PPC_MAX_REGISTER_SIZE  64
+
 /* An instruction to match.  */
 
 struct ppc_insn_pattern
@@ -318,6 +324,9 @@ extern CORE_ADDR ppc_insn_d_field (unsigned int insn);
 
 extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);
 
+extern int ppc_process_record (struct gdbarch *gdbarch,
+                              struct regcache *regcache, CORE_ADDR addr);
+
 /* Instruction size.  */
 #define PPC_INSN_SIZE 4