/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
- Copyright (C) 2011-2012 Free Software Foundation, Inc.
+ Copyright (C) 2011-2016 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
RL78_PSW_REGNUM, /* 8 bits */
RL78_ES_REGNUM, /* 8 bits */
RL78_CS_REGNUM, /* 8 bits */
- RL78_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
+ RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
/* Fixed address SFRs (some of those above are SFRs too.) */
RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
RL78_NUM_REGS,
/* Pseudo registers. */
- RL78_SP_REGNUM = RL78_NUM_REGS,
+ RL78_PC_REGNUM = RL78_NUM_REGS,
+ RL78_SP_REGNUM,
RL78_X_REGNUM,
RL78_A_REGNUM,
RL78_BANK3_RP2_REGNUM,
RL78_BANK3_RP3_REGNUM,
+ /* These are the same as the above 16 registers, but have
+ a pointer type for use as base registers in expression
+ evaluation. These are not user visible registers. */
+ RL78_BANK0_RP0_PTR_REGNUM,
+ RL78_BANK0_RP1_PTR_REGNUM,
+ RL78_BANK0_RP2_PTR_REGNUM,
+ RL78_BANK0_RP3_PTR_REGNUM,
+
+ RL78_BANK1_RP0_PTR_REGNUM,
+ RL78_BANK1_RP1_PTR_REGNUM,
+ RL78_BANK1_RP2_PTR_REGNUM,
+ RL78_BANK1_RP3_PTR_REGNUM,
+
+ RL78_BANK2_RP0_PTR_REGNUM,
+ RL78_BANK2_RP1_PTR_REGNUM,
+ RL78_BANK2_RP2_PTR_REGNUM,
+ RL78_BANK2_RP3_PTR_REGNUM,
+
+ RL78_BANK3_RP0_PTR_REGNUM,
+ RL78_BANK3_RP1_PTR_REGNUM,
+ RL78_BANK3_RP2_PTR_REGNUM,
+ RL78_BANK3_RP3_PTR_REGNUM,
+
RL78_NUM_TOTAL_REGS,
RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
};
+#define RL78_SP_ADDR 0xffff8
+
/* Architecture specific data. */
struct gdbarch_tdep
*rl78_uint32,
*rl78_int32,
*rl78_data_pointer,
- *rl78_code_pointer;
+ *rl78_code_pointer,
+ *rl78_psw_type;
};
/* This structure holds the results of a prologue analysis. */
int reg_offset[RL78_NUM_TOTAL_REGS];
};
+/* Construct type for PSW register. */
+
+static struct type *
+rl78_psw_type (struct gdbarch *gdbarch)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (tdep->rl78_psw_type == NULL)
+ {
+ tdep->rl78_psw_type = arch_flags_type (gdbarch,
+ "builtin_type_rl78_psw", 1);
+ append_flags_type_flag (tdep->rl78_psw_type, 0, "CY");
+ append_flags_type_flag (tdep->rl78_psw_type, 1, "ISP0");
+ append_flags_type_flag (tdep->rl78_psw_type, 2, "ISP1");
+ append_flags_type_flag (tdep->rl78_psw_type, 3, "RBS0");
+ append_flags_type_flag (tdep->rl78_psw_type, 4, "AC");
+ append_flags_type_flag (tdep->rl78_psw_type, 5, "RBS1");
+ append_flags_type_flag (tdep->rl78_psw_type, 6, "Z");
+ append_flags_type_flag (tdep->rl78_psw_type, 7, "IE");
+ }
+
+ return tdep->rl78_psw_type;
+}
+
/* Implement the "register_type" gdbarch method. */
static struct type *
if (reg_nr == RL78_PC_REGNUM)
return tdep->rl78_code_pointer;
+ else if (reg_nr == RL78_RAW_PC_REGNUM)
+ return tdep->rl78_uint32;
+ else if (reg_nr == RL78_PSW_REGNUM)
+ return rl78_psw_type (gdbarch);
else if (reg_nr <= RL78_MEM_REGNUM
|| (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
|| (RL78_BANK0_R0_REGNUM <= reg_nr
&& reg_nr <= RL78_BANK3_R7_REGNUM))
return tdep->rl78_int8;
- else
+ else if (reg_nr == RL78_SP_REGNUM
+ || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
+ && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
return tdep->rl78_data_pointer;
+ else
+ return tdep->rl78_int16;
}
/* Implement the "register_name" gdbarch method. */
"psw",
"es",
"cs",
- "pc",
+ "",
"", /* spl */
"", /* sph */
"pmc",
"mem",
+ "pc",
"sp",
"x",
"bank3_rp0",
"bank3_rp1",
"bank3_rp2",
- "bank3_rp3"
+ "bank3_rp3",
+
+ /* The 16 register slots would be named
+ bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
+ want these to be user visible registers. */
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
+ };
+
+ return reg_names[regnr];
+}
+
+/* Implement the "register_name" gdbarch method for the g10 variant. */
+
+static const char *
+rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
+{
+ static const char *const reg_names[] =
+ {
+ "", /* bank0_r0 */
+ "", /* bank0_r1 */
+ "", /* bank0_r2 */
+ "", /* bank0_r3 */
+ "", /* bank0_r4 */
+ "", /* bank0_r5 */
+ "", /* bank0_r6 */
+ "", /* bank0_r7 */
+
+ "", /* bank1_r0 */
+ "", /* bank1_r1 */
+ "", /* bank1_r2 */
+ "", /* bank1_r3 */
+ "", /* bank1_r4 */
+ "", /* bank1_r5 */
+ "", /* bank1_r6 */
+ "", /* bank1_r7 */
+
+ "", /* bank2_r0 */
+ "", /* bank2_r1 */
+ "", /* bank2_r2 */
+ "", /* bank2_r3 */
+ "", /* bank2_r4 */
+ "", /* bank2_r5 */
+ "", /* bank2_r6 */
+ "", /* bank2_r7 */
+
+ "", /* bank3_r0 */
+ "", /* bank3_r1 */
+ "", /* bank3_r2 */
+ "", /* bank3_r3 */
+ "", /* bank3_r4 */
+ "", /* bank3_r5 */
+ "", /* bank3_r6 */
+ "", /* bank3_r7 */
+
+ "psw",
+ "es",
+ "cs",
+ "",
+
+ "", /* spl */
+ "", /* sph */
+ "pmc",
+ "mem",
+
+ "pc",
+ "sp",
+
+ "x",
+ "a",
+ "c",
+ "b",
+ "e",
+ "d",
+ "l",
+ "h",
+
+ "ax",
+ "bc",
+ "de",
+ "hl",
+
+ "bank0_r0",
+ "bank0_r1",
+ "bank0_r2",
+ "bank0_r3",
+ "bank0_r4",
+ "bank0_r5",
+ "bank0_r6",
+ "bank0_r7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "bank0_rp0",
+ "bank0_rp1",
+ "bank0_rp2",
+ "bank0_rp3",
+
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+
+ /* The 16 register slots would be named
+ bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
+ want these to be user visible registers. */
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
};
return reg_names[regnr];
/* All other registers are saved and restored. */
if (group == save_reggroup || group == restore_reggroup)
{
- if (regnum < RL78_NUM_REGS)
+ if ((regnum < RL78_NUM_REGS
+ && regnum != RL78_SPL_REGNUM
+ && regnum != RL78_SPH_REGNUM
+ && regnum != RL78_RAW_PC_REGNUM)
+ || regnum == RL78_SP_REGNUM
+ || regnum == RL78_PC_REGNUM)
return 1;
else
return 0;
|| regnum == RL78_SPH_REGNUM
|| regnum == RL78_PMC_REGNUM
|| regnum == RL78_MEM_REGNUM
+ || regnum == RL78_RAW_PC_REGNUM
|| (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
return group == system_reggroup;
int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
+ RL78_RAW_BANK0_R0_REGNUM;
+ status = regcache_raw_read (regcache, raw_regnum, buffer);
+ if (status == REG_VALID)
+ status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
+ }
+ else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
+ {
+ int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
+ + RL78_RAW_BANK0_R0_REGNUM;
+
status = regcache_raw_read (regcache, raw_regnum, buffer);
if (status == REG_VALID)
status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
if (status == REG_VALID)
status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
}
+ else if (reg == RL78_PC_REGNUM)
+ {
+ gdb_byte rawbuf[4];
+
+ status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
+ memcpy (buffer, rawbuf, 3);
+ }
else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
{
ULONGEST psw;
int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
+ RL78_RAW_BANK0_R0_REGNUM;
+ regcache_raw_write (regcache, raw_regnum, buffer);
+ regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
+ }
+ else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
+ {
+ int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
+ + RL78_RAW_BANK0_R0_REGNUM;
+
regcache_raw_write (regcache, raw_regnum, buffer);
regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
}
regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
}
+ else if (reg == RL78_PC_REGNUM)
+ {
+ gdb_byte rawbuf[4];
+
+ memcpy (rawbuf, buffer, 3);
+ rawbuf[3] = 0;
+ regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
+ }
else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
{
ULONGEST psw;
gdb_assert_not_reached ("invalid pseudo register number");
}
-/* Implement the "breakpoint_from_pc" gdbarch method. */
+/* The documented BRK instruction is actually a two byte sequence,
+ {0x61, 0xcc}, but instructions may be as short as one byte.
+ Correspondence with Renesas revealed that the one byte sequence
+ 0xff is used when a one byte breakpoint instruction is required. */
+constexpr gdb_byte rl78_break_insn[] = { 0xff };
-const gdb_byte *
-rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
- int *lenptr)
-{
- /* The documented BRK instruction is actually a two byte sequence,
- {0x61, 0xcc}, but instructions may be as short as one byte.
- Correspondence with Renesas revealed that the one byte sequence
- 0xff is used when a one byte breakpoint instruction is required. */
- static gdb_byte breakpoint[] = { 0xff };
-
- *lenptr = sizeof breakpoint;
- return breakpoint;
-}
+typedef BP_MANIPULATION (rl78_break_insn) rl78_breakpoint;
/* Define a "handle" struct for fetching the next opcode. */
CORE_ADDR pc;
};
+static int
+opc_reg_to_gdb_regnum (int opcreg)
+{
+ switch (opcreg)
+ {
+ case RL78_Reg_X:
+ return RL78_X_REGNUM;
+ case RL78_Reg_A:
+ return RL78_A_REGNUM;
+ case RL78_Reg_C:
+ return RL78_C_REGNUM;
+ case RL78_Reg_B:
+ return RL78_B_REGNUM;
+ case RL78_Reg_E:
+ return RL78_E_REGNUM;
+ case RL78_Reg_D:
+ return RL78_D_REGNUM;
+ case RL78_Reg_L:
+ return RL78_L_REGNUM;
+ case RL78_Reg_H:
+ return RL78_H_REGNUM;
+ case RL78_Reg_AX:
+ return RL78_AX_REGNUM;
+ case RL78_Reg_BC:
+ return RL78_BC_REGNUM;
+ case RL78_Reg_DE:
+ return RL78_DE_REGNUM;
+ case RL78_Reg_HL:
+ return RL78_HL_REGNUM;
+ case RL78_Reg_SP:
+ return RL78_SP_REGNUM;
+ case RL78_Reg_PSW:
+ return RL78_PSW_REGNUM;
+ case RL78_Reg_CS:
+ return RL78_CS_REGNUM;
+ case RL78_Reg_ES:
+ return RL78_ES_REGNUM;
+ case RL78_Reg_PMC:
+ return RL78_PMC_REGNUM;
+ case RL78_Reg_MEM:
+ return RL78_MEM_REGNUM;
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Undefined mapping for opc reg %d"),
+ opcreg);
+ }
+
+ /* Not reached. */
+ return 0;
+}
+
/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
the memory address of the next byte to fetch. If successful,
the address in the handle is updated and the byte fetched is
static int
rl78_get_opcode_byte (void *handle)
{
- struct rl78_get_opcode_byte_handle *opcdata = handle;
+ struct rl78_get_opcode_byte_handle *opcdata
+ = (struct rl78_get_opcode_byte_handle *) handle;
int status;
gdb_byte byte;
if (value.kind == pvk_register
&& value.k == 0
&& pv_is_register (addr, RL78_SP_REGNUM)
- && size == register_size (target_gdbarch, value.reg))
+ && size == register_size (target_gdbarch (), value.reg))
result->reg_offset[value.reg] = addr.k;
}
result->reg_offset[rn] = 1;
}
- stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch));
+ stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
back_to = make_cleanup_free_pv_area (stack);
/* The call instruction has saved the return address on the stack. */
opcode_handle.pc = pc;
bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
- &opcode_handle);
+ &opcode_handle, RL78_ISA_DEFAULT);
next_pc = pc + bytes_read;
if (opc.id == RLO_sel)
-addend);
after_last_frame_setup_insn = next_pc;
}
+ else if (opc.id == RLO_mov
+ && opc.size == RL78_Word
+ && opc.op[0].type == RL78_Operand_Register
+ && opc.op[1].type == RL78_Operand_Indirect
+ && opc.op[1].addend == RL78_SP_ADDR)
+ {
+ reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
+ = reg[RL78_SP_REGNUM];
+ }
+ else if (opc.id == RLO_sub
+ && opc.size == RL78_Word
+ && opc.op[0].type == RL78_Operand_Register
+ && opc.op[1].type == RL78_Operand_Immediate)
+ {
+ int addend = opc.op[1].addend;
+ int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
+
+ reg[regnum] = pv_add_constant (reg[regnum], -addend);
+ }
+ else if (opc.id == RLO_mov
+ && opc.size == RL78_Word
+ && opc.op[0].type == RL78_Operand_Indirect
+ && opc.op[0].addend == RL78_SP_ADDR
+ && opc.op[1].type == RL78_Operand_Register)
+ {
+ reg[RL78_SP_REGNUM]
+ = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
+ after_last_frame_setup_insn = next_pc;
+ }
else
{
/* Terminate the prologue scan. */
if (!func_start)
stop_addr = func_start;
- rl78_analyze_prologue (func_start, stop_addr, *this_prologue_cache);
+ rl78_analyze_prologue (func_start, stop_addr,
+ (struct rl78_prologue *) *this_prologue_cache);
}
- return *this_prologue_cache;
+ return (struct rl78_prologue *) *this_prologue_cache;
}
/* Given a frame and a prologue cache, return this frame's base. */
if (0 <= reg && reg <= 31)
{
if ((reg & 1) == 0)
- /* Map even registers to their 16-bit counterparts. This
- is usually what is required from the DWARF info. */
- return (reg >> 1) + RL78_BANK0_RP0_REGNUM;
+ /* Map even registers to their 16-bit counterparts which have a
+ pointer type. This is usually what is required from the DWARF
+ info. */
+ return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM;
else
return reg;
}
else if (reg == 32)
return RL78_SP_REGNUM;
else if (reg == 33)
+ return -1; /* ap */
+ else if (reg == 34)
+ return RL78_PSW_REGNUM;
+ else if (reg == 35)
+ return RL78_ES_REGNUM;
+ else if (reg == 36)
+ return RL78_CS_REGNUM;
+ else if (reg == 37)
return RL78_PC_REGNUM;
else
- internal_error (__FILE__, __LINE__,
- _("Undefined dwarf2 register mapping of reg %d"),
- reg);
+ return -1;
}
/* Implement the `register_sim_regno' gdbarch method. */
static enum return_value_convention
rl78_return_value (struct gdbarch *gdbarch,
- struct type *func_type,
+ struct value *function,
struct type *valtype,
struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST valtype_len = TYPE_LENGTH (valtype);
+ int is_g10 = gdbarch_tdep (gdbarch)->elf_flags & E_FLAG_RL78_G10;
if (valtype_len > 8)
return RETURN_VALUE_STRUCT_CONVENTION;
{
ULONGEST u;
int argreg = RL78_RAW_BANK1_R0_REGNUM;
+ CORE_ADDR g10_raddr = 0xffec8;
int offset = 0;
while (valtype_len > 0)
{
- regcache_cooked_read_unsigned (regcache, argreg, &u);
+ if (is_g10)
+ u = read_memory_integer (g10_raddr, 1,
+ gdbarch_byte_order (gdbarch));
+ else
+ regcache_cooked_read_unsigned (regcache, argreg, &u);
store_unsigned_integer (readbuf + offset, 1, byte_order, u);
valtype_len -= 1;
offset += 1;
argreg++;
+ g10_raddr++;
}
}
{
ULONGEST u;
int argreg = RL78_RAW_BANK1_R0_REGNUM;
+ CORE_ADDR g10_raddr = 0xffec8;
int offset = 0;
while (valtype_len > 0)
{
u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
- regcache_cooked_write_unsigned (regcache, argreg, u);
+ if (is_g10) {
+ gdb_byte b = u & 0xff;
+ write_memory (g10_raddr, &b, 1);
+ }
+ else
+ regcache_cooked_write_unsigned (regcache, argreg, u);
valtype_len -= 1;
offset += 1;
argreg++;
+ g10_raddr++;
}
}
struct type *value_type = value_enclosing_type (args[i]);
int len = TYPE_LENGTH (value_type);
int container_len = (len + 1) & ~1;
- int offset;
sp -= container_len;
write_memory (rl78_make_data_address (sp),
/* None found, create a new architecture from the information
provided. */
- tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
+ tdep = XNEW (struct gdbarch_tdep);
gdbarch = gdbarch_alloc (&info, tdep);
tdep->elf_flags = elf_flags;
tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
tdep->rl78_data_pointer
- = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
- xstrdup ("rl78_data_addr_t"));
- TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
- TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;
-
+ = arch_pointer_type (gdbarch, 16, "rl78_data_addr_t", tdep->rl78_void);
tdep->rl78_code_pointer
- = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
- xstrdup ("rl78_code_addr_t"));
- TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
- TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
+ = arch_pointer_type (gdbarch, 32, "rl78_code_addr_t", tdep->rl78_void);
/* Registers. */
set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
- set_gdbarch_register_name (gdbarch, rl78_register_name);
+ if (tdep->elf_flags & E_FLAG_RL78_G10)
+ set_gdbarch_register_name (gdbarch, rl78_g10_register_name);
+ else
+ set_gdbarch_register_name (gdbarch, rl78_register_name);
set_gdbarch_register_type (gdbarch, rl78_register_type);
set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 16);
set_gdbarch_addr_bit (gdbarch, 32);
+ set_gdbarch_dwarf2_addr_size (gdbarch, 4);
set_gdbarch_float_bit (gdbarch, 32);
set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
set_gdbarch_double_bit (gdbarch, 32);
set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
/* Breakpoints. */
- set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
+ set_gdbarch_breakpoint_kind_from_pc (gdbarch, rl78_breakpoint::kind_from_pc);
+ set_gdbarch_sw_breakpoint_from_kind (gdbarch, rl78_breakpoint::bp_from_kind);
set_gdbarch_decr_pc_after_break (gdbarch, 1);
/* Disassembly. */
set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
set_gdbarch_frame_align (gdbarch, rl78_frame_align);
+
+ dwarf2_append_unwinders (gdbarch);
frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
/* Dummy frames, return values. */
return gdbarch;
}
+/* -Wmissing-prototypes */
+extern initialize_file_ftype _initialize_rl78_tdep;
+
/* Register the above initialization routine. */
void
projects / deliverable / binutils-gdb.git / blobdiff