/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
- Copyright (C) 2011-2014 Free Software Foundation, Inc.
+ Copyright (C) 2011-2015 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
RL78_BANK3_RP2_REGNUM,
RL78_BANK3_RP3_REGNUM,
+ /* These are the same as the above 16 registers, but have
+ a pointer type for use as base registers in expression
+ evaluation. These are not user visible registers. */
+ RL78_BANK0_RP0_PTR_REGNUM,
+ RL78_BANK0_RP1_PTR_REGNUM,
+ RL78_BANK0_RP2_PTR_REGNUM,
+ RL78_BANK0_RP3_PTR_REGNUM,
+
+ RL78_BANK1_RP0_PTR_REGNUM,
+ RL78_BANK1_RP1_PTR_REGNUM,
+ RL78_BANK1_RP2_PTR_REGNUM,
+ RL78_BANK1_RP3_PTR_REGNUM,
+
+ RL78_BANK2_RP0_PTR_REGNUM,
+ RL78_BANK2_RP1_PTR_REGNUM,
+ RL78_BANK2_RP2_PTR_REGNUM,
+ RL78_BANK2_RP3_PTR_REGNUM,
+
+ RL78_BANK3_RP0_PTR_REGNUM,
+ RL78_BANK3_RP1_PTR_REGNUM,
+ RL78_BANK3_RP2_PTR_REGNUM,
+ RL78_BANK3_RP3_PTR_REGNUM,
+
RL78_NUM_TOTAL_REGS,
RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
};
+#define RL78_SP_ADDR 0xffff8
+
/* Architecture specific data. */
struct gdbarch_tdep
*rl78_uint32,
*rl78_int32,
*rl78_data_pointer,
- *rl78_code_pointer;
+ *rl78_code_pointer,
+ *rl78_psw_type;
};
/* This structure holds the results of a prologue analysis. */
return tdep->rl78_code_pointer;
else if (reg_nr == RL78_RAW_PC_REGNUM)
return tdep->rl78_uint32;
+ else if (reg_nr == RL78_PSW_REGNUM)
+ return (tdep->rl78_psw_type);
else if (reg_nr <= RL78_MEM_REGNUM
|| (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
|| (RL78_BANK0_R0_REGNUM <= reg_nr
&& reg_nr <= RL78_BANK3_R7_REGNUM))
return tdep->rl78_int8;
- else
+ else if (reg_nr == RL78_SP_REGNUM
+ || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
+ && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
return tdep->rl78_data_pointer;
+ else
+ return tdep->rl78_int16;
}
/* Implement the "register_name" gdbarch method. */
"bank3_rp0",
"bank3_rp1",
"bank3_rp2",
- "bank3_rp3"
+ "bank3_rp3",
+
+ /* The 16 register slots would be named
+ bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
+ want these to be user visible registers. */
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
};
return reg_names[regnr];
"",
"",
"",
- ""
+ "",
+
+ /* The 16 register slots would be named
+ bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
+ want these to be user visible registers. */
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
};
return reg_names[regnr];
int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
+ RL78_RAW_BANK0_R0_REGNUM;
+ status = regcache_raw_read (regcache, raw_regnum, buffer);
+ if (status == REG_VALID)
+ status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
+ }
+ else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
+ {
+ int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
+ + RL78_RAW_BANK0_R0_REGNUM;
+
status = regcache_raw_read (regcache, raw_regnum, buffer);
if (status == REG_VALID)
status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
+ RL78_RAW_BANK0_R0_REGNUM;
+ regcache_raw_write (regcache, raw_regnum, buffer);
+ regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
+ }
+ else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
+ {
+ int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
+ + RL78_RAW_BANK0_R0_REGNUM;
+
regcache_raw_write (regcache, raw_regnum, buffer);
regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
}
CORE_ADDR pc;
};
+static int
+opc_reg_to_gdb_regnum (int opcreg)
+{
+ switch (opcreg)
+ {
+ case RL78_Reg_X:
+ return RL78_X_REGNUM;
+ case RL78_Reg_A:
+ return RL78_A_REGNUM;
+ case RL78_Reg_C:
+ return RL78_C_REGNUM;
+ case RL78_Reg_B:
+ return RL78_B_REGNUM;
+ case RL78_Reg_E:
+ return RL78_E_REGNUM;
+ case RL78_Reg_D:
+ return RL78_D_REGNUM;
+ case RL78_Reg_L:
+ return RL78_L_REGNUM;
+ case RL78_Reg_H:
+ return RL78_H_REGNUM;
+ case RL78_Reg_AX:
+ return RL78_AX_REGNUM;
+ case RL78_Reg_BC:
+ return RL78_BC_REGNUM;
+ case RL78_Reg_DE:
+ return RL78_DE_REGNUM;
+ case RL78_Reg_HL:
+ return RL78_HL_REGNUM;
+ case RL78_Reg_SP:
+ return RL78_SP_REGNUM;
+ case RL78_Reg_PSW:
+ return RL78_PSW_REGNUM;
+ case RL78_Reg_CS:
+ return RL78_CS_REGNUM;
+ case RL78_Reg_ES:
+ return RL78_ES_REGNUM;
+ case RL78_Reg_PMC:
+ return RL78_PMC_REGNUM;
+ case RL78_Reg_MEM:
+ return RL78_MEM_REGNUM;
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Undefined mapping for opc reg %d"),
+ opcreg);
+ }
+
+ /* Not reached. */
+ return 0;
+}
+
/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
the memory address of the next byte to fetch. If successful,
the address in the handle is updated and the byte fetched is
opcode_handle.pc = pc;
bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
- &opcode_handle);
+ &opcode_handle, RL78_ISA_DEFAULT);
next_pc = pc + bytes_read;
if (opc.id == RLO_sel)
-addend);
after_last_frame_setup_insn = next_pc;
}
+ else if (opc.id == RLO_mov
+ && opc.size == RL78_Word
+ && opc.op[0].type == RL78_Operand_Register
+ && opc.op[1].type == RL78_Operand_Indirect
+ && opc.op[1].addend == RL78_SP_ADDR)
+ {
+ reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
+ = reg[RL78_SP_REGNUM];
+ }
+ else if (opc.id == RLO_sub
+ && opc.size == RL78_Word
+ && opc.op[0].type == RL78_Operand_Register
+ && opc.op[1].type == RL78_Operand_Immediate)
+ {
+ int addend = opc.op[1].addend;
+ int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
+
+ reg[regnum] = pv_add_constant (reg[regnum], -addend);
+ }
+ else if (opc.id == RLO_mov
+ && opc.size == RL78_Word
+ && opc.op[0].type == RL78_Operand_Indirect
+ && opc.op[0].addend == RL78_SP_ADDR
+ && opc.op[1].type == RL78_Operand_Register)
+ {
+ reg[RL78_SP_REGNUM]
+ = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
+ after_last_frame_setup_insn = next_pc;
+ }
else
{
/* Terminate the prologue scan. */
if (0 <= reg && reg <= 31)
{
if ((reg & 1) == 0)
- /* Map even registers to their 16-bit counterparts. This
- is usually what is required from the DWARF info. */
- return (reg >> 1) + RL78_BANK0_RP0_REGNUM;
+ /* Map even registers to their 16-bit counterparts which have a
+ pointer type. This is usually what is required from the DWARF
+ info. */
+ return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM;
else
return reg;
}
TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
+ tdep->rl78_psw_type = arch_flags_type (gdbarch, "builtin_type_rl78_psw", 1);
+ append_flags_type_flag (tdep->rl78_psw_type, 0, "CY");
+ append_flags_type_flag (tdep->rl78_psw_type, 1, "ISP0");
+ append_flags_type_flag (tdep->rl78_psw_type, 2, "ISP1");
+ append_flags_type_flag (tdep->rl78_psw_type, 3, "RBS0");
+ append_flags_type_flag (tdep->rl78_psw_type, 4, "AC");
+ append_flags_type_flag (tdep->rl78_psw_type, 5, "RBS1");
+ append_flags_type_flag (tdep->rl78_psw_type, 6, "Z");
+ append_flags_type_flag (tdep->rl78_psw_type, 7, "IE");
+
/* Registers. */
set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
projects / deliverable / binutils-gdb.git / blobdiff