/* Target-dependent code for GDB, the GNU debugger.
- Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000
+ Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
+ 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
This file is part of GDB.
#include "gdbcmd.h"
#include "symfile.h"
#include "objfiles.h"
-#include "xcoffsolib.h"
#include "arch-utils.h"
+#include "regcache.h"
+#include "doublest.h"
+#include "value.h"
+#include "parser-defs.h"
-#include "bfd/libbfd.h" /* for bfd_default_set_arch_mach */
+#include "libbfd.h" /* for bfd_default_set_arch_mach */
#include "coff/internal.h" /* for libcoff.h */
-#include "bfd/libcoff.h" /* for xcoff_data */
+#include "libcoff.h" /* for xcoff_data */
+#include "coff/xcoff.h"
+#include "libxcoff.h"
#include "elf-bfd.h"
+#include "solib-svr4.h"
#include "ppc-tdep.h"
/* If the kernel has to deliver a signal, it pushes a sigcontext
the frame */
int saved_gpr; /* smallest # of saved gpr */
int saved_fpr; /* smallest # of saved fpr */
+ int saved_vr; /* smallest # of saved vr */
+ int saved_ev; /* smallest # of saved ev */
int alloca_reg; /* alloca register number (frame ptr) */
char frameless; /* true if frameless functions. */
char nosavedpc; /* true if pc not saved. */
int gpr_offset; /* offset of saved gprs from prev sp */
int fpr_offset; /* offset of saved fprs from prev sp */
+ int vr_offset; /* offset of saved vrs from prev sp */
+ int ev_offset; /* offset of saved evs from prev sp */
int lr_offset; /* offset of saved lr */
int cr_offset; /* offset of saved cr */
+ int vrsave_offset; /* offset of saved vrsave register */
};
/* Description of a single register. */
unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
unsigned char fpr; /* whether register is floating-point */
+ unsigned char pseudo; /* whether register is pseudo */
};
-/* Private data that this module attaches to struct gdbarch. */
-
-struct gdbarch_tdep
- {
- int wordsize; /* size in bytes of fixed-point word */
- int osabi; /* OS / ABI from ELF header */
- int *regoff; /* byte offsets in register arrays */
- const struct reg *regs; /* from current variant */
- };
-
-/* Return the current architecture's gdbarch_tdep structure. */
-
-#define TDEP gdbarch_tdep (current_gdbarch)
-
/* Breakpoint shadows for the single step instructions will be kept here. */
static struct sstep_breaks
struct rs6000_framedata * fdatap);
static CORE_ADDR frame_initial_stack_address (struct frame_info *);
+/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
+int
+altivec_register_p (int regno)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
+ return 0;
+ else
+ return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
+}
+
/* Read a LEN-byte address from debugged memory address MEMADDR. */
static CORE_ADDR
/* and this is a special signal frame. */
/* (fi->pc will be some low address in the kernel, */
/* to which the signal handler returns). */
- fi->signal_handler_caller = 1;
+ deprecated_set_frame_type (fi, SIGTRAMP_FRAME);
}
/* Put here the code to store, into a struct frame_saved_regs,
static CORE_ADDR
rs6000_saved_pc_after_call (struct frame_info *fi)
{
- return read_register (PPC_LR_REGNUM);
+ return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
}
/* Calculate the destination of a branch/jump. Return -1 if not a branch. */
if (ext_op == 16) /* br conditional register */
{
- dest = read_register (PPC_LR_REGNUM) & ~3;
+ dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
/* If we are about to return from a signal handler, dest is
something like 0x3c90. The current frame is a signal handler
fi = get_current_frame ();
if (fi != NULL)
dest = read_memory_addr (fi->frame + SIG_FRAME_PC_OFFSET,
- TDEP->wordsize);
+ gdbarch_tdep (current_gdbarch)->wordsize);
}
}
else if (ext_op == 528) /* br cond to count reg */
{
- dest = read_register (PPC_CTR_REGNUM) & ~3;
+ dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
/* If we are about to execute a system call, dest is something
like 0x22fc or 0x3b00. Upon completion the system call
will return to the address in the link register. */
if (dest < TEXT_SEGMENT_BASE)
- dest = read_register (PPC_LR_REGNUM) & ~3;
+ dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
}
else
return -1;
#define BIG_BREAKPOINT { 0x7d, 0x82, 0x10, 0x08 }
#define LITTLE_BREAKPOINT { 0x08, 0x10, 0x82, 0x7d }
-static unsigned char *
+const static unsigned char *
rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
{
static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
*bp_size = 4;
- if (TARGET_BYTE_ORDER == BIG_ENDIAN)
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
return big_breakpoint;
else
return little_breakpoint;
/* AIX does not support PT_STEP. Simulate it. */
void
-rs6000_software_single_step (unsigned int signal, int insert_breakpoints_p)
+rs6000_software_single_step (enum target_signal signal,
+ int insert_breakpoints_p)
{
-#define INSNLEN(OPCODE) 4
-
- static char le_breakp[] = LITTLE_BREAKPOINT;
- static char be_breakp[] = BIG_BREAKPOINT;
- char *breakp = TARGET_BYTE_ORDER == BIG_ENDIAN ? be_breakp : le_breakp;
+ CORE_ADDR dummy;
+ int breakp_sz;
+ const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
int ii, insn;
CORE_ADDR loc;
CORE_ADDR breaks[2];
insn = read_memory_integer (loc, 4);
- breaks[0] = loc + INSNLEN (insn);
+ breaks[0] = loc + breakp_sz;
opcode = insn >> 26;
breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
/* ignore invalid breakpoint. */
if (breaks[ii] == -1)
continue;
-
- read_memory (breaks[ii], stepBreaks[ii].data, 4);
-
- write_memory (breaks[ii], breakp, 4);
+ target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
stepBreaks[ii].address = breaks[ii];
}
/* remove step breakpoints. */
for (ii = 0; ii < 2; ++ii)
if (stepBreaks[ii].address != 0)
- write_memory
- (stepBreaks[ii].address, stepBreaks[ii].data, 4);
-
+ target_remove_breakpoint (stepBreaks[ii].address,
+ stepBreaks[ii].data);
}
errno = 0; /* FIXME, don't ignore errors! */
/* What errors? {read,write}_memory call error(). */
which we decrement the sp to allocate the frame.
- saved_gpr is the number of the first saved gpr.
- saved_fpr is the number of the first saved fpr.
+ - saved_vr is the number of the first saved vr.
+ - saved_ev is the number of the first saved ev.
- alloca_reg is the number of the register used for alloca() handling.
Otherwise -1.
- gpr_offset is the offset of the first saved gpr from the previous frame.
- fpr_offset is the offset of the first saved fpr from the previous frame.
+ - vr_offset is the offset of the first saved vr from the previous frame.
+ - ev_offset is the offset of the first saved ev from the previous frame.
- lr_offset is the offset of the saved lr
- cr_offset is the offset of the saved cr
+ - vrsave_offset is the offset of the saved vrsave register
*/
#define SIGNED_SHORT(x) \
#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
+/* Limit the number of skipped non-prologue instructions, as the examining
+ of the prologue is expensive. */
+static int max_skip_non_prologue_insns = 10;
+
+/* Given PC representing the starting address of a function, and
+ LIM_PC which is the (sloppy) limit to which to scan when looking
+ for a prologue, attempt to further refine this limit by using
+ the line data in the symbol table. If successful, a better guess
+ on where the prologue ends is returned, otherwise the previous
+ value of lim_pc is returned. */
+static CORE_ADDR
+refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
+{
+ struct symtab_and_line prologue_sal;
+
+ prologue_sal = find_pc_line (pc, 0);
+ if (prologue_sal.line != 0)
+ {
+ int i;
+ CORE_ADDR addr = prologue_sal.end;
+
+ /* Handle the case in which compiler's optimizer/scheduler
+ has moved instructions into the prologue. We scan ahead
+ in the function looking for address ranges whose corresponding
+ line number is less than or equal to the first one that we
+ found for the function. (It can be less than when the
+ scheduler puts a body instruction before the first prologue
+ instruction.) */
+ for (i = 2 * max_skip_non_prologue_insns;
+ i > 0 && (lim_pc == 0 || addr < lim_pc);
+ i--)
+ {
+ struct symtab_and_line sal;
+
+ sal = find_pc_line (addr, 0);
+ if (sal.line == 0)
+ break;
+ if (sal.line <= prologue_sal.line
+ && sal.symtab == prologue_sal.symtab)
+ {
+ prologue_sal = sal;
+ }
+ addr = sal.end;
+ }
+
+ if (lim_pc == 0 || prologue_sal.end < lim_pc)
+ lim_pc = prologue_sal.end;
+ }
+ return lim_pc;
+}
+
+
static CORE_ADDR
skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
{
CORE_ADDR orig_pc = pc;
- CORE_ADDR last_prologue_pc;
+ CORE_ADDR last_prologue_pc = pc;
+ CORE_ADDR li_found_pc = 0;
char buf[4];
unsigned long op;
long offset = 0;
+ long vr_saved_offset = 0;
int lr_reg = -1;
int cr_reg = -1;
+ int vr_reg = -1;
+ int ev_reg = -1;
+ long ev_offset = 0;
+ int vrsave_reg = -1;
int reg;
int framep = 0;
int minimal_toc_loaded = 0;
int prev_insn_was_prologue_insn = 1;
+ int num_skip_non_prologue_insns = 0;
+ const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ /* Attempt to find the end of the prologue when no limit is specified.
+ Note that refine_prologue_limit() has been written so that it may
+ be used to "refine" the limits of non-zero PC values too, but this
+ is only safe if we 1) trust the line information provided by the
+ compiler and 2) iterate enough to actually find the end of the
+ prologue.
+
+ It may become a good idea at some point (for both performance and
+ accuracy) to unconditionally call refine_prologue_limit(). But,
+ until we can make a clear determination that this is beneficial,
+ we'll play it safe and only use it to obtain a limit when none
+ has been specified. */
+ if (lim_pc == 0)
+ lim_pc = refine_prologue_limit (pc, lim_pc);
memset (fdata, 0, sizeof (struct rs6000_framedata));
fdata->saved_gpr = -1;
fdata->saved_fpr = -1;
+ fdata->saved_vr = -1;
+ fdata->saved_ev = -1;
fdata->alloca_reg = -1;
fdata->frameless = 1;
fdata->nosavedpc = 1;
- pc -= 4;
- while (lim_pc == 0 || pc < lim_pc - 4)
+ for (;; pc += 4)
{
- pc += 4;
-
/* Sometimes it isn't clear if an instruction is a prologue
instruction or not. When we encounter one of these ambiguous
cases, we'll set prev_insn_was_prologue_insn to 0 (false).
Otherwise, we'll assume that it really is a prologue instruction. */
if (prev_insn_was_prologue_insn)
last_prologue_pc = pc;
+
+ /* Stop scanning if we've hit the limit. */
+ if (lim_pc != 0 && pc >= lim_pc)
+ break;
+
prev_insn_was_prologue_insn = 1;
+ /* Fetch the instruction and convert it to an integer. */
if (target_read_memory (pc, buf, 4))
break;
op = extract_signed_integer (buf, 4);
}
else if ((op & 0xffff0000) == 0x60000000)
{
- /* nop */
+ /* nop */
/* Allow nops in the prologue, but do not consider them to
be part of the prologue unless followed by other prologue
instructions. */
break;
}
- else if (((op & 0xffff0000) == 0x801e0000 || /* lwz 0,NUM(r30), used
- in V.4 -mrelocatable */
- op == 0x7fc0f214) && /* add r30,r0,r30, used
- in V.4 -mrelocatable */
- lr_reg == 0x901e0000)
- {
- continue;
-
- }
- else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
- in V.4 -mminimal-toc */
+ else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
+ in V.4 -mminimal-toc */
(op & 0xffff0000) == 0x3bde0000)
{ /* addi 30,30,foo@l */
continue;
to save fprs??? */
fdata->frameless = 0;
- /* Don't skip over the subroutine call if it is not within the first
- three instructions of the prologue. */
+ /* Don't skip over the subroutine call if it is not within
+ the first three instructions of the prologue. */
if ((pc - orig_pc) > 8)
break;
op = read_memory_integer (pc + 4, 4);
- /* At this point, make sure this is not a trampoline function
- (a function that simply calls another functions, and nothing else).
- If the next is not a nop, this branch was part of the function
- prologue. */
+ /* At this point, make sure this is not a trampoline
+ function (a function that simply calls another functions,
+ and nothing else). If the next is not a nop, this branch
+ was part of the function prologue. */
if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
break; /* don't skip over
else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
(((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
(((op >> 21) & 31) <= 10) &&
- (((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
+ ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
{
continue;
/* store parameters in stack */
}
- else if ((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
- (op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
+ else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
(op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
(op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
{
{ /* mr r31, r1 */
fdata->frameless = 0;
framep = 1;
- fdata->alloca_reg = 31;
+ fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
continue;
/* Another way to set up the frame pointer. */
{ /* addi rX, r1, 0x0 */
fdata->frameless = 0;
framep = 1;
- fdata->alloca_reg = (op & ~0x38010000) >> 21;
+ fdata->alloca_reg = (tdep->ppc_gp0_regnum
+ + ((op & ~0x38010000) >> 21));
+ continue;
+ }
+ /* AltiVec related instructions. */
+ /* Store the vrsave register (spr 256) in another register for
+ later manipulation, or load a register into the vrsave
+ register. 2 instructions are used: mfvrsave and
+ mtvrsave. They are shorthand notation for mfspr Rn, SPR256
+ and mtspr SPR256, Rn. */
+ /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
+ mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
+ else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
+ {
+ vrsave_reg = GET_SRC_REG (op);
continue;
+ }
+ else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
+ {
+ continue;
+ }
+ /* Store the register where vrsave was saved to onto the stack:
+ rS is the register where vrsave was stored in a previous
+ instruction. */
+ /* 100100 sssss 00001 dddddddd dddddddd */
+ else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
+ {
+ if (vrsave_reg == GET_SRC_REG (op))
+ {
+ fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
+ vrsave_reg = -1;
+ }
+ continue;
+ }
+ /* Compute the new value of vrsave, by modifying the register
+ where vrsave was saved to. */
+ else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
+ || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
+ {
+ continue;
+ }
+ /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
+ in a pair of insns to save the vector registers on the
+ stack. */
+ /* 001110 00000 00000 iiii iiii iiii iiii */
+ /* 001110 01110 00000 iiii iiii iiii iiii */
+ else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
+ || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
+ {
+ li_found_pc = pc;
+ vr_saved_offset = SIGNED_SHORT (op);
+ }
+ /* Store vector register S at (r31+r0) aligned to 16 bytes. */
+ /* 011111 sssss 11111 00000 00111001110 */
+ else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
+ {
+ if (pc == (li_found_pc + 4))
+ {
+ vr_reg = GET_SRC_REG (op);
+ /* If this is the first vector reg to be saved, or if
+ it has a lower number than others previously seen,
+ reupdate the frame info. */
+ if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
+ {
+ fdata->saved_vr = vr_reg;
+ fdata->vr_offset = vr_saved_offset + offset;
+ }
+ vr_saved_offset = -1;
+ vr_reg = -1;
+ li_found_pc = 0;
+ }
+ }
+ /* End AltiVec related instructions. */
+
+ /* Start BookE related instructions. */
+ /* Store gen register S at (r31+uimm).
+ Any register less than r13 is volatile, so we don't care. */
+ /* 000100 sssss 11111 iiiii 01100100001 */
+ else if (arch_info->mach == bfd_mach_ppc_e500
+ && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
+ {
+ if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
+ {
+ unsigned int imm;
+ ev_reg = GET_SRC_REG (op);
+ imm = (op >> 11) & 0x1f;
+ ev_offset = imm * 8;
+ /* If this is the first vector reg to be saved, or if
+ it has a lower number than others previously seen,
+ reupdate the frame info. */
+ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+ {
+ fdata->saved_ev = ev_reg;
+ fdata->ev_offset = ev_offset + offset;
+ }
+ }
+ continue;
+ }
+ /* Store gen register rS at (r1+rB). */
+ /* 000100 sssss 00001 bbbbb 01100100000 */
+ else if (arch_info->mach == bfd_mach_ppc_e500
+ && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
+ {
+ if (pc == (li_found_pc + 4))
+ {
+ ev_reg = GET_SRC_REG (op);
+ /* If this is the first vector reg to be saved, or if
+ it has a lower number than others previously seen,
+ reupdate the frame info. */
+ /* We know the contents of rB from the previous instruction. */
+ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+ {
+ fdata->saved_ev = ev_reg;
+ fdata->ev_offset = vr_saved_offset + offset;
+ }
+ vr_saved_offset = -1;
+ ev_reg = -1;
+ li_found_pc = 0;
+ }
+ continue;
+ }
+ /* Store gen register r31 at (rA+uimm). */
+ /* 000100 11111 aaaaa iiiii 01100100001 */
+ else if (arch_info->mach == bfd_mach_ppc_e500
+ && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
+ {
+ /* Wwe know that the source register is 31 already, but
+ it can't hurt to compute it. */
+ ev_reg = GET_SRC_REG (op);
+ ev_offset = ((op >> 11) & 0x1f) * 8;
+ /* If this is the first vector reg to be saved, or if
+ it has a lower number than others previously seen,
+ reupdate the frame info. */
+ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+ {
+ fdata->saved_ev = ev_reg;
+ fdata->ev_offset = ev_offset + offset;
+ }
+ continue;
+ }
+ /* Store gen register S at (r31+r0).
+ Store param on stack when offset from SP bigger than 4 bytes. */
+ /* 000100 sssss 11111 00000 01100100000 */
+ else if (arch_info->mach == bfd_mach_ppc_e500
+ && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
+ {
+ if (pc == (li_found_pc + 4))
+ {
+ if ((op & 0x03e00000) >= 0x01a00000)
+ {
+ ev_reg = GET_SRC_REG (op);
+ /* If this is the first vector reg to be saved, or if
+ it has a lower number than others previously seen,
+ reupdate the frame info. */
+ /* We know the contents of r0 from the previous
+ instruction. */
+ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+ {
+ fdata->saved_ev = ev_reg;
+ fdata->ev_offset = vr_saved_offset + offset;
+ }
+ ev_reg = -1;
+ }
+ vr_saved_offset = -1;
+ li_found_pc = 0;
+ continue;
+ }
}
+ /* End BookE related instructions. */
+
else
{
- break;
+ /* Not a recognized prologue instruction.
+ Handle optimizer code motions into the prologue by continuing
+ the search if we have no valid frame yet or if the return
+ address is not yet saved in the frame. */
+ if (fdata->frameless == 0
+ && (lr_reg == -1 || fdata->nosavedpc == 0))
+ break;
+
+ if (op == 0x4e800020 /* blr */
+ || op == 0x4e800420) /* bctr */
+ /* Do not scan past epilogue in frameless functions or
+ trampolines. */
+ break;
+ if ((op & 0xf4000000) == 0x40000000) /* bxx */
+ /* Never skip branches. */
+ break;
+
+ if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
+ /* Do not scan too many insns, scanning insns is expensive with
+ remote targets. */
+ break;
+
+ /* Continue scanning. */
+ prev_insn_was_prologue_insn = 0;
+ continue;
}
}
/* If the first thing after skipping a prolog is a branch to a function,
this might be a call to an initializer in main(), introduced by gcc2.
- We'd like to skip over it as well. Fortunately, xlc does some extra
+ We'd like to skip over it as well. Fortunately, xlc does some extra
work before calling a function right after a prologue, thus we can
- single out such gcc2 behaviour. */
+ single out such gcc2 behaviour. */
if ((op & 0xfc000001) == 0x48000001)
if (op == 0x4def7b82)
{ /* cror 0xf, 0xf, 0xf (nop) */
- /* check and see if we are in main. If so, skip over this initializer
- function as well. */
+ /* Check and see if we are in main. If so, skip over this
+ initializer function as well. */
tmp = find_pc_misc_function (pc);
- if (tmp >= 0 && STREQ (misc_function_vector[tmp].name, "main"))
+ if (tmp >= 0 && STREQ (misc_function_vector[tmp].name, main_name ()))
return pc + 8;
}
}
*************************************************************************/
-/* Pop the innermost frame, go back to the caller. */
+/* Pop the innermost frame, go back to the caller. */
static void
rs6000_pop_frame (void)
}
/* Make sure that all registers are valid. */
- read_register_bytes (0, NULL, REGISTER_BYTES);
+ deprecated_read_register_bytes (0, NULL, REGISTER_BYTES);
- /* figure out previous %pc value. If the function is frameless, it is
+ /* Figure out previous %pc value. If the function is frameless, it is
still in the link register, otherwise walk the frames and retrieve the
- saved %pc value in the previous frame. */
+ saved %pc value in the previous frame. */
addr = get_pc_function_start (frame->pc);
(void) skip_prologue (addr, frame->pc, &fdata);
- wordsize = TDEP->wordsize;
+ wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
if (fdata.frameless)
prev_sp = sp;
else
prev_sp = read_memory_addr (sp, wordsize);
if (fdata.lr_offset == 0)
- lr = read_register (PPC_LR_REGNUM);
+ lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
else
lr = read_memory_addr (prev_sp + fdata.lr_offset, wordsize);
/* reset %pc value. */
write_register (PC_REGNUM, lr);
- /* reset register values if any was saved earlier. */
+ /* reset register values if any was saved earlier. */
if (fdata.saved_gpr != -1)
{
addr = prev_sp + fdata.gpr_offset;
for (ii = fdata.saved_gpr; ii <= 31; ++ii)
{
- read_memory (addr, ®isters[REGISTER_BYTE (ii)], wordsize);
+ read_memory (addr, &deprecated_registers[REGISTER_BYTE (ii)],
+ wordsize);
addr += wordsize;
}
}
addr = prev_sp + fdata.fpr_offset;
for (ii = fdata.saved_fpr; ii <= 31; ++ii)
{
- read_memory (addr, ®isters[REGISTER_BYTE (ii + FP0_REGNUM)], 8);
+ read_memory (addr, &deprecated_registers[REGISTER_BYTE (ii + FP0_REGNUM)], 8);
addr += 8;
}
}
}
/* Fixup the call sequence of a dummy function, with the real function
- address. Its arguments will be passed by gdb. */
+ address. Its arguments will be passed by gdb. */
static void
rs6000_fix_call_dummy (char *dummyname, CORE_ADDR pc, CORE_ADDR fun,
- int nargs, value_ptr *args, struct type *type,
+ int nargs, struct value **args, struct type *type,
int gcc_p)
{
-#define TOC_ADDR_OFFSET 20
-#define TARGET_ADDR_OFFSET 28
-
int ii;
CORE_ADDR target_addr;
if (rs6000_find_toc_address_hook != NULL)
{
CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (fun);
- write_register (PPC_TOC_REGNUM, tocvalue);
+ write_register (gdbarch_tdep (current_gdbarch)->ppc_toc_regnum,
+ tocvalue);
}
}
+/* All the ABI's require 16 byte alignment. */
+static CORE_ADDR
+rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
+{
+ return (addr & -16);
+}
+
/* Pass the arguments in either registers, or in the stack. In RS/6000,
the first eight words of the argument list (that might be less than
eight parameters if some parameters occupy more than one word) are
passed in r3..r10 registers. float and double parameters are
- passed in fpr's, in addition to that. Rest of the parameters if any
- are passed in user stack. There might be cases in which half of the
+ passed in fpr's, in addition to that. Rest of the parameters if any
+ are passed in user stack. There might be cases in which half of the
parameter is copied into registers, the other half is pushed into
stack.
If the function is returning a structure, then the return address is passed
in r3, then the first 7 words of the parameters can be passed in registers,
- starting from r4. */
+ starting from r4. */
static CORE_ADDR
-rs6000_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp,
+rs6000_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
int ii;
int argbytes; /* current argument byte */
char tmp_buffer[50];
int f_argno = 0; /* current floating point argno */
- int wordsize = TDEP->wordsize;
+ int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
- value_ptr arg = 0;
+ struct value *arg = 0;
struct type *type;
CORE_ADDR saved_sp;
- /* The first eight words of ther arguments are passed in registers. Copy
- them appropriately.
+ /* The first eight words of ther arguments are passed in registers.
+ Copy them appropriately.
If the function is returning a `struct', then the first word (which
- will be passed in r3) is used for struct return address. In that
+ will be passed in r3) is used for struct return address. In that
case we should advance one word and start from r4 register to copy
- parameters. */
+ parameters. */
ii = struct_return ? 1 : 0;
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- /* floating point arguments are passed in fpr's, as well as gpr's.
+ /* Floating point arguments are passed in fpr's, as well as gpr's.
There are 13 fpr's reserved for passing parameters. At this point
- there is no way we would run out of them. */
+ there is no way we would run out of them. */
if (len > 8)
printf_unfiltered (
"Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
- memcpy (®isters[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
+ memcpy (&deprecated_registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
VALUE_CONTENTS (arg),
len);
++f_argno;
if (len > reg_size)
{
- /* Argument takes more than one register. */
+ /* Argument takes more than one register. */
while (argbytes < len)
{
- memset (®isters[REGISTER_BYTE (ii + 3)], 0, reg_size);
- memcpy (®isters[REGISTER_BYTE (ii + 3)],
+ memset (&deprecated_registers[REGISTER_BYTE (ii + 3)], 0,
+ reg_size);
+ memcpy (&deprecated_registers[REGISTER_BYTE (ii + 3)],
((char *) VALUE_CONTENTS (arg)) + argbytes,
(len - argbytes) > reg_size
? reg_size : len - argbytes);
--ii;
}
else
- { /* Argument can fit in one register. No problem. */
- int adj = TARGET_BYTE_ORDER == BIG_ENDIAN ? reg_size - len : 0;
- memset (®isters[REGISTER_BYTE (ii + 3)], 0, reg_size);
- memcpy ((char *)®isters[REGISTER_BYTE (ii + 3)] + adj,
+ {
+ /* Argument can fit in one register. No problem. */
+ int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
+ memset (&deprecated_registers[REGISTER_BYTE (ii + 3)], 0, reg_size);
+ memcpy ((char *)&deprecated_registers[REGISTER_BYTE (ii + 3)] + adj,
VALUE_CONTENTS (arg), len);
}
++argno;
ran_out_of_registers_for_arguments:
saved_sp = read_sp ();
-#ifndef ELF_OBJECT_FORMAT
- /* location for 8 parameters are always reserved. */
+
+ /* Location for 8 parameters are always reserved. */
sp -= wordsize * 8;
- /* another six words for back chain, TOC register, link register, etc. */
+ /* Another six words for back chain, TOC register, link register, etc. */
sp -= wordsize * 6;
- /* stack pointer must be quadword aligned */
+ /* Stack pointer must be quadword aligned. */
sp &= -16;
-#endif
- /* if there are more arguments, allocate space for them in
- the stack, then push them starting from the ninth one. */
+ /* If there are more arguments, allocate space for them in
+ the stack, then push them starting from the ninth one. */
if ((argno < nargs) || argbytes)
{
for (; jj < nargs; ++jj)
{
- value_ptr val = args[jj];
+ struct value *val = args[jj];
space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
}
- /* add location required for the rest of the parameters */
+ /* Add location required for the rest of the parameters. */
space = (space + 15) & -16;
sp -= space;
- /* This is another instance we need to be concerned about securing our
- stack space. If we write anything underneath %sp (r1), we might conflict
- with the kernel who thinks he is free to use this area. So, update %sp
- first before doing anything else. */
+ /* This is another instance we need to be concerned about
+ securing our stack space. If we write anything underneath %sp
+ (r1), we might conflict with the kernel who thinks he is free
+ to use this area. So, update %sp first before doing anything
+ else. */
write_register (SP_REGNUM, sp);
- /* if the last argument copied into the registers didn't fit there
- completely, push the rest of it into stack. */
+ /* If the last argument copied into the registers didn't fit there
+ completely, push the rest of it into stack. */
if (argbytes)
{
ii += ((len - argbytes + 3) & -4) / 4;
}
- /* push the rest of the arguments into stack. */
+ /* Push the rest of the arguments into stack. */
for (; argno < nargs; ++argno)
{
len = TYPE_LENGTH (type);
- /* float types should be passed in fpr's, as well as in the stack. */
+ /* Float types should be passed in fpr's, as well as in the
+ stack. */
if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
{
printf_unfiltered (
"Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
- memcpy (®isters[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
+ memcpy (&deprecated_registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
VALUE_CONTENTS (arg),
len);
++f_argno;
}
}
else
- /* Secure stack areas first, before doing anything else. */
+ /* Secure stack areas first, before doing anything else. */
write_register (SP_REGNUM, sp);
/* set back chain properly */
}
/* Function: ppc_push_return_address (pc, sp)
- Set up the return address for the inferior function call. */
+ Set up the return address for the inferior function call. */
static CORE_ADDR
ppc_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
{
- write_register (PPC_LR_REGNUM, CALL_DUMMY_ADDRESS ());
+ write_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum,
+ CALL_DUMMY_ADDRESS ());
return sp;
}
/* Extract a function return value of type TYPE from raw register array
- REGBUF, and copy that return value into VALBUF in virtual format. */
+ REGBUF, and copy that return value into VALBUF in virtual format. */
+static void
+e500_extract_return_value (struct type *valtype, struct regcache *regbuf, void *valbuf)
+{
+ int offset = 0;
+ int vallen = TYPE_LENGTH (valtype);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
+ && vallen == 8
+ && TYPE_VECTOR (valtype))
+ {
+ regcache_raw_read (regbuf, tdep->ppc_ev0_regnum + 3, valbuf);
+ }
+ else
+ {
+ /* Return value is copied starting from r3. Note that r3 for us
+ is a pseudo register. */
+ int offset = 0;
+ int return_regnum = tdep->ppc_gp0_regnum + 3;
+ int reg_size = REGISTER_RAW_SIZE (return_regnum);
+ int reg_part_size;
+ char *val_buffer;
+ int copied = 0;
+ int i = 0;
+
+ /* Compute where we will start storing the value from. */
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ {
+ if (vallen <= reg_size)
+ offset = reg_size - vallen;
+ else
+ offset = reg_size + (reg_size - vallen);
+ }
+
+ /* How big does the local buffer need to be? */
+ if (vallen <= reg_size)
+ val_buffer = alloca (reg_size);
+ else
+ val_buffer = alloca (vallen);
+
+ /* Read all we need into our private buffer. We copy it in
+ chunks that are as long as one register, never shorter, even
+ if the value is smaller than the register. */
+ while (copied < vallen)
+ {
+ reg_part_size = REGISTER_RAW_SIZE (return_regnum + i);
+ /* It is a pseudo/cooked register. */
+ regcache_cooked_read (regbuf, return_regnum + i,
+ val_buffer + copied);
+ copied += reg_part_size;
+ i++;
+ }
+ /* Put the stuff in the return buffer. */
+ memcpy (valbuf, val_buffer + offset, vallen);
+ }
+}
static void
rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
{
int offset = 0;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
{
float ff;
/* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
We need to truncate the return value into float size (4 byte) if
- necessary. */
+ necessary. */
if (TYPE_LENGTH (valtype) > 4) /* this is a double */
memcpy (valbuf,
memcpy (valbuf, &ff, sizeof (float));
}
}
+ else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
+ && TYPE_LENGTH (valtype) == 16
+ && TYPE_VECTOR (valtype))
+ {
+ memcpy (valbuf, regbuf + REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
+ TYPE_LENGTH (valtype));
+ }
else
{
/* return value is copied starting from r3. */
- if (TARGET_BYTE_ORDER == BIG_ENDIAN
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
&& TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (3))
offset = REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype);
}
}
-/* Keep structure return address in this variable.
- FIXME: This is a horrid kludge which should not be allowed to continue
- living. This only allows a single nested call to a structure-returning
- function. Come on, guys! -- gnu@cygnus.com, Aug 92 */
+/* Return whether handle_inferior_event() should proceed through code
+ starting at PC in function NAME when stepping.
-static CORE_ADDR rs6000_struct_return_address;
+ The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
+ handle memory references that are too distant to fit in instructions
+ generated by the compiler. For example, if 'foo' in the following
+ instruction:
-/* Indirect function calls use a piece of trampoline code to do context
- switching, i.e. to set the new TOC table. Skip such code if we are on
- its first instruction (as when we have single-stepped to here).
- Also skip shared library trampoline code (which is different from
+ lwz r9,foo(r2)
+
+ is greater than 32767, the linker might replace the lwz with a branch to
+ somewhere in @FIX1 that does the load in 2 instructions and then branches
+ back to where execution should continue.
+
+ GDB should silently step over @FIX code, just like AIX dbx does.
+ Unfortunately, the linker uses the "b" instruction for the branches,
+ meaning that the link register doesn't get set. Therefore, GDB's usual
+ step_over_function() mechanism won't work.
+
+ Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
+ in handle_inferior_event() to skip past @FIX code. */
+
+int
+rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
+{
+ return name && !strncmp (name, "@FIX", 4);
+}
+
+/* Skip code that the user doesn't want to see when stepping:
+
+ 1. Indirect function calls use a piece of trampoline code to do context
+ switching, i.e. to set the new TOC table. Skip such code if we are on
+ its first instruction (as when we have single-stepped to here).
+
+ 2. Skip shared library trampoline code (which is different from
indirect function call trampolines).
+
+ 3. Skip bigtoc fixup code.
+
Result is desired PC to step until, or NULL if we are not in
- trampoline code. */
+ code that should be skipped. */
CORE_ADDR
rs6000_skip_trampoline_code (CORE_ADDR pc)
{
register unsigned int ii, op;
+ int rel;
CORE_ADDR solib_target_pc;
+ struct minimal_symbol *msymbol;
static unsigned trampoline_code[] =
{
0
};
+ /* Check for bigtoc fixup code. */
+ msymbol = lookup_minimal_symbol_by_pc (pc);
+ if (msymbol && rs6000_in_solib_return_trampoline (pc, SYMBOL_NAME (msymbol)))
+ {
+ /* Double-check that the third instruction from PC is relative "b". */
+ op = read_memory_integer (pc + 8, 4);
+ if ((op & 0xfc000003) == 0x48000000)
+ {
+ /* Extract bits 6-29 as a signed 24-bit relative word address and
+ add it to the containing PC. */
+ rel = ((int)(op << 6) >> 6);
+ return pc + 8 + rel;
+ }
+ }
+
/* If pc is in a shared library trampoline, return its target. */
solib_target_pc = find_solib_trampoline_target (pc);
if (solib_target_pc)
return 0;
}
ii = read_register (11); /* r11 holds destination addr */
- pc = read_memory_addr (ii, TDEP->wordsize); /* (r11) value */
+ pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
return pc;
}
/* Don't even think about framelessness except on the innermost frame
or if the function was interrupted by a signal. */
- if (fi->next != NULL && !fi->next->signal_handler_caller)
+ if (fi->next != NULL && !(get_frame_type (fi->next) == SIGTRAMP_FRAME))
return 0;
func_start = get_pc_function_start (fi->pc);
/* If we failed to find the start of the function, it is a mistake
- to inspect the instructions. */
+ to inspect the instructions. */
if (!func_start)
{
/* A frame with a zero PC is usually created by dereferencing a NULL
function pointer, normally causing an immediate core dump of the
- inferior. Mark function as frameless, as the inferior has no chance
+ inferior. Mark function as frameless, as the inferior has no chance
of setting up a stack frame. */
if (fi->pc == 0)
return 1;
return fdata.frameless;
}
-/* Return the PC saved in a frame */
+/* Return the PC saved in a frame. */
CORE_ADDR
rs6000_frame_saved_pc (struct frame_info *fi)
{
CORE_ADDR func_start;
struct rs6000_framedata fdata;
- int wordsize = TDEP->wordsize;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ int wordsize = tdep->wordsize;
- if (fi->signal_handler_caller)
+ if ((get_frame_type (fi) == SIGTRAMP_FRAME))
return read_memory_addr (fi->frame + SIG_FRAME_PC_OFFSET, wordsize);
if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
- return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
+ return deprecated_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
func_start = get_pc_function_start (fi->pc);
/* If we failed to find the start of the function, it is a mistake
- to inspect the instructions. */
+ to inspect the instructions. */
if (!func_start)
return 0;
if (fdata.lr_offset == 0 && fi->next != NULL)
{
- if (fi->next->signal_handler_caller)
+ if ((get_frame_type (fi->next) == SIGTRAMP_FRAME))
return read_memory_addr (fi->next->frame + SIG_FRAME_LR_OFFSET,
wordsize);
+ else if (PC_IN_CALL_DUMMY (get_next_frame (fi)->pc, 0, 0))
+ /* The link register wasn't saved by this frame and the next
+ (inner, newer) frame is a dummy. Get the link register
+ value by unwinding it from that [dummy] frame. */
+ {
+ ULONGEST lr;
+ frame_unwind_unsigned_register (get_next_frame (fi),
+ tdep->ppc_lr_regnum, &lr);
+ return lr;
+ }
else
- return read_memory_addr (FRAME_CHAIN (fi) + DEFAULT_LR_SAVE,
+ return read_memory_addr (FRAME_CHAIN (fi) + tdep->lr_frame_offset,
wordsize);
}
if (fdata.lr_offset == 0)
- return read_register (PPC_LR_REGNUM);
+ return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
return read_memory_addr (FRAME_CHAIN (fi) + fdata.lr_offset, wordsize);
}
{
CORE_ADDR frame_addr;
struct rs6000_framedata work_fdata;
- int wordsize = TDEP->wordsize;
+ struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch);
+ int wordsize = tdep->wordsize;
if (fi->saved_regs)
return;
frame_saved_regs_zalloc (fi);
/* If there were any saved registers, figure out parent's stack
- pointer. */
+ pointer. */
/* The following is true only if the frame doesn't have a call to
- alloca(), FIXME. */
-
- if (fdatap->saved_fpr == 0 && fdatap->saved_gpr == 0
- && fdatap->lr_offset == 0 && fdatap->cr_offset == 0)
+ alloca(), FIXME. */
+
+ if (fdatap->saved_fpr == 0
+ && fdatap->saved_gpr == 0
+ && fdatap->saved_vr == 0
+ && fdatap->saved_ev == 0
+ && fdatap->lr_offset == 0
+ && fdatap->cr_offset == 0
+ && fdatap->vr_offset == 0
+ && fdatap->ev_offset == 0)
frame_addr = 0;
- else if (fi->prev && fi->prev->frame)
- frame_addr = fi->prev->frame;
else
- frame_addr = read_memory_addr (fi->frame, wordsize);
+ /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
+ address of the current frame. Things might be easier if the
+ ->frame pointed to the outer-most address of the frame. In the
+ mean time, the address of the prev frame is used as the base
+ address of this frame. */
+ frame_addr = FRAME_CHAIN (fi);
/* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr.
All fpr's from saved_fpr to fp31 are saved. */
}
}
+ /* if != -1, fdatap->saved_vr is the smallest number of saved_vr.
+ All vr's from saved_vr to vr31 are saved. */
+ if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
+ {
+ if (fdatap->saved_vr >= 0)
+ {
+ int i;
+ CORE_ADDR vr_addr = frame_addr + fdatap->vr_offset;
+ for (i = fdatap->saved_vr; i < 32; i++)
+ {
+ fi->saved_regs[tdep->ppc_vr0_regnum + i] = vr_addr;
+ vr_addr += REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
+ }
+ }
+ }
+
+ /* if != -1, fdatap->saved_ev is the smallest number of saved_ev.
+ All vr's from saved_ev to ev31 are saved. ????? */
+ if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
+ {
+ if (fdatap->saved_ev >= 0)
+ {
+ int i;
+ CORE_ADDR ev_addr = frame_addr + fdatap->ev_offset;
+ for (i = fdatap->saved_ev; i < 32; i++)
+ {
+ fi->saved_regs[tdep->ppc_ev0_regnum + i] = ev_addr;
+ fi->saved_regs[tdep->ppc_gp0_regnum + i] = ev_addr + 4;
+ ev_addr += REGISTER_RAW_SIZE (tdep->ppc_ev0_regnum);
+ }
+ }
+ }
+
/* If != 0, fdatap->cr_offset is the offset from the frame that holds
the CR. */
if (fdatap->cr_offset != 0)
- fi->saved_regs[PPC_CR_REGNUM] = frame_addr + fdatap->cr_offset;
+ fi->saved_regs[tdep->ppc_cr_regnum] = frame_addr + fdatap->cr_offset;
/* If != 0, fdatap->lr_offset is the offset from the frame that holds
the LR. */
if (fdatap->lr_offset != 0)
- fi->saved_regs[PPC_LR_REGNUM] = frame_addr + fdatap->lr_offset;
+ fi->saved_regs[tdep->ppc_lr_regnum] = frame_addr + fdatap->lr_offset;
+
+ /* If != 0, fdatap->vrsave_offset is the offset from the frame that holds
+ the VRSAVE. */
+ if (fdatap->vrsave_offset != 0)
+ fi->saved_regs[tdep->ppc_vrsave_regnum] = frame_addr + fdatap->vrsave_offset;
}
/* Return the address of a frame. This is the inital %sp value when the frame
- was first allocated. For functions calling alloca(), it might be saved in
- an alloca register. */
+ was first allocated. For functions calling alloca(), it might be saved in
+ an alloca register. */
static CORE_ADDR
frame_initial_stack_address (struct frame_info *fi)
struct rs6000_framedata fdata;
struct frame_info *callee_fi;
- /* if the initial stack pointer (frame address) of this frame is known,
- just return it. */
+ /* If the initial stack pointer (frame address) of this frame is known,
+ just return it. */
if (fi->extra_info->initial_sp)
return fi->extra_info->initial_sp;
- /* find out if this function is using an alloca register.. */
+ /* Find out if this function is using an alloca register. */
(void) skip_prologue (get_pc_function_start (fi->pc), fi->pc, &fdata);
- /* if saved registers of this frame are not known yet, read and cache them. */
+ /* If saved registers of this frame are not known yet, read and
+ cache them. */
if (!fi->saved_regs)
frame_get_saved_regs (fi, &fdata);
/* If no alloca register used, then fi->frame is the value of the %sp for
- this frame, and it is good enough. */
+ this frame, and it is good enough. */
if (fdata.alloca_reg < 0)
{
return fi->extra_info->initial_sp;
}
- /* This function has an alloca register. If this is the top-most frame
- (with the lowest address), the value in alloca register is good. */
-
- if (!fi->next)
- return fi->extra_info->initial_sp = read_register (fdata.alloca_reg);
-
- /* Otherwise, this is a caller frame. Callee has usually already saved
- registers, but there are exceptions (such as when the callee
- has no parameters). Find the address in which caller's alloca
- register is saved. */
-
- for (callee_fi = fi->next; callee_fi; callee_fi = callee_fi->next)
- {
-
- if (!callee_fi->saved_regs)
- frame_get_saved_regs (callee_fi, NULL);
-
- /* this is the address in which alloca register is saved. */
-
- tmpaddr = callee_fi->saved_regs[fdata.alloca_reg];
- if (tmpaddr)
- {
- fi->extra_info->initial_sp =
- read_memory_addr (tmpaddr, TDEP->wordsize);
- return fi->extra_info->initial_sp;
- }
-
- /* Go look into deeper levels of the frame chain to see if any one of
- the callees has saved alloca register. */
- }
-
- /* If alloca register was not saved, by the callee (or any of its callees)
- then the value in the register is still good. */
-
- fi->extra_info->initial_sp = read_register (fdata.alloca_reg);
+ /* There is an alloca register, use its value, in the current frame,
+ as the initial stack pointer. */
+ {
+ char *tmpbuf = alloca (MAX_REGISTER_RAW_SIZE);
+ if (frame_register_read (fi, fdata.alloca_reg, tmpbuf))
+ {
+ fi->extra_info->initial_sp
+ = extract_unsigned_integer (tmpbuf,
+ REGISTER_RAW_SIZE (fdata.alloca_reg));
+ }
+ else
+ /* NOTE: cagney/2002-04-17: At present the only time
+ frame_register_read will fail is when the register isn't
+ available. If that does happen, use the frame. */
+ fi->extra_info->initial_sp = fi->frame;
+ }
return fi->extra_info->initial_sp;
}
(its caller). */
/* FRAME_CHAIN takes a frame's nominal address
- and produces the frame's chain-pointer. */
+ and produces the frame's chain-pointer. */
/* In the case of the RS/6000, the frame's nominal address
is the address of a 4-byte word containing the calling frame's address. */
rs6000_frame_chain (struct frame_info *thisframe)
{
CORE_ADDR fp, fpp, lr;
- int wordsize = TDEP->wordsize;
+ int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
if (PC_IN_CALL_DUMMY (thisframe->pc, thisframe->frame, thisframe->frame))
- return thisframe->frame; /* dummy frame same as caller's frame */
+ /* A dummy frame always correctly chains back to the previous
+ frame. */
+ return read_memory_addr ((thisframe)->frame, wordsize);
if (inside_entry_file (thisframe->pc) ||
thisframe->pc == entry_point_address ())
return 0;
- if (thisframe->signal_handler_caller)
+ if ((get_frame_type (thisframe) == SIGTRAMP_FRAME))
fp = read_memory_addr (thisframe->frame + SIG_FRAME_FP_OFFSET,
wordsize);
else if (thisframe->next != NULL
- && thisframe->next->signal_handler_caller
+ && (get_frame_type (thisframe->next) == SIGTRAMP_FRAME)
&& FRAMELESS_FUNCTION_INVOCATION (thisframe))
/* A frameless function interrupted by a signal did not change the
frame pointer. */
fp = FRAME_FP (thisframe);
else
fp = read_memory_addr ((thisframe)->frame, wordsize);
-
- lr = read_register (PPC_LR_REGNUM);
- if (lr == entry_point_address ())
- if (fp != 0 && (fpp = read_memory_addr (fp, wordsize)) != 0)
- if (PC_IN_CALL_DUMMY (lr, fpp, fpp))
- return fpp;
-
return fp;
}
/* Return the size of register REG when words are WORDSIZE bytes long. If REG
- isn't available with that word size, return 0. */
+ isn't available with that word size, return 0. */
static int
regsize (const struct reg *reg, int wordsize)
}
/* Return the name of register number N, or null if no such register exists
- in the current architecture. */
+ in the current architecture. */
-static char *
+static const char *
rs6000_register_name (int n)
{
- struct gdbarch_tdep *tdep = TDEP;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
const struct reg *reg = tdep->regs + n;
if (!regsize (reg, tdep->wordsize))
static int
rs6000_register_byte (int n)
{
- return TDEP->regoff[n];
+ return gdbarch_tdep (current_gdbarch)->regoff[n];
}
/* Return the number of bytes of storage in the actual machine representation
- for register N if that register is available, else return 0. */
+ for register N if that register is available, else return 0. */
static int
rs6000_register_raw_size (int n)
{
- struct gdbarch_tdep *tdep = TDEP;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
const struct reg *reg = tdep->regs + n;
return regsize (reg, tdep->wordsize);
}
-/* Number of bytes of storage in the program's representation
- for register N. */
-
-static int
-rs6000_register_virtual_size (int n)
-{
- return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (n));
-}
-
/* Return the GDB type object for the "standard" data type
of data in register N. */
static struct type *
rs6000_register_virtual_type (int n)
{
- struct gdbarch_tdep *tdep = TDEP;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
const struct reg *reg = tdep->regs + n;
- return reg->fpr ? builtin_type_double :
- regsize (reg, tdep->wordsize) == 8 ? builtin_type_int64 :
- builtin_type_int32;
+ if (reg->fpr)
+ return builtin_type_double;
+ else
+ {
+ int size = regsize (reg, tdep->wordsize);
+ switch (size)
+ {
+ case 8:
+ if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
+ return builtin_type_vec64;
+ else
+ return builtin_type_int64;
+ break;
+ case 16:
+ return builtin_type_vec128;
+ break;
+ default:
+ return builtin_type_int32;
+ break;
+ }
+ }
}
/* For the PowerPC, it appears that the debug info marks float parameters as
floats regardless of whether the function is prototyped, but the actual
values are always passed in as doubles. Tell gdb to always assume that
- floats are passed as doubles and then converted in the callee. */
+ floats are passed as doubles and then converted in the callee. */
static int
rs6000_coerce_float_to_double (struct type *formal, struct type *actual)
to virtual format.
The register format for RS/6000 floating point registers is always
- double, we need a conversion if the memory format is float. */
+ double, we need a conversion if the memory format is float. */
static int
rs6000_register_convertible (int n)
{
- const struct reg *reg = TDEP->regs + n;
+ const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n;
return reg->fpr;
}
/* Convert data from raw format for register N in buffer FROM
- to virtual format with type TYPE in buffer TO. */
+ to virtual format with type TYPE in buffer TO. */
static void
rs6000_register_convert_to_virtual (int n, struct type *type,
}
/* Convert data from virtual format with type TYPE in buffer FROM
- to raw format for register N in buffer TO. */
+ to raw format for register N in buffer TO. */
static void
rs6000_register_convert_to_raw (struct type *type, int n,
memcpy (to, from, REGISTER_RAW_SIZE (n));
}
-/* Store the address of the place in which to copy the structure the
- subroutine will return. This is called from call_function.
+static void
+e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
+ int reg_nr, void *buffer)
+{
+ int base_regnum;
+ int offset = 0;
+ char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- In RS/6000, struct return addresses are passed as an extra parameter in r3.
- In function return, callee is not responsible of returning this address
- back. Since gdb needs to find it, we will store in a designated variable
- `rs6000_struct_return_address'. */
+ if (reg_nr >= tdep->ppc_gp0_regnum
+ && reg_nr <= tdep->ppc_gplast_regnum)
+ {
+ base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
+
+ /* Build the value in the provided buffer. */
+ /* Read the raw register of which this one is the lower portion. */
+ regcache_raw_read (regcache, base_regnum, temp_buffer);
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = 4;
+ memcpy ((char *) buffer, temp_buffer + offset, 4);
+ }
+}
+
+static void
+e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
+ int reg_nr, const void *buffer)
+{
+ int base_regnum;
+ int offset = 0;
+ char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (reg_nr >= tdep->ppc_gp0_regnum
+ && reg_nr <= tdep->ppc_gplast_regnum)
+ {
+ base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
+ /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = 4;
+
+ /* Let's read the value of the base register into a temporary
+ buffer, so that overwriting the last four bytes with the new
+ value of the pseudo will leave the upper 4 bytes unchanged. */
+ regcache_raw_read (regcache, base_regnum, temp_buffer);
+
+ /* Write as an 8 byte quantity. */
+ memcpy (temp_buffer + offset, (char *) buffer, 4);
+ regcache_raw_write (regcache, base_regnum, temp_buffer);
+ }
+}
+
+/* Convert a dwarf2 register number to a gdb REGNUM. */
+static int
+e500_dwarf2_reg_to_regnum (int num)
+{
+ int regnum;
+ if (0 <= num && num <= 31)
+ return num + gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum;
+ else
+ return num;
+}
+
+/* Convert a dbx stab register number (from `r' declaration) to a gdb
+ REGNUM. */
+static int
+rs6000_stab_reg_to_regnum (int num)
+{
+ int regnum;
+ switch (num)
+ {
+ case 64:
+ regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum;
+ break;
+ case 65:
+ regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum;
+ break;
+ case 66:
+ regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum;
+ break;
+ case 76:
+ regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum;
+ break;
+ default:
+ regnum = num;
+ break;
+ }
+ return regnum;
+}
+
+/* Store the address of the place in which to copy the structure the
+ subroutine will return. */
static void
rs6000_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
{
- write_register (3, addr);
- rs6000_struct_return_address = addr;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ write_register (tdep->ppc_gp0_regnum + 3, addr);
}
/* Write into appropriate registers a function return value
of type TYPE, given in virtual format. */
+static void
+e500_store_return_value (struct type *type, char *valbuf)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ /* Everything is returned in GPR3 and up. */
+ int copied = 0;
+ int i = 0;
+ int len = TYPE_LENGTH (type);
+ while (copied < len)
+ {
+ int regnum = gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3 + i;
+ int reg_size = REGISTER_RAW_SIZE (regnum);
+ char *reg_val_buf = alloca (reg_size);
+
+ memcpy (reg_val_buf, valbuf + copied, reg_size);
+ copied += reg_size;
+ deprecated_write_register_gen (regnum, reg_val_buf);
+ i++;
+ }
+}
static void
rs6000_store_return_value (struct type *type, char *valbuf)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
if (TYPE_CODE (type) == TYPE_CODE_FLT)
/* Floating point values are returned starting from FPR1 and up.
Say a double_double_double type could be returned in
- FPR1/FPR2/FPR3 triple. */
+ FPR1/FPR2/FPR3 triple. */
- write_register_bytes (REGISTER_BYTE (FP0_REGNUM + 1), valbuf,
- TYPE_LENGTH (type));
+ deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM + 1), valbuf,
+ TYPE_LENGTH (type));
+ else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
+ {
+ if (TYPE_LENGTH (type) == 16
+ && TYPE_VECTOR (type))
+ deprecated_write_register_bytes (REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
+ valbuf, TYPE_LENGTH (type));
+ }
else
- /* Everything else is returned in GPR3 and up. */
- write_register_bytes (REGISTER_BYTE (PPC_GP0_REGNUM + 3), valbuf,
- TYPE_LENGTH (type));
+ /* Everything else is returned in GPR3 and up. */
+ deprecated_write_register_bytes (REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3),
+ valbuf, TYPE_LENGTH (type));
}
/* Extract from an array REGBUF containing the (raw) register state
as a CORE_ADDR (or an expression that can be used as one). */
static CORE_ADDR
-rs6000_extract_struct_value_address (char *regbuf)
+rs6000_extract_struct_value_address (struct regcache *regcache)
{
- return rs6000_struct_return_address;
+ /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
+ function call GDB knows the address of the struct return value
+ and hence, should not need to call this function. Unfortunately,
+ the current hand_function_call() code only saves the most recent
+ struct address leading to occasional calls. The code should
+ instead maintain a stack of such addresses (in the dummy frame
+ object). */
+ /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
+ really got no idea where the return value is being stored. While
+ r3, on function entry, contained the address it will have since
+ been reused (scratch) and hence wouldn't be valid */
+ return 0;
}
/* Return whether PC is in a dummy function call.
FIXME: This just checks for the end of the stack, which is broken
- for things like stepping through gcc nested function stubs. */
+ for things like stepping through gcc nested function stubs. */
static int
rs6000_pc_in_call_dummy (CORE_ADDR pc, CORE_ADDR sp, CORE_ADDR fp)
return sp < pc && pc < fp;
}
-/* Hook called when a new child process is started. */
+/* Hook called when a new child process is started. */
void
rs6000_create_inferior (int pid)
return addr;
/* ADDR is in the data space, so it's a special function pointer. */
- return read_memory_addr (addr, TDEP->wordsize);
+ return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
}
\f
Most of these register groups aren't anything formal. I arrived at
them by looking at the registers that occurred in more than one
- processor. */
-
-/* Convenience macros for populating register arrays. */
-
-/* Within another macro, convert S to a string. */
+ processor.
+
+ Note: kevinb/2002-04-30: Support for the fpscr register was added
+ during April, 2002. Slot 70 is being used for PowerPC and slot 71
+ for Power. For PowerPC, slot 70 was unused and was already in the
+ PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
+ slot 70 was being used for "mq", so the next available slot (71)
+ was chosen. It would have been nice to be able to make the
+ register numbers the same across processor cores, but this wasn't
+ possible without either 1) renumbering some registers for some
+ processors or 2) assigning fpscr to a really high slot that's
+ larger than any current register number. Doing (1) is bad because
+ existing stubs would break. Doing (2) is undesirable because it
+ would introduce a really large gap between fpscr and the rest of
+ the registers for most processors. */
+
+/* Convenience macros for populating register arrays. */
+
+/* Within another macro, convert S to a string. */
#define STR(s) #s
/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
- and 64 bits on 64-bit systems. */
-#define R(name) { STR(name), 4, 8, 0 }
+ and 64 bits on 64-bit systems. */
+#define R(name) { STR(name), 4, 8, 0, 0 }
/* Return a struct reg defining register NAME that's 32 bits on all
- systems. */
-#define R4(name) { STR(name), 4, 4, 0 }
+ systems. */
+#define R4(name) { STR(name), 4, 4, 0, 0 }
/* Return a struct reg defining register NAME that's 64 bits on all
- systems. */
-#define R8(name) { STR(name), 8, 8, 0 }
+ systems. */
+#define R8(name) { STR(name), 8, 8, 0, 0 }
+
+/* Return a struct reg defining register NAME that's 128 bits on all
+ systems. */
+#define R16(name) { STR(name), 16, 16, 0, 0 }
-/* Return a struct reg defining floating-point register NAME. */
-#define F(name) { STR(name), 8, 8, 1 }
+/* Return a struct reg defining floating-point register NAME. */
+#define F(name) { STR(name), 8, 8, 1, 0 }
+
+/* Return a struct reg defining a pseudo register NAME. */
+#define P(name) { STR(name), 4, 8, 0, 1}
/* Return a struct reg defining register NAME that's 32 bits on 32-bit
- systems and that doesn't exist on 64-bit systems. */
-#define R32(name) { STR(name), 4, 0, 0 }
+ systems and that doesn't exist on 64-bit systems. */
+#define R32(name) { STR(name), 4, 0, 0, 0 }
/* Return a struct reg defining register NAME that's 64 bits on 64-bit
- systems and that doesn't exist on 32-bit systems. */
-#define R64(name) { STR(name), 0, 8, 0 }
+ systems and that doesn't exist on 32-bit systems. */
+#define R64(name) { STR(name), 0, 8, 0, 0 }
-/* Return a struct reg placeholder for a register that doesn't exist. */
-#define R0 { 0, 0, 0, 0 }
+/* Return a struct reg placeholder for a register that doesn't exist. */
+#define R0 { 0, 0, 0, 0, 0 }
/* UISA registers common across all architectures, including POWER. */
/* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
/* 64 */ R(pc), R(ps)
+#define COMMON_UISA_NOFP_REGS \
+ /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
+ /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
+ /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
+ /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
+ /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
+ /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
+ /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
+ /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
+ /* 64 */ R(pc), R(ps)
+
/* UISA-level SPRs for PowerPC. */
#define PPC_UISA_SPRS \
+ /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
+
+/* UISA-level SPRs for PowerPC without floating point support. */
+#define PPC_UISA_NOFP_SPRS \
/* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
/* Segment registers, for PowerPC. */
/* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
/* 116 */ R4(dec), R(dabr), R4(ear)
+/* AltiVec registers. */
+#define PPC_ALTIVEC_REGS \
+ /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
+ /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
+ /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
+ /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
+ /*151*/R4(vscr), R4(vrsave)
+
+/* Vectors of hi-lo general purpose registers. */
+#define PPC_EV_REGS \
+ /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
+ /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
+ /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
+ /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
+
+/* Lower half of the EV registers. */
+#define PPC_GPRS_PSEUDO_REGS \
+ /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
+ /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
+ /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
+ /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31), \
+
/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
- user-level SPR's. */
+ user-level SPR's. */
static const struct reg registers_power[] =
{
COMMON_UISA_REGS,
- /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq)
+ /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
+ /* 71 */ R4(fpscr)
};
/* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
- view of the PowerPC. */
+ view of the PowerPC. */
static const struct reg registers_powerpc[] =
{
COMMON_UISA_REGS,
+ PPC_UISA_SPRS,
+ PPC_ALTIVEC_REGS
+};
+
+/* PowerPC UISA - a PPC processor as viewed by user-level
+ code, but without floating point registers. */
+static const struct reg registers_powerpc_nofp[] =
+{
+ COMMON_UISA_NOFP_REGS,
PPC_UISA_SPRS
};
-/* IBM PowerPC 403. */
+/* IBM PowerPC 403. */
static const struct reg registers_403[] =
{
COMMON_UISA_REGS,
/* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2)
};
-/* IBM PowerPC 403GC. */
+/* IBM PowerPC 403GC. */
static const struct reg registers_403GC[] =
{
COMMON_UISA_REGS,
/* 147 */ R(tbhu), R(tblu)
};
-/* Motorola PowerPC 505. */
+/* Motorola PowerPC 505. */
static const struct reg registers_505[] =
{
COMMON_UISA_REGS,
/* 119 */ R(eie), R(eid), R(nri)
};
-/* Motorola PowerPC 860 or 850. */
+/* Motorola PowerPC 860 or 850. */
static const struct reg registers_860[] =
{
COMMON_UISA_REGS,
/* 123 */ R(pir), R(mq), R(rtcu), R(rtcl)
};
-/* Motorola PowerPC 602. */
+/* Motorola PowerPC 602. */
static const struct reg registers_602[] =
{
COMMON_UISA_REGS,
/* 127 */ R(sebr), R(ser), R(sp), R(lt)
};
-/* Motorola/IBM PowerPC 603 or 603e. */
+/* Motorola/IBM PowerPC 603 or 603e. */
static const struct reg registers_603[] =
{
COMMON_UISA_REGS,
/* 127 */ R(hash2), R(imiss), R(icmp), R(rpa)
};
-/* Motorola PowerPC 604 or 604e. */
+/* Motorola PowerPC 604 or 604e. */
static const struct reg registers_604[] =
{
COMMON_UISA_REGS,
/* 127 */ R(sia), R(sda)
};
-/* Motorola/IBM PowerPC 750 or 740. */
+/* Motorola/IBM PowerPC 750 or 740. */
static const struct reg registers_750[] =
{
COMMON_UISA_REGS,
};
+/* Motorola PowerPC 7400. */
+static const struct reg registers_7400[] =
+{
+ /* gpr0-gpr31, fpr0-fpr31 */
+ COMMON_UISA_REGS,
+ /* ctr, xre, lr, cr */
+ PPC_UISA_SPRS,
+ /* sr0-sr15 */
+ PPC_SEGMENT_REGS,
+ PPC_OEA_SPRS,
+ /* vr0-vr31, vrsave, vscr */
+ PPC_ALTIVEC_REGS
+ /* FIXME? Add more registers? */
+};
+
+/* Motorola e500. */
+static const struct reg registers_e500[] =
+{
+ R(pc), R(ps),
+ /* cr, lr, ctr, xer, "" */
+ PPC_UISA_NOFP_SPRS,
+ /* 7...38 */
+ PPC_EV_REGS,
+ /* 39...70 */
+ PPC_GPRS_PSEUDO_REGS
+};
+
/* Information about a particular processor variant. */
struct variant
/* English description of the variant. */
char *description;
- /* bfd_arch_info.arch corresponding to variant. */
+ /* bfd_arch_info.arch corresponding to variant. */
enum bfd_architecture arch;
- /* bfd_arch_info.mach corresponding to variant. */
+ /* bfd_arch_info.mach corresponding to variant. */
unsigned long mach;
+ /* Number of real registers. */
+ int nregs;
+
+ /* Number of pseudo registers. */
+ int npregs;
+
+ /* Number of total registers (the sum of nregs and npregs). */
+ int num_tot_regs;
+
/* Table of register names; registers[R] is the name of the register
number R. */
- int nregs;
const struct reg *regs;
};
-#define num_registers(list) (sizeof (list) / sizeof((list)[0]))
+#define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
+static int
+num_registers (const struct reg *reg_list, int num_tot_regs)
+{
+ int i;
+ int nregs = 0;
+
+ for (i = 0; i < num_tot_regs; i++)
+ if (!reg_list[i].pseudo)
+ nregs++;
+
+ return nregs;
+}
+
+static int
+num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
+{
+ int i;
+ int npregs = 0;
+
+ for (i = 0; i < num_tot_regs; i++)
+ if (reg_list[i].pseudo)
+ npregs ++;
+
+ return npregs;
+}
/* Information in this table comes from the following web sites:
IBM: http://www.chips.ibm.com:80/products/embedded/
If you add entries to this table, please be sure to allow the new
value as an argument to the --with-cpu flag, in configure.in. */
-static const struct variant variants[] =
+static struct variant variants[] =
{
+
{"powerpc", "PowerPC user-level", bfd_arch_powerpc,
- bfd_mach_ppc, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
{"power", "POWER user-level", bfd_arch_rs6000,
- bfd_mach_rs6k, num_registers (registers_power), registers_power},
+ bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
+ registers_power},
{"403", "IBM PowerPC 403", bfd_arch_powerpc,
- bfd_mach_ppc_403, num_registers (registers_403), registers_403},
+ bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
+ registers_403},
{"601", "Motorola PowerPC 601", bfd_arch_powerpc,
- bfd_mach_ppc_601, num_registers (registers_601), registers_601},
+ bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
+ registers_601},
{"602", "Motorola PowerPC 602", bfd_arch_powerpc,
- bfd_mach_ppc_602, num_registers (registers_602), registers_602},
+ bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
+ registers_602},
{"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
- bfd_mach_ppc_603, num_registers (registers_603), registers_603},
+ bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
+ registers_603},
{"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
- 604, num_registers (registers_604), registers_604},
+ 604, -1, -1, tot_num_registers (registers_604),
+ registers_604},
{"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
- bfd_mach_ppc_403gc, num_registers (registers_403GC), registers_403GC},
+ bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
+ registers_403GC},
{"505", "Motorola PowerPC 505", bfd_arch_powerpc,
- bfd_mach_ppc_505, num_registers (registers_505), registers_505},
+ bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
+ registers_505},
{"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
- bfd_mach_ppc_860, num_registers (registers_860), registers_860},
+ bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
+ registers_860},
{"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
- bfd_mach_ppc_750, num_registers (registers_750), registers_750},
-
- /* FIXME: I haven't checked the register sets of the following. */
+ bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
+ registers_750},
+ {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
+ bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
+ registers_7400},
+ {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
+ bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
+ registers_e500},
+
+ /* 64-bit */
+ {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
+ bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
{"620", "Motorola PowerPC 620", bfd_arch_powerpc,
- bfd_mach_ppc_620, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
+ {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
+ bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
{"a35", "PowerPC A35", bfd_arch_powerpc,
- bfd_mach_ppc_a35, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
+ {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
+ bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
+ {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
+ bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
+
+ /* FIXME: I haven't checked the register sets of the following. */
{"rs1", "IBM POWER RS1", bfd_arch_rs6000,
- bfd_mach_rs6k_rs1, num_registers (registers_power), registers_power},
+ bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
+ registers_power},
{"rsc", "IBM POWER RSC", bfd_arch_rs6000,
- bfd_mach_rs6k_rsc, num_registers (registers_power), registers_power},
+ bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
+ registers_power},
{"rs2", "IBM POWER RS2", bfd_arch_rs6000,
- bfd_mach_rs6k_rs2, num_registers (registers_power), registers_power},
+ bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
+ registers_power},
- {0, 0, 0, 0}
+ {0, 0, 0, 0, 0, 0, 0, 0}
};
-#undef num_registers
+/* Initialize the number of registers and pseudo registers in each variant. */
-/* Look up the variant named NAME in the `variants' table. Return a
- pointer to the struct variant, or null if we couldn't find it. */
-
-static const struct variant *
-find_variant_by_name (char *name)
+static void
+init_variants (void)
{
- const struct variant *v;
+ struct variant *v;
for (v = variants; v->name; v++)
- if (!strcmp (name, v->name))
- return v;
-
- return NULL;
+ {
+ if (v->nregs == -1)
+ v->nregs = num_registers (v->regs, v->num_tot_regs);
+ if (v->npregs == -1)
+ v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
+ }
}
/* Return the variant corresponding to architecture ARCH and machine number
- MACH. If no such variant exists, return null. */
+ MACH. If no such variant exists, return null. */
static const struct variant *
find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
return NULL;
}
-
-
-\f
-static void
-process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj)
-{
- int *os_ident_ptr = obj;
- const char *name;
- unsigned int sectsize;
-
- name = bfd_get_section_name (abfd, sect);
- sectsize = bfd_section_size (abfd, sect);
- if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0)
- {
- unsigned int name_length, data_length, note_type;
- char *note = alloca (sectsize);
-
- bfd_get_section_contents (abfd, sect, note,
- (file_ptr) 0, (bfd_size_type) sectsize);
-
- name_length = bfd_h_get_32 (abfd, note);
- data_length = bfd_h_get_32 (abfd, note + 4);
- note_type = bfd_h_get_32 (abfd, note + 8);
-
- if (name_length == 4 && data_length == 16 && note_type == 1
- && strcmp (note + 12, "GNU") == 0)
- {
- int os_number = bfd_h_get_32 (abfd, note + 16);
-
- /* The case numbers are from abi-tags in glibc */
- switch (os_number)
- {
- case 0 :
- *os_ident_ptr = ELFOSABI_LINUX;
- break;
- case 1 :
- *os_ident_ptr = ELFOSABI_HURD;
- break;
- case 2 :
- *os_ident_ptr = ELFOSABI_SOLARIS;
- break;
- default :
- internal_error (
- "process_note_abi_sections: unknown OS number %d", os_number);
- break;
- }
- }
- }
-}
-
-/* Return one of the ELFOSABI_ constants for BFDs representing ELF
- executables. If it's not an ELF executable or if the OS/ABI couldn't
- be determined, simply return -1. */
-
static int
-get_elfosabi (bfd *abfd)
+gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
{
- int elfosabi = -1;
-
- if (abfd != NULL && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
- {
- elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
-
- /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate
- that we're on a SYSV system. However, GNU/Linux uses a note section
- to record OS/ABI info, but leaves e_ident[EI_OSABI] zero. So we
- have to check the note sections too. */
- if (elfosabi == 0)
- {
- bfd_map_over_sections (abfd,
- process_note_abi_tag_sections,
- &elfosabi);
- }
- }
-
- return elfosabi;
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ return print_insn_big_powerpc (memaddr, info);
+ else
+ return print_insn_little_powerpc (memaddr, info);
}
-
\f
-
/* Initialize the current architecture based on INFO. If possible, re-use an
architecture from ARCHES, which is a list of architectures already created
during this debugging session.
Called e.g. at program startup, when reading a core file, and when reading
- a binary file. */
+ a binary file. */
static struct gdbarch *
rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
enum bfd_architecture arch;
unsigned long mach;
bfd abfd;
- int osabi, sysv_abi;
+ int sysv_abi;
+ enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
+ asection *sect;
from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
- osabi = get_elfosabi (info.abfd);
+ if (info.abfd)
+ osabi = gdbarch_lookup_osabi (info.abfd);
- /* Check word size. If INFO is from a binary file, infer it from that,
- else use the previously-inferred size. */
+ /* Check word size. If INFO is from a binary file, infer it from
+ that, else choose a likely default. */
if (from_xcoff_exec)
{
- if (xcoff_data (info.abfd)->xcoff64)
+ if (bfd_xcoff_is_xcoff64 (info.abfd))
wordsize = 8;
else
wordsize = 4;
}
else
{
- tdep = TDEP;
- if (tdep)
- wordsize = tdep->wordsize;
+ if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
+ wordsize = info.bfd_arch_info->bits_per_word /
+ info.bfd_arch_info->bits_per_byte;
else
wordsize = 4;
}
- /* Find a candidate among extant architectures. */
+ /* Find a candidate among extant architectures. */
for (arches = gdbarch_list_lookup_by_info (arches, &info);
arches != NULL;
arches = gdbarch_list_lookup_by_info (arches->next, &info))
{
/* Word size in the various PowerPC bfd_arch_info structs isn't
meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
- separate word size check. */
+ separate word size check. */
tdep = gdbarch_tdep (arches->gdbarch);
if (tdep && tdep->wordsize == wordsize && tdep->osabi == osabi)
return arches->gdbarch;
if (!from_xcoff_exec)
{
- arch = info.bfd_architecture;
+ arch = info.bfd_arch_info->arch;
mach = info.bfd_arch_info->mach;
}
else
tdep = xmalloc (sizeof (struct gdbarch_tdep));
tdep->wordsize = wordsize;
tdep->osabi = osabi;
+
+ /* For e500 executables, the apuinfo section is of help here. Such
+ section contains the identifier and revision number of each
+ Application-specific Processing Unit that is present on the
+ chip. The content of the section is determined by the assembler
+ which looks at each instruction and determines which unit (and
+ which version of it) can execute it. In our case we just look for
+ the existance of the section. */
+
+ if (info.abfd)
+ {
+ sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
+ if (sect)
+ {
+ arch = info.bfd_arch_info->arch;
+ mach = bfd_mach_ppc_e500;
+ bfd_default_set_arch_mach (&abfd, arch, mach);
+ info.bfd_arch_info = bfd_get_arch_info (&abfd);
+ }
+ }
+
gdbarch = gdbarch_alloc (&info, tdep);
power = arch == bfd_arch_rs6000;
- /* Select instruction printer. */
- tm_print_insn = arch == power ? print_insn_rs6000 :
- info.byte_order == BIG_ENDIAN ? print_insn_big_powerpc :
- print_insn_little_powerpc;
+ /* Initialize the number of real and pseudo registers in each variant. */
+ init_variants ();
- /* Choose variant. */
+ /* Choose variant. */
v = find_variant_by_arch (arch, mach);
if (!v)
- v = find_variant_by_name (power ? "power" : "powerpc");
+ return NULL;
+
tdep->regs = v->regs;
- /* Calculate byte offsets in raw register array. */
- tdep->regoff = xmalloc (v->nregs * sizeof (int));
- for (i = off = 0; i < v->nregs; i++)
+ tdep->ppc_gp0_regnum = 0;
+ tdep->ppc_gplast_regnum = 31;
+ tdep->ppc_toc_regnum = 2;
+ tdep->ppc_ps_regnum = 65;
+ tdep->ppc_cr_regnum = 66;
+ tdep->ppc_lr_regnum = 67;
+ tdep->ppc_ctr_regnum = 68;
+ tdep->ppc_xer_regnum = 69;
+ if (v->mach == bfd_mach_ppc_601)
+ tdep->ppc_mq_regnum = 124;
+ else if (power)
+ tdep->ppc_mq_regnum = 70;
+ else
+ tdep->ppc_mq_regnum = -1;
+ tdep->ppc_fpscr_regnum = power ? 71 : 70;
+
+ set_gdbarch_pc_regnum (gdbarch, 64);
+ set_gdbarch_sp_regnum (gdbarch, 1);
+ set_gdbarch_fp_regnum (gdbarch, 1);
+ set_gdbarch_deprecated_extract_return_value (gdbarch,
+ rs6000_extract_return_value);
+ set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value);
+
+ if (v->arch == bfd_arch_powerpc)
+ switch (v->mach)
+ {
+ case bfd_mach_ppc:
+ tdep->ppc_vr0_regnum = 71;
+ tdep->ppc_vrsave_regnum = 104;
+ tdep->ppc_ev0_regnum = -1;
+ tdep->ppc_ev31_regnum = -1;
+ break;
+ case bfd_mach_ppc_7400:
+ tdep->ppc_vr0_regnum = 119;
+ tdep->ppc_vrsave_regnum = 152;
+ tdep->ppc_ev0_regnum = -1;
+ tdep->ppc_ev31_regnum = -1;
+ break;
+ case bfd_mach_ppc_e500:
+ tdep->ppc_gp0_regnum = 39;
+ tdep->ppc_gplast_regnum = 70;
+ tdep->ppc_toc_regnum = -1;
+ tdep->ppc_ps_regnum = 1;
+ tdep->ppc_cr_regnum = 2;
+ tdep->ppc_lr_regnum = 3;
+ tdep->ppc_ctr_regnum = 4;
+ tdep->ppc_xer_regnum = 5;
+ tdep->ppc_ev0_regnum = 7;
+ tdep->ppc_ev31_regnum = 38;
+ set_gdbarch_pc_regnum (gdbarch, 0);
+ set_gdbarch_sp_regnum (gdbarch, 40);
+ set_gdbarch_fp_regnum (gdbarch, 40);
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, e500_dwarf2_reg_to_regnum);
+ set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
+ set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
+ set_gdbarch_extract_return_value (gdbarch, e500_extract_return_value);
+ set_gdbarch_deprecated_store_return_value (gdbarch, e500_store_return_value);
+ break;
+ default:
+ tdep->ppc_vr0_regnum = -1;
+ tdep->ppc_vrsave_regnum = -1;
+ tdep->ppc_ev0_regnum = -1;
+ tdep->ppc_ev31_regnum = -1;
+ break;
+ }
+
+ /* Set lr_frame_offset. */
+ if (wordsize == 8)
+ tdep->lr_frame_offset = 16;
+ else if (sysv_abi)
+ tdep->lr_frame_offset = 4;
+ else
+ tdep->lr_frame_offset = 8;
+
+ /* Calculate byte offsets in raw register array. */
+ tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int));
+ for (i = off = 0; i < v->num_tot_regs; i++)
{
tdep->regoff[i] = off;
off += regsize (v->regs + i, wordsize);
}
+ /* Select instruction printer. */
+ if (arch == power)
+ set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
+ else
+ set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
+
set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
- set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
set_gdbarch_num_regs (gdbarch, v->nregs);
- set_gdbarch_sp_regnum (gdbarch, 1);
- set_gdbarch_fp_regnum (gdbarch, 1);
- set_gdbarch_pc_regnum (gdbarch, 64);
+ set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
set_gdbarch_register_name (gdbarch, rs6000_register_name);
set_gdbarch_register_size (gdbarch, wordsize);
set_gdbarch_register_bytes (gdbarch, off);
set_gdbarch_register_byte (gdbarch, rs6000_register_byte);
set_gdbarch_register_raw_size (gdbarch, rs6000_register_raw_size);
- set_gdbarch_max_register_raw_size (gdbarch, 8);
- set_gdbarch_register_virtual_size (gdbarch, rs6000_register_virtual_size);
- set_gdbarch_max_register_virtual_size (gdbarch, 8);
+ set_gdbarch_max_register_raw_size (gdbarch, 16);
+ set_gdbarch_register_virtual_size (gdbarch, generic_register_size);
+ set_gdbarch_max_register_virtual_size (gdbarch, 16);
set_gdbarch_register_virtual_type (gdbarch, rs6000_register_virtual_type);
set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+ set_gdbarch_char_signed (gdbarch, 0);
set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
set_gdbarch_call_dummy_length (gdbarch, 0);
set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
set_gdbarch_call_dummy_p (gdbarch, 1);
set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
- set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
set_gdbarch_fix_call_dummy (gdbarch, rs6000_fix_call_dummy);
+ set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
set_gdbarch_push_return_address (gdbarch, ppc_push_return_address);
set_gdbarch_register_convertible (gdbarch, rs6000_register_convertible);
set_gdbarch_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual);
set_gdbarch_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw);
-
- set_gdbarch_extract_return_value (gdbarch, rs6000_extract_return_value);
-
- if (sysv_abi)
+ set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
+ /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
+ is correct for the SysV ABI when the wordsize is 8, but I'm also
+ fairly certain that ppc_sysv_abi_push_arguments() will give even
+ worse results since it only works for 32-bit code. So, for the moment,
+ we're better off calling rs6000_push_arguments() since it works for
+ 64-bit code. At some point in the future, this matter needs to be
+ revisited. */
+ if (sysv_abi && wordsize == 4)
set_gdbarch_push_arguments (gdbarch, ppc_sysv_abi_push_arguments);
else
set_gdbarch_push_arguments (gdbarch, rs6000_push_arguments);
set_gdbarch_store_struct_return (gdbarch, rs6000_store_struct_return);
- set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
set_gdbarch_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
- set_gdbarch_use_struct_convention (gdbarch, generic_use_struct_convention);
-
set_gdbarch_pop_frame (gdbarch, rs6000_pop_frame);
set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
/* Not sure on this. FIXMEmgo */
set_gdbarch_frame_args_skip (gdbarch, 8);
- set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
- if (osabi == ELFOSABI_LINUX)
- {
- set_gdbarch_frameless_function_invocation (gdbarch,
- ppc_linux_frameless_function_invocation);
- set_gdbarch_frame_chain (gdbarch, ppc_linux_frame_chain);
- set_gdbarch_frame_saved_pc (gdbarch, ppc_linux_frame_saved_pc);
-
- set_gdbarch_frame_init_saved_regs (gdbarch,
- ppc_linux_frame_init_saved_regs);
- set_gdbarch_init_extra_frame_info (gdbarch,
- ppc_linux_init_extra_frame_info);
-
- set_gdbarch_memory_remove_breakpoint (gdbarch,
- ppc_linux_memory_remove_breakpoint);
- }
+ if (sysv_abi)
+ set_gdbarch_use_struct_convention (gdbarch,
+ ppc_sysv_abi_use_struct_convention);
else
- {
- set_gdbarch_frameless_function_invocation (gdbarch,
- rs6000_frameless_function_invocation);
- set_gdbarch_frame_chain (gdbarch, rs6000_frame_chain);
- set_gdbarch_frame_saved_pc (gdbarch, rs6000_frame_saved_pc);
+ set_gdbarch_use_struct_convention (gdbarch,
+ generic_use_struct_convention);
+
+ set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
+
+ set_gdbarch_frameless_function_invocation (gdbarch,
+ rs6000_frameless_function_invocation);
+ set_gdbarch_frame_chain (gdbarch, rs6000_frame_chain);
+ set_gdbarch_frame_saved_pc (gdbarch, rs6000_frame_saved_pc);
- set_gdbarch_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs);
- set_gdbarch_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info);
+ set_gdbarch_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs);
+ set_gdbarch_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info);
- /* Handle RS/6000 function pointers. */
+ if (!sysv_abi)
+ {
+ /* Handle RS/6000 function pointers (which are really function
+ descriptors). */
set_gdbarch_convert_from_func_ptr_addr (gdbarch,
rs6000_convert_from_func_ptr_addr);
}
now that the C compiler delays popping them. */
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
+ /* Hook in ABI-specific overrides, if they have been registered. */
+ gdbarch_init_osabi (info, gdbarch, osabi);
+
return gdbarch;
}
+static void
+rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (tdep == NULL)
+ return;
+
+ fprintf_unfiltered (file, "rs6000_dump_tdep: OS ABI = %s\n",
+ gdbarch_osabi_name (tdep->osabi));
+}
+
+static struct cmd_list_element *info_powerpc_cmdlist = NULL;
+
+static void
+rs6000_info_powerpc_command (char *args, int from_tty)
+{
+ help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
+}
+
/* Initialization code. */
void
_initialize_rs6000_tdep (void)
{
- register_gdbarch_init (bfd_arch_rs6000, rs6000_gdbarch_init);
- register_gdbarch_init (bfd_arch_powerpc, rs6000_gdbarch_init);
+ gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
+ gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
+
+ /* Add root prefix command for "info powerpc" commands */
+ add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
+ "Various POWERPC info specific commands.",
+ &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);
}
projects / deliverable / binutils-gdb.git / blobdiff