/* Target-dependent code for GDB, the GNU debugger.
- Copyright (C) 1986-2016 Free Software Foundation, Inc.
+ Copyright (C) 1986-2017 Free Software Foundation, Inc.
This file is part of GDB.
&& (regnum) >= (tdep)->ppc_efpr0_regnum \
&& (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
+/* Holds the current set of options to be passed to the disassembler. */
+static char *powerpc_disassembler_options;
+
/* The list of available "set powerpc ..." and "show powerpc ..."
commands. */
static struct cmd_list_element *setpowerpccmdlist = NULL;
/* Instruction masks used during single-stepping of atomic
sequences. */
-#define LWARX_MASK 0xfc0007fe
+#define LOAD_AND_RESERVE_MASK 0xfc0007fe
#define LWARX_INSTRUCTION 0x7c000028
#define LDARX_INSTRUCTION 0x7c0000A8
-#define STWCX_MASK 0xfc0007ff
+#define LBARX_INSTRUCTION 0x7c000068
+#define LHARX_INSTRUCTION 0x7c0000e8
+#define LQARX_INSTRUCTION 0x7c000228
+#define STORE_CONDITIONAL_MASK 0xfc0007ff
#define STWCX_INSTRUCTION 0x7c00012d
#define STDCX_INSTRUCTION 0x7c0001ad
+#define STBCX_INSTRUCTION 0x7c00056d
+#define STHCX_INSTRUCTION 0x7c0005ad
+#define STQCX_INSTRUCTION 0x7c00016d
+
+/* Check if insn is one of the Load And Reserve instructions used for atomic
+ sequences. */
+#define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
+ || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
+ || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
+ || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
+ || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
+/* Check if insn is one of the Store Conditional instructions used for atomic
+ sequences. */
+#define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
+ || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
+ || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
+ || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
+ || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
/* We can't displaced step atomic sequences. Otherwise this is just
like simple_displaced_step_copy_insn. */
insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order);
- /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
- if ((insn & LWARX_MASK) == LWARX_INSTRUCTION
- || (insn & LWARX_MASK) == LDARX_INSTRUCTION)
+ /* Assume all atomic sequences start with a Load and Reserve instruction. */
+ if (IS_LOAD_AND_RESERVE_INSN (insn))
{
if (debug_displaced)
{
return 1;
}
-/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
- instruction and ending with a STWCX/STDCX instruction. If such a sequence
- is found, attempt to step through it. A breakpoint is placed at the end of
- the sequence. */
-
-VEC (CORE_ADDR) *
+/* Checks for an atomic sequence of instructions beginning with a
+ Load And Reserve instruction and ending with a Store Conditional
+ instruction. If such a sequence is found, attempt to step through it.
+ A breakpoint is placed at the end of the sequence. */
+std::vector<CORE_ADDR>
ppc_deal_with_atomic_sequence (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
int bc_insn_count = 0; /* Conditional branch instruction count. */
- VEC (CORE_ADDR) *next_pcs = NULL;
- /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
- if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
- && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
- return NULL;
+ /* Assume all atomic sequences start with a Load And Reserve instruction. */
+ if (!IS_LOAD_AND_RESERVE_INSN (insn))
+ return {};
/* Assume that no atomic sequence is longer than "atomic_sequence_length"
instructions. */
int absolute = insn & 2;
if (bc_insn_count >= 1)
- return 0; /* More than one conditional branch found, fallback
- to the standard single-step code. */
+ return {}; /* More than one conditional branch found, fallback
+ to the standard single-step code. */
if (absolute)
breaks[1] = immediate;
last_breakpoint++;
}
- if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
- || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
+ if (IS_STORE_CONDITIONAL_INSN (insn))
break;
}
- /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
- if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
- && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
- return NULL;
+ /* Assume that the atomic sequence ends with a Store Conditional
+ instruction. */
+ if (!IS_STORE_CONDITIONAL_INSN (insn))
+ return {};
closing_insn = loc;
loc += PPC_INSN_SIZE;
|| (breaks[1] >= pc && breaks[1] <= closing_insn)))
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}
int *optimizedp, int *unavailablep)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
- gdb_byte from[MAX_REGISTER_SIZE];
+ gdb_byte from[PPC_MAX_REGISTER_SIZE];
gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
const gdb_byte *from)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
- gdb_byte to[MAX_REGISTER_SIZE];
+ gdb_byte to[PPC_MAX_REGISTER_SIZE];
gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
struct variant
{
/* Name of this variant. */
- char *name;
+ const char *name;
/* English description of the variant. */
- char *description;
+ const char *description;
/* bfd_arch_info.arch corresponding to variant. */
enum bfd_architecture arch;
return NULL;
}
-static int
-gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
-{
- if (info->endian == BFD_ENDIAN_BIG)
- return print_insn_big_powerpc (memaddr, info);
- else
- return print_insn_little_powerpc (memaddr, info);
-}
\f
static CORE_ADDR
rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
- /* Select instruction printer. */
- if (arch == bfd_arch_rs6000)
- set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
- else
- set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
-
set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
if (have_spe)
set_gdbarch_displaced_step_hw_singlestep (gdbarch,
ppc_displaced_step_hw_singlestep);
set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
- set_gdbarch_displaced_step_free_closure (gdbarch,
- simple_displaced_step_free_closure);
set_gdbarch_displaced_step_location (gdbarch,
displaced_step_at_entry_point);
/* Hook in ABI-specific overrides, if they have been registered. */
info.target_desc = tdesc;
- info.tdep_info = tdesc_data;
+ info.tdesc_data = tdesc_data;
gdbarch_init_osabi (info, gdbarch);
switch (info.osabi)
{
case GDB_OSABI_LINUX:
- case GDB_OSABI_NETBSD_AOUT:
- case GDB_OSABI_NETBSD_ELF:
+ case GDB_OSABI_NETBSD:
case GDB_OSABI_UNKNOWN:
set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind);
else
register_ppc_ravenscar_ops (gdbarch);
+ set_gdbarch_disassembler_options (gdbarch, &powerpc_disassembler_options);
+ set_gdbarch_valid_disassembler_options (gdbarch,
+ disassembler_options_powerpc ());
+
return gdbarch;
}
projects / deliverable / binutils-gdb.git / blobdiff