/* Target-dependent code for GDB, the GNU debugger.
- Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
- 1998, 1999, 2000, 2001, 2002
- Free Software Foundation, Inc.
+
+ Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
+ 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software
+ Foundation, Inc.
This file is part of GDB.
#include "target.h"
#include "gdbcore.h"
#include "gdbcmd.h"
-#include "symfile.h"
#include "objfiles.h"
#include "arch-utils.h"
#include "regcache.h"
+#include "regset.h"
#include "doublest.h"
#include "value.h"
#include "parser-defs.h"
+#include "osabi.h"
+#include "infcall.h"
+#include "sim-regno.h"
+#include "gdb/sim-ppc.h"
+#include "reggroups.h"
#include "libbfd.h" /* for bfd_default_set_arch_mach */
#include "coff/internal.h" /* for libcoff.h */
#include "libcoff.h" /* for xcoff_data */
+#include "coff/xcoff.h"
+#include "libxcoff.h"
#include "elf-bfd.h"
#include "solib-svr4.h"
#include "ppc-tdep.h"
+#include "gdb_assert.h"
+#include "dis-asm.h"
+
+#include "trad-frame.h"
+#include "frame-unwind.h"
+#include "frame-base.h"
+
+#include "reggroups.h"
+
/* If the kernel has to deliver a signal, it pushes a sigcontext
structure on the stack and then calls the signal handler, passing
the address of the sigcontext in an argument register. Usually
int saved_gpr; /* smallest # of saved gpr */
int saved_fpr; /* smallest # of saved fpr */
int saved_vr; /* smallest # of saved vr */
+ int saved_ev; /* smallest # of saved ev */
int alloca_reg; /* alloca register number (frame ptr) */
char frameless; /* true if frameless functions. */
char nosavedpc; /* true if pc not saved. */
int gpr_offset; /* offset of saved gprs from prev sp */
int fpr_offset; /* offset of saved fprs from prev sp */
int vr_offset; /* offset of saved vrs from prev sp */
+ int ev_offset; /* offset of saved evs from prev sp */
int lr_offset; /* offset of saved lr */
int cr_offset; /* offset of saved cr */
int vrsave_offset; /* offset of saved vrsave register */
unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
unsigned char fpr; /* whether register is floating-point */
+ unsigned char pseudo; /* whether register is pseudo */
+ int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
+ This is an ISA SPR number, not a GDB
+ register number. */
};
-/* Return the current architecture's gdbarch_tdep structure. */
-
-#define TDEP gdbarch_tdep (current_gdbarch)
-
/* Breakpoint shadows for the single step instructions will be kept here. */
static struct sstep_breaks
- {
- /* Address, or 0 if this is not in use. */
- CORE_ADDR address;
- /* Shadow contents. */
- char data[4];
- }
+{
+ /* Address, or 0 if this is not in use. */
+ CORE_ADDR address;
+ /* Shadow contents. */
+ gdb_byte data[4];
+}
stepBreaks[2];
/* Hook for determining the TOC address when calling functions in the
CORE_ADDR safety);
static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
struct rs6000_framedata *);
-static void frame_get_saved_regs (struct frame_info * fi,
- struct rs6000_framedata * fdatap);
-static CORE_ADDR frame_initial_stack_address (struct frame_info *);
+
+/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
+int
+altivec_register_p (int regno)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
+ return 0;
+ else
+ return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
+}
+
+
+/* Return true if REGNO is an SPE register, false otherwise. */
+int
+spe_register_p (int regno)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ /* Is it a reference to EV0 -- EV31, and do we have those? */
+ if (tdep->ppc_ev0_regnum >= 0
+ && tdep->ppc_ev31_regnum >= 0
+ && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
+ return 1;
+
+ /* Is it a reference to one of the raw upper GPR halves? */
+ if (tdep->ppc_ev0_upper_regnum >= 0
+ && tdep->ppc_ev0_upper_regnum <= regno
+ && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
+ return 1;
+
+ /* Is it a reference to the 64-bit accumulator, and do we have that? */
+ if (tdep->ppc_acc_regnum >= 0
+ && tdep->ppc_acc_regnum == regno)
+ return 1;
+
+ /* Is it a reference to the SPE floating-point status and control register,
+ and do we have that? */
+ if (tdep->ppc_spefscr_regnum >= 0
+ && tdep->ppc_spefscr_regnum == regno)
+ return 1;
+
+ return 0;
+}
+
+
+/* Return non-zero if the architecture described by GDBARCH has
+ floating-point registers (f0 --- f31 and fpscr). */
+int
+ppc_floating_point_unit_p (struct gdbarch *gdbarch)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ return (tdep->ppc_fp0_regnum >= 0
+ && tdep->ppc_fpscr_regnum >= 0);
+}
+
+
+/* Check that TABLE[GDB_REGNO] is not already initialized, and then
+ set it to SIM_REGNO.
+
+ This is a helper function for init_sim_regno_table, constructing
+ the table mapping GDB register numbers to sim register numbers; we
+ initialize every element in that table to -1 before we start
+ filling it in. */
+static void
+set_sim_regno (int *table, int gdb_regno, int sim_regno)
+{
+ /* Make sure we don't try to assign any given GDB register a sim
+ register number more than once. */
+ gdb_assert (table[gdb_regno] == -1);
+ table[gdb_regno] = sim_regno;
+}
+
+
+/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
+ numbers to simulator register numbers, based on the values placed
+ in the ARCH->tdep->ppc_foo_regnum members. */
+static void
+init_sim_regno_table (struct gdbarch *arch)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
+ int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
+ const struct reg *regs = tdep->regs;
+ int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
+ int i;
+
+ /* Presume that all registers not explicitly mentioned below are
+ unavailable from the sim. */
+ for (i = 0; i < total_regs; i++)
+ sim_regno[i] = -1;
+
+ /* General-purpose registers. */
+ for (i = 0; i < ppc_num_gprs; i++)
+ set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
+
+ /* Floating-point registers. */
+ if (tdep->ppc_fp0_regnum >= 0)
+ for (i = 0; i < ppc_num_fprs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_fp0_regnum + i,
+ sim_ppc_f0_regnum + i);
+ if (tdep->ppc_fpscr_regnum >= 0)
+ set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
+
+ set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
+ set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
+ set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
+
+ /* Segment registers. */
+ if (tdep->ppc_sr0_regnum >= 0)
+ for (i = 0; i < ppc_num_srs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_sr0_regnum + i,
+ sim_ppc_sr0_regnum + i);
+
+ /* Altivec registers. */
+ if (tdep->ppc_vr0_regnum >= 0)
+ {
+ for (i = 0; i < ppc_num_vrs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_vr0_regnum + i,
+ sim_ppc_vr0_regnum + i);
+
+ /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
+ we can treat this more like the other cases. */
+ set_sim_regno (sim_regno,
+ tdep->ppc_vr0_regnum + ppc_num_vrs,
+ sim_ppc_vscr_regnum);
+ }
+ /* vsave is a special-purpose register, so the code below handles it. */
+
+ /* SPE APU (E500) registers. */
+ if (tdep->ppc_ev0_regnum >= 0)
+ for (i = 0; i < ppc_num_gprs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_ev0_regnum + i,
+ sim_ppc_ev0_regnum + i);
+ if (tdep->ppc_ev0_upper_regnum >= 0)
+ for (i = 0; i < ppc_num_gprs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_ev0_upper_regnum + i,
+ sim_ppc_rh0_regnum + i);
+ if (tdep->ppc_acc_regnum >= 0)
+ set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
+ /* spefscr is a special-purpose register, so the code below handles it. */
+
+ /* Now handle all special-purpose registers. Verify that they
+ haven't mistakenly been assigned numbers by any of the above
+ code). */
+ for (i = 0; i < total_regs; i++)
+ if (regs[i].spr_num >= 0)
+ set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
+
+ /* Drop the initialized array into place. */
+ tdep->sim_regno = sim_regno;
+}
+
+
+/* Given a GDB register number REG, return the corresponding SIM
+ register number. */
+static int
+rs6000_register_sim_regno (int reg)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ int sim_regno;
+
+ gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
+ sim_regno = tdep->sim_regno[reg];
+
+ if (sim_regno >= 0)
+ return sim_regno;
+ else
+ return LEGACY_SIM_REGNO_IGNORE;
+}
+
+\f
+
+/* Register set support functions. */
+
+static void
+ppc_supply_reg (struct regcache *regcache, int regnum,
+ const gdb_byte *regs, size_t offset)
+{
+ if (regnum != -1 && offset != -1)
+ regcache_raw_supply (regcache, regnum, regs + offset);
+}
+
+static void
+ppc_collect_reg (const struct regcache *regcache, int regnum,
+ gdb_byte *regs, size_t offset)
+{
+ if (regnum != -1 && offset != -1)
+ regcache_raw_collect (regcache, regnum, regs + offset);
+}
+
+/* Supply register REGNUM in the general-purpose register set REGSET
+ from the buffer specified by GREGS and LEN to register cache
+ REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
+
+void
+ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *gregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
+ i < tdep->ppc_gp0_regnum + ppc_num_gprs;
+ i++, offset += 4)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_supply_reg (regcache, i, gregs, offset);
+ }
+
+ if (regnum == -1 || regnum == PC_REGNUM)
+ ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
+ gregs, offsets->ps_offset);
+ if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
+ gregs, offsets->cr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
+ gregs, offsets->lr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
+ gregs, offsets->ctr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
+ gregs, offsets->cr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
+}
+
+/* Supply register REGNUM in the floating-point register set REGSET
+ from the buffer specified by FPREGS and LEN to register cache
+ REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
+
+void
+ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *fpregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+ offset = offsets->f0_offset;
+ for (i = tdep->ppc_fp0_regnum;
+ i < tdep->ppc_fp0_regnum + ppc_num_fprs;
+ i++, offset += 8)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_supply_reg (regcache, i, fpregs, offset);
+ }
+
+ if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
+ fpregs, offsets->fpscr_offset);
+}
+
+/* Collect register REGNUM in the general-purpose register set
+ REGSET. from register cache REGCACHE into the buffer specified by
+ GREGS and LEN. If REGNUM is -1, do this for all registers in
+ REGSET. */
+
+void
+ppc_collect_gregset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *gregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ offset = offsets->r0_offset;
+ for (i = tdep->ppc_gp0_regnum;
+ i < tdep->ppc_gp0_regnum + ppc_num_gprs;
+ i++, offset += 4)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_collect_reg (regcache, i, gregs, offset);
+ }
+
+ if (regnum == -1 || regnum == PC_REGNUM)
+ ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
+ gregs, offsets->ps_offset);
+ if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
+ gregs, offsets->cr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
+ gregs, offsets->lr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
+ gregs, offsets->ctr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
+ gregs, offsets->xer_offset);
+ if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
+ gregs, offsets->mq_offset);
+}
+
+/* Collect register REGNUM in the floating-point register set
+ REGSET. from register cache REGCACHE into the buffer specified by
+ FPREGS and LEN. If REGNUM is -1, do this for all registers in
+ REGSET. */
+
+void
+ppc_collect_fpregset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *fpregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+ offset = offsets->f0_offset;
+ for (i = tdep->ppc_fp0_regnum;
+ i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
+ i++, offset += 8)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_collect_reg (regcache, i, fpregs, offset);
+ }
+
+ if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
+ fpregs, offsets->fpscr_offset);
+}
+\f
/* Read a LEN-byte address from debugged memory address MEMADDR. */
CORE_ADDR initial_sp; /* initial stack pointer. */
};
-void
-rs6000_init_extra_frame_info (int fromleaf, struct frame_info *fi)
-{
- fi->extra_info = (struct frame_extra_info *)
- frame_obstack_alloc (sizeof (struct frame_extra_info));
- fi->extra_info->initial_sp = 0;
- if (fi->next != (CORE_ADDR) 0
- && fi->pc < TEXT_SEGMENT_BASE)
- /* We're in get_prev_frame */
- /* and this is a special signal frame. */
- /* (fi->pc will be some low address in the kernel, */
- /* to which the signal handler returns). */
- fi->signal_handler_caller = 1;
-}
-
-/* Put here the code to store, into a struct frame_saved_regs,
- the addresses of the saved registers of frame described by FRAME_INFO.
- This includes special registers such as pc and fp saved in special
- ways in the stack frame. sp is even more special:
- the address we return for it IS the sp for the next frame. */
-
-/* In this implementation for RS/6000, we do *not* save sp. I am
- not sure if it will be needed. The following function takes care of gpr's
- and fpr's only. */
-
-void
-rs6000_frame_init_saved_regs (struct frame_info *fi)
-{
- frame_get_saved_regs (fi, NULL);
-}
-
-static CORE_ADDR
-rs6000_frame_args_address (struct frame_info *fi)
-{
- if (fi->extra_info->initial_sp != 0)
- return fi->extra_info->initial_sp;
- else
- return frame_initial_stack_address (fi);
-}
-
-/* Immediately after a function call, return the saved pc.
- Can't go through the frames for this because on some machines
- the new frame is not set up until the new function executes
- some instructions. */
-
+/* Get the ith function argument for the current function. */
static CORE_ADDR
-rs6000_saved_pc_after_call (struct frame_info *fi)
+rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
+ struct type *type)
{
- return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
+ return get_frame_register_unsigned (frame, 3 + argi);
}
/* Calculate the destination of a branch/jump. Return -1 if not a branch. */
fi = get_current_frame ();
if (fi != NULL)
- dest = read_memory_addr (fi->frame + SIG_FRAME_PC_OFFSET,
- TDEP->wordsize);
+ dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
+ gdbarch_tdep (current_gdbarch)->wordsize);
}
}
/* Sequence of bytes for breakpoint instruction. */
-#define BIG_BREAKPOINT { 0x7d, 0x82, 0x10, 0x08 }
-#define LITTLE_BREAKPOINT { 0x08, 0x10, 0x82, 0x7d }
-
const static unsigned char *
rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
{
- static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
- static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
+ static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
+ static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
*bp_size = 4;
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
return big_breakpoint;
{
CORE_ADDR dummy;
int breakp_sz;
- const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
+ const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
int ii, insn;
CORE_ADDR loc;
CORE_ADDR breaks[2];
- saved_gpr is the number of the first saved gpr.
- saved_fpr is the number of the first saved fpr.
- saved_vr is the number of the first saved vr.
+ - saved_ev is the number of the first saved ev.
- alloca_reg is the number of the register used for alloca() handling.
Otherwise -1.
- gpr_offset is the offset of the first saved gpr from the previous frame.
- fpr_offset is the offset of the first saved fpr from the previous frame.
- vr_offset is the offset of the first saved vr from the previous frame.
+ - ev_offset is the offset of the first saved ev from the previous frame.
- lr_offset is the offset of the saved lr
- cr_offset is the offset of the saved cr
- vrsave_offset is the offset of the saved vrsave register
the line data in the symbol table. If successful, a better guess
on where the prologue ends is returned, otherwise the previous
value of lim_pc is returned. */
+
+/* FIXME: cagney/2004-02-14: This function and logic have largely been
+ superseded by skip_prologue_using_sal. */
+
static CORE_ADDR
refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
{
return lim_pc;
}
+/* Return nonzero if the given instruction OP can be part of the prologue
+ of a function and saves a parameter on the stack. FRAMEP should be
+ set if one of the previous instructions in the function has set the
+ Frame Pointer. */
+
+static int
+store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
+{
+ /* Move parameters from argument registers to temporary register. */
+ if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
+ {
+ /* Rx must be scratch register r0. */
+ const int rx_regno = (op >> 16) & 31;
+ /* Ry: Only r3 - r10 are used for parameter passing. */
+ const int ry_regno = GET_SRC_REG (op);
+
+ if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
+ {
+ *r0_contains_arg = 1;
+ return 1;
+ }
+ else
+ return 0;
+ }
+
+ /* Save a General Purpose Register on stack. */
+
+ if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
+ (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
+ {
+ /* Rx: Only r3 - r10 are used for parameter passing. */
+ const int rx_regno = GET_SRC_REG (op);
+
+ return (rx_regno >= 3 && rx_regno <= 10);
+ }
+
+ /* Save a General Purpose Register on stack via the Frame Pointer. */
+
+ if (framep &&
+ ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
+ (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
+ (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
+ {
+ /* Rx: Usually, only r3 - r10 are used for parameter passing.
+ However, the compiler sometimes uses r0 to hold an argument. */
+ const int rx_regno = GET_SRC_REG (op);
+
+ return ((rx_regno >= 3 && rx_regno <= 10)
+ || (rx_regno == 0 && *r0_contains_arg));
+ }
+
+ if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
+ {
+ /* Only f2 - f8 are used for parameter passing. */
+ const int src_regno = GET_SRC_REG (op);
+
+ return (src_regno >= 2 && src_regno <= 8);
+ }
+
+ if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
+ {
+ /* Only f2 - f8 are used for parameter passing. */
+ const int src_regno = GET_SRC_REG (op);
+
+ return (src_regno >= 2 && src_regno <= 8);
+ }
+
+ /* Not an insn that saves a parameter on stack. */
+ return 0;
+}
static CORE_ADDR
skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
CORE_ADDR orig_pc = pc;
CORE_ADDR last_prologue_pc = pc;
CORE_ADDR li_found_pc = 0;
- char buf[4];
+ gdb_byte buf[4];
unsigned long op;
long offset = 0;
long vr_saved_offset = 0;
int lr_reg = -1;
int cr_reg = -1;
int vr_reg = -1;
+ int ev_reg = -1;
+ long ev_offset = 0;
int vrsave_reg = -1;
int reg;
int framep = 0;
int minimal_toc_loaded = 0;
int prev_insn_was_prologue_insn = 1;
int num_skip_non_prologue_insns = 0;
-
+ int r0_contains_arg = 0;
+ const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
/* Attempt to find the end of the prologue when no limit is specified.
Note that refine_prologue_limit() has been written so that it may
be used to "refine" the limits of non-zero PC values too, but this
fdata->saved_gpr = -1;
fdata->saved_fpr = -1;
fdata->saved_vr = -1;
+ fdata->saved_ev = -1;
fdata->alloca_reg = -1;
fdata->frameless = 1;
fdata->nosavedpc = 1;
if ((op & 0xfc1fffff) == 0x7c0802a6)
{ /* mflr Rx */
- lr_reg = (op & 0x03e00000) | 0x90010000;
+ /* Since shared library / PIC code, which needs to get its
+ address at runtime, can appear to save more than one link
+ register vis:
+
+ *INDENT-OFF*
+ stwu r1,-304(r1)
+ mflr r3
+ bl 0xff570d0 (blrl)
+ stw r30,296(r1)
+ mflr r30
+ stw r31,300(r1)
+ stw r3,308(r1);
+ ...
+ *INDENT-ON*
+
+ remember just the first one, but skip over additional
+ ones. */
+ if (lr_reg < 0)
+ lr_reg = (op & 0x03e00000);
+ if (lr_reg == 0)
+ r0_contains_arg = 0;
continue;
-
}
else if ((op & 0xfc1fffff) == 0x7c000026)
{ /* mfcr Rx */
- cr_reg = (op & 0x03e00000) | 0x90010000;
+ cr_reg = (op & 0x03e00000);
+ if (cr_reg == 0)
+ r0_contains_arg = 0;
continue;
}
{
fdata->saved_gpr = reg;
if ((op & 0xfc1f0003) == 0xf8010000)
- op = (op >> 1) << 1;
+ op &= ~3UL;
fdata->gpr_offset = SIGNED_SHORT (op) + offset;
}
continue;
}
else if ((op & 0xffff0000) == 0x60000000)
{
- /* nop */
+ /* nop */
/* Allow nops in the prologue, but do not consider them to
be part of the prologue unless followed by other prologue
instructions. */
for >= 32k frames */
fdata->offset = (op & 0x0000ffff) << 16;
fdata->frameless = 0;
+ r0_contains_arg = 0;
continue;
}
lf of >= 32k frames */
fdata->offset |= (op & 0x0000ffff);
fdata->frameless = 0;
+ r0_contains_arg = 0;
continue;
}
- else if (lr_reg != -1 && (op & 0xffff0000) == lr_reg)
- { /* st Rx,NUM(r1)
- where Rx == lr */
- fdata->lr_offset = SIGNED_SHORT (op) + offset;
+ else if (lr_reg >= 0 &&
+ /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
+ (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
+ /* stw Rx, NUM(r1) */
+ ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
+ /* stwu Rx, NUM(r1) */
+ ((op & 0xffff0000) == (lr_reg | 0x94010000))))
+ { /* where Rx == lr */
+ fdata->lr_offset = offset;
fdata->nosavedpc = 0;
- lr_reg = 0;
+ /* Invalidate lr_reg, but don't set it to -1.
+ That would mean that it had never been set. */
+ lr_reg = -2;
+ if ((op & 0xfc000003) == 0xf8000000 || /* std */
+ (op & 0xfc000000) == 0x90000000) /* stw */
+ {
+ /* Does not update r1, so add displacement to lr_offset. */
+ fdata->lr_offset += SIGNED_SHORT (op);
+ }
continue;
}
- else if (cr_reg != -1 && (op & 0xffff0000) == cr_reg)
- { /* st Rx,NUM(r1)
- where Rx == cr */
- fdata->cr_offset = SIGNED_SHORT (op) + offset;
- cr_reg = 0;
+ else if (cr_reg >= 0 &&
+ /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
+ (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
+ /* stw Rx, NUM(r1) */
+ ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
+ /* stwu Rx, NUM(r1) */
+ ((op & 0xffff0000) == (cr_reg | 0x94010000))))
+ { /* where Rx == cr */
+ fdata->cr_offset = offset;
+ /* Invalidate cr_reg, but don't set it to -1.
+ That would mean that it had never been set. */
+ cr_reg = -2;
+ if ((op & 0xfc000003) == 0xf8000000 ||
+ (op & 0xfc000000) == 0x90000000)
+ {
+ /* Does not update r1, so add displacement to cr_offset. */
+ fdata->cr_offset += SIGNED_SHORT (op);
+ }
continue;
}
fdata->frameless = 0;
/* Don't skip over the subroutine call if it is not within
- the first three instructions of the prologue. */
+ the first three instructions of the prologue and either
+ we have no line table information or the line info tells
+ us that the subroutine call is not part of the line
+ associated with the prologue. */
if ((pc - orig_pc) > 8)
- break;
+ {
+ struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
+ struct symtab_and_line this_sal = find_pc_line (pc, 0);
+
+ if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
+ break;
+ }
op = read_memory_integer (pc + 4, 4);
this branch */
continue;
- /* update stack pointer */
}
- else if ((op & 0xffff0000) == 0x94210000 || /* stu r1,NUM(r1) */
- (op & 0xffff0003) == 0xf8210001) /* stdu r1,NUM(r1) */
- {
+ /* update stack pointer */
+ else if ((op & 0xfc1f0000) == 0x94010000)
+ { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
fdata->frameless = 0;
- if ((op & 0xffff0003) == 0xf8210001)
- op = (op >> 1) << 1;
fdata->offset = SIGNED_SHORT (op);
offset = fdata->offset;
continue;
-
}
- else if (op == 0x7c21016e)
- { /* stwux 1,1,0 */
+ else if ((op & 0xfc1f016a) == 0x7c01016e)
+ { /* stwux rX,r1,rY */
+ /* no way to figure out what r1 is going to be */
+ fdata->frameless = 0;
+ offset = fdata->offset;
+ continue;
+ }
+ else if ((op & 0xfc1f0003) == 0xf8010001)
+ { /* stdu rX,NUM(r1) */
+ fdata->frameless = 0;
+ fdata->offset = SIGNED_SHORT (op & ~3UL);
+ offset = fdata->offset;
+ continue;
+ }
+ else if ((op & 0xfc1f016a) == 0x7c01016a)
+ { /* stdux rX,r1,rY */
+ /* no way to figure out what r1 is going to be */
fdata->frameless = 0;
offset = fdata->offset;
continue;
-
- /* Load up minimal toc pointer */
}
- else if ((op >> 22) == 0x20f
+ /* Load up minimal toc pointer */
+ else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
+ (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
&& !minimal_toc_loaded)
- { /* l r31,... or l r30,... */
+ {
minimal_toc_loaded = 1;
continue;
else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
(((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
(((op >> 21) & 31) <= 10) &&
- (((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
+ ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
{
continue;
/* store parameters in stack */
}
- else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
- (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
- (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
- {
- continue;
-
- /* store parameters in stack via frame pointer */
- }
- else if (framep &&
- ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */
- (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */
- (op & 0xfc1f0000) == 0xfc1f0000))
- { /* frsp, fp?,NUM(r1) */
+ /* Move parameters from argument registers to temporary register. */
+ else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
+ {
continue;
/* Set up frame pointer */
{ /* mr r31, r1 */
fdata->frameless = 0;
framep = 1;
- fdata->alloca_reg = 31;
+ fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
continue;
/* Another way to set up the frame pointer. */
{ /* addi rX, r1, 0x0 */
fdata->frameless = 0;
framep = 1;
- fdata->alloca_reg = (op & ~0x38010000) >> 21;
+ fdata->alloca_reg = (tdep->ppc_gp0_regnum
+ + ((op & ~0x38010000) >> 21));
continue;
}
/* AltiVec related instructions. */
in a pair of insns to save the vector registers on the
stack. */
/* 001110 00000 00000 iiii iiii iiii iiii */
- else if ((op & 0xffff0000) == 0x38000000) /* li r0, SIMM */
+ /* 001110 01110 00000 iiii iiii iiii iiii */
+ else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
+ || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
{
+ if ((op & 0xffff0000) == 0x38000000)
+ r0_contains_arg = 0;
li_found_pc = pc;
vr_saved_offset = SIGNED_SHORT (op);
+
+ /* This insn by itself is not part of the prologue, unless
+ if part of the pair of insns mentioned above. So do not
+ record this insn as part of the prologue yet. */
+ prev_insn_was_prologue_insn = 0;
}
/* Store vector register S at (r31+r0) aligned to 16 bytes. */
/* 011111 sssss 11111 00000 00111001110 */
}
}
/* End AltiVec related instructions. */
+
+ /* Start BookE related instructions. */
+ /* Store gen register S at (r31+uimm).
+ Any register less than r13 is volatile, so we don't care. */
+ /* 000100 sssss 11111 iiiii 01100100001 */
+ else if (arch_info->mach == bfd_mach_ppc_e500
+ && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
+ {
+ if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
+ {
+ unsigned int imm;
+ ev_reg = GET_SRC_REG (op);
+ imm = (op >> 11) & 0x1f;
+ ev_offset = imm * 8;
+ /* If this is the first vector reg to be saved, or if
+ it has a lower number than others previously seen,
+ reupdate the frame info. */
+ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+ {
+ fdata->saved_ev = ev_reg;
+ fdata->ev_offset = ev_offset + offset;
+ }
+ }
+ continue;
+ }
+ /* Store gen register rS at (r1+rB). */
+ /* 000100 sssss 00001 bbbbb 01100100000 */
+ else if (arch_info->mach == bfd_mach_ppc_e500
+ && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
+ {
+ if (pc == (li_found_pc + 4))
+ {
+ ev_reg = GET_SRC_REG (op);
+ /* If this is the first vector reg to be saved, or if
+ it has a lower number than others previously seen,
+ reupdate the frame info. */
+ /* We know the contents of rB from the previous instruction. */
+ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+ {
+ fdata->saved_ev = ev_reg;
+ fdata->ev_offset = vr_saved_offset + offset;
+ }
+ vr_saved_offset = -1;
+ ev_reg = -1;
+ li_found_pc = 0;
+ }
+ continue;
+ }
+ /* Store gen register r31 at (rA+uimm). */
+ /* 000100 11111 aaaaa iiiii 01100100001 */
+ else if (arch_info->mach == bfd_mach_ppc_e500
+ && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
+ {
+ /* Wwe know that the source register is 31 already, but
+ it can't hurt to compute it. */
+ ev_reg = GET_SRC_REG (op);
+ ev_offset = ((op >> 11) & 0x1f) * 8;
+ /* If this is the first vector reg to be saved, or if
+ it has a lower number than others previously seen,
+ reupdate the frame info. */
+ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+ {
+ fdata->saved_ev = ev_reg;
+ fdata->ev_offset = ev_offset + offset;
+ }
+
+ continue;
+ }
+ /* Store gen register S at (r31+r0).
+ Store param on stack when offset from SP bigger than 4 bytes. */
+ /* 000100 sssss 11111 00000 01100100000 */
+ else if (arch_info->mach == bfd_mach_ppc_e500
+ && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
+ {
+ if (pc == (li_found_pc + 4))
+ {
+ if ((op & 0x03e00000) >= 0x01a00000)
+ {
+ ev_reg = GET_SRC_REG (op);
+ /* If this is the first vector reg to be saved, or if
+ it has a lower number than others previously seen,
+ reupdate the frame info. */
+ /* We know the contents of r0 from the previous
+ instruction. */
+ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+ {
+ fdata->saved_ev = ev_reg;
+ fdata->ev_offset = vr_saved_offset + offset;
+ }
+ ev_reg = -1;
+ }
+ vr_saved_offset = -1;
+ li_found_pc = 0;
+ continue;
+ }
+ }
+ /* End BookE related instructions. */
+
else
{
/* Not a recognized prologue instruction.
trampolines. */
break;
if ((op & 0xf4000000) == 0x40000000) /* bxx */
- /* Never skip branches. */
+ /* Never skip branches. */
break;
if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
/* If the first thing after skipping a prolog is a branch to a function,
this might be a call to an initializer in main(), introduced by gcc2.
- We'd like to skip over it as well. Fortunately, xlc does some extra
+ We'd like to skip over it as well. Fortunately, xlc does some extra
work before calling a function right after a prologue, thus we can
- single out such gcc2 behaviour. */
+ single out such gcc2 behaviour. */
if ((op & 0xfc000001) == 0x48000001)
if (op == 0x4def7b82)
{ /* cror 0xf, 0xf, 0xf (nop) */
- /* check and see if we are in main. If so, skip over this initializer
- function as well. */
+ /* Check and see if we are in main. If so, skip over this
+ initializer function as well. */
tmp = find_pc_misc_function (pc);
- if (tmp >= 0 && STREQ (misc_function_vector[tmp].name, main_name ()))
+ if (tmp >= 0
+ && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
return pc + 8;
}
}
*************************************************************************/
-/* Pop the innermost frame, go back to the caller. */
-
-static void
-rs6000_pop_frame (void)
+/* All the ABI's require 16 byte alignment. */
+static CORE_ADDR
+rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
{
- CORE_ADDR pc, lr, sp, prev_sp, addr; /* %pc, %lr, %sp */
- struct rs6000_framedata fdata;
- struct frame_info *frame = get_current_frame ();
- int ii, wordsize;
+ return (addr & -16);
+}
- pc = read_pc ();
- sp = FRAME_FP (frame);
+/* Pass the arguments in either registers, or in the stack. In RS/6000,
+ the first eight words of the argument list (that might be less than
+ eight parameters if some parameters occupy more than one word) are
+ passed in r3..r10 registers. float and double parameters are
+ passed in fpr's, in addition to that. Rest of the parameters if any
+ are passed in user stack. There might be cases in which half of the
+ parameter is copied into registers, the other half is pushed into
+ stack.
- if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
- {
- generic_pop_dummy_frame ();
- flush_cached_frames ();
- return;
- }
+ Stack must be aligned on 64-bit boundaries when synthesizing
+ function calls.
- /* Make sure that all registers are valid. */
- read_register_bytes (0, NULL, REGISTER_BYTES);
+ If the function is returning a structure, then the return address is passed
+ in r3, then the first 7 words of the parameters can be passed in registers,
+ starting from r4. */
- /* figure out previous %pc value. If the function is frameless, it is
- still in the link register, otherwise walk the frames and retrieve the
- saved %pc value in the previous frame. */
+static CORE_ADDR
+rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+ struct regcache *regcache, CORE_ADDR bp_addr,
+ int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ int ii;
+ int len = 0;
+ int argno; /* current argument number */
+ int argbytes; /* current argument byte */
+ gdb_byte tmp_buffer[50];
+ int f_argno = 0; /* current floating point argno */
+ int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
+ CORE_ADDR func_addr = find_function_addr (function, NULL);
- addr = get_pc_function_start (frame->pc);
- (void) skip_prologue (addr, frame->pc, &fdata);
+ struct value *arg = 0;
+ struct type *type;
- wordsize = TDEP->wordsize;
- if (fdata.frameless)
- prev_sp = sp;
- else
- prev_sp = read_memory_addr (sp, wordsize);
- if (fdata.lr_offset == 0)
- lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
- else
- lr = read_memory_addr (prev_sp + fdata.lr_offset, wordsize);
+ CORE_ADDR saved_sp;
- /* reset %pc value. */
- write_register (PC_REGNUM, lr);
+ /* The calling convention this function implements assumes the
+ processor has floating-point registers. We shouldn't be using it
+ on PPC variants that lack them. */
+ gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
- /* reset register values if any was saved earlier. */
+ /* The first eight words of ther arguments are passed in registers.
+ Copy them appropriately. */
+ ii = 0;
- if (fdata.saved_gpr != -1)
+ /* If the function is returning a `struct', then the first word
+ (which will be passed in r3) is used for struct return address.
+ In that case we should advance one word and start from r4
+ register to copy parameters. */
+ if (struct_return)
{
- addr = prev_sp + fdata.gpr_offset;
- for (ii = fdata.saved_gpr; ii <= 31; ++ii)
- {
- read_memory (addr, ®isters[REGISTER_BYTE (ii)], wordsize);
- addr += wordsize;
- }
+ regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
+ struct_addr);
+ ii++;
}
- if (fdata.saved_fpr != -1)
- {
- addr = prev_sp + fdata.fpr_offset;
- for (ii = fdata.saved_fpr; ii <= 31; ++ii)
- {
- read_memory (addr, ®isters[REGISTER_BYTE (ii + FP0_REGNUM)], 8);
- addr += 8;
- }
- }
-
- write_register (SP_REGNUM, prev_sp);
- target_store_registers (-1);
- flush_cached_frames ();
-}
-
-/* Fixup the call sequence of a dummy function, with the real function
- address. Its arguments will be passed by gdb. */
-
-static void
-rs6000_fix_call_dummy (char *dummyname, CORE_ADDR pc, CORE_ADDR fun,
- int nargs, struct value **args, struct type *type,
- int gcc_p)
-{
- int ii;
- CORE_ADDR target_addr;
-
- if (rs6000_find_toc_address_hook != NULL)
- {
- CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (fun);
- write_register (gdbarch_tdep (current_gdbarch)->ppc_toc_regnum,
- tocvalue);
- }
-}
-
-/* Pass the arguments in either registers, or in the stack. In RS/6000,
- the first eight words of the argument list (that might be less than
- eight parameters if some parameters occupy more than one word) are
- passed in r3..r10 registers. float and double parameters are
- passed in fpr's, in addition to that. Rest of the parameters if any
- are passed in user stack. There might be cases in which half of the
- parameter is copied into registers, the other half is pushed into
- stack.
-
- Stack must be aligned on 64-bit boundaries when synthesizing
- function calls.
-
- If the function is returning a structure, then the return address is passed
- in r3, then the first 7 words of the parameters can be passed in registers,
- starting from r4. */
-
-static CORE_ADDR
-rs6000_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
- int struct_return, CORE_ADDR struct_addr)
-{
- int ii;
- int len = 0;
- int argno; /* current argument number */
- int argbytes; /* current argument byte */
- char tmp_buffer[50];
- int f_argno = 0; /* current floating point argno */
- int wordsize = TDEP->wordsize;
-
- struct value *arg = 0;
- struct type *type;
-
- CORE_ADDR saved_sp;
-
- /* The first eight words of ther arguments are passed in registers. Copy
- them appropriately.
-
- If the function is returning a `struct', then the first word (which
- will be passed in r3) is used for struct return address. In that
- case we should advance one word and start from r4 register to copy
- parameters. */
-
- ii = struct_return ? 1 : 0;
-
/*
effectively indirect call... gcc does...
for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
{
- int reg_size = REGISTER_RAW_SIZE (ii + 3);
+ int reg_size = register_size (current_gdbarch, ii + 3);
arg = args[argno];
- type = check_typedef (VALUE_TYPE (arg));
+ type = check_typedef (value_type (arg));
len = TYPE_LENGTH (type);
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- /* floating point arguments are passed in fpr's, as well as gpr's.
+ /* Floating point arguments are passed in fpr's, as well as gpr's.
There are 13 fpr's reserved for passing parameters. At this point
- there is no way we would run out of them. */
+ there is no way we would run out of them. */
- if (len > 8)
- printf_unfiltered (
- "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
+ gdb_assert (len <= 8);
- memcpy (®isters[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
- VALUE_CONTENTS (arg),
- len);
+ regcache_cooked_write (regcache,
+ tdep->ppc_fp0_regnum + 1 + f_argno,
+ value_contents (arg));
++f_argno;
}
if (len > reg_size)
{
- /* Argument takes more than one register. */
+ /* Argument takes more than one register. */
while (argbytes < len)
{
- memset (®isters[REGISTER_BYTE (ii + 3)], 0, reg_size);
- memcpy (®isters[REGISTER_BYTE (ii + 3)],
- ((char *) VALUE_CONTENTS (arg)) + argbytes,
+ gdb_byte word[MAX_REGISTER_SIZE];
+ memset (word, 0, reg_size);
+ memcpy (word,
+ ((char *) value_contents (arg)) + argbytes,
(len - argbytes) > reg_size
? reg_size : len - argbytes);
+ regcache_cooked_write (regcache,
+ tdep->ppc_gp0_regnum + 3 + ii,
+ word);
++ii, argbytes += reg_size;
if (ii >= 8)
--ii;
}
else
- { /* Argument can fit in one register. No problem. */
+ {
+ /* Argument can fit in one register. No problem. */
int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
- memset (®isters[REGISTER_BYTE (ii + 3)], 0, reg_size);
- memcpy ((char *)®isters[REGISTER_BYTE (ii + 3)] + adj,
- VALUE_CONTENTS (arg), len);
+ gdb_byte word[MAX_REGISTER_SIZE];
+
+ memset (word, 0, reg_size);
+ memcpy (word, value_contents (arg), len);
+ regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
}
++argno;
}
saved_sp = read_sp ();
- /* location for 8 parameters are always reserved. */
+ /* Location for 8 parameters are always reserved. */
sp -= wordsize * 8;
- /* another six words for back chain, TOC register, link register, etc. */
+ /* Another six words for back chain, TOC register, link register, etc. */
sp -= wordsize * 6;
- /* stack pointer must be quadword aligned */
+ /* Stack pointer must be quadword aligned. */
sp &= -16;
- /* if there are more arguments, allocate space for them in
- the stack, then push them starting from the ninth one. */
+ /* If there are more arguments, allocate space for them in
+ the stack, then push them starting from the ninth one. */
if ((argno < nargs) || argbytes)
{
for (; jj < nargs; ++jj)
{
struct value *val = args[jj];
- space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
+ space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
}
- /* add location required for the rest of the parameters */
+ /* Add location required for the rest of the parameters. */
space = (space + 15) & -16;
sp -= space;
- /* This is another instance we need to be concerned about securing our
- stack space. If we write anything underneath %sp (r1), we might conflict
- with the kernel who thinks he is free to use this area. So, update %sp
- first before doing anything else. */
+ /* This is another instance we need to be concerned about
+ securing our stack space. If we write anything underneath %sp
+ (r1), we might conflict with the kernel who thinks he is free
+ to use this area. So, update %sp first before doing anything
+ else. */
- write_register (SP_REGNUM, sp);
+ regcache_raw_write_signed (regcache, SP_REGNUM, sp);
- /* if the last argument copied into the registers didn't fit there
- completely, push the rest of it into stack. */
+ /* If the last argument copied into the registers didn't fit there
+ completely, push the rest of it into stack. */
if (argbytes)
{
write_memory (sp + 24 + (ii * 4),
- ((char *) VALUE_CONTENTS (arg)) + argbytes,
+ value_contents (arg) + argbytes,
len - argbytes);
++argno;
ii += ((len - argbytes + 3) & -4) / 4;
}
- /* push the rest of the arguments into stack. */
+ /* Push the rest of the arguments into stack. */
for (; argno < nargs; ++argno)
{
arg = args[argno];
- type = check_typedef (VALUE_TYPE (arg));
+ type = check_typedef (value_type (arg));
len = TYPE_LENGTH (type);
- /* float types should be passed in fpr's, as well as in the stack. */
+ /* Float types should be passed in fpr's, as well as in the
+ stack. */
if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
{
- if (len > 8)
- printf_unfiltered (
- "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
+ gdb_assert (len <= 8);
- memcpy (®isters[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
- VALUE_CONTENTS (arg),
- len);
+ regcache_cooked_write (regcache,
+ tdep->ppc_fp0_regnum + 1 + f_argno,
+ value_contents (arg));
++f_argno;
}
- write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len);
+ write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
ii += ((len + 3) & -4) / 4;
}
}
- else
- /* Secure stack areas first, before doing anything else. */
- write_register (SP_REGNUM, sp);
- /* set back chain properly */
- store_address (tmp_buffer, 4, saved_sp);
+ /* Set the stack pointer. According to the ABI, the SP is meant to
+ be set _before_ the corresponding stack space is used. On AIX,
+ this even applies when the target has been completely stopped!
+ Not doing this can lead to conflicts with the kernel which thinks
+ that it still has control over this not-yet-allocated stack
+ region. */
+ regcache_raw_write_signed (regcache, SP_REGNUM, sp);
+
+ /* Set back chain properly. */
+ store_unsigned_integer (tmp_buffer, 4, saved_sp);
write_memory (sp, tmp_buffer, 4);
+ /* Point the inferior function call's return address at the dummy's
+ breakpoint. */
+ regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
+
+ /* Set the TOC register, get the value from the objfile reader
+ which, in turn, gets it from the VMAP table. */
+ if (rs6000_find_toc_address_hook != NULL)
+ {
+ CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
+ regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
+ }
+
target_store_registers (-1);
return sp;
}
-/* Function: ppc_push_return_address (pc, sp)
- Set up the return address for the inferior function call. */
+/* PowerOpen always puts structures in memory. Vectors, which were
+ added later, do get returned in a register though. */
-static CORE_ADDR
-ppc_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
-{
- write_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum,
- CALL_DUMMY_ADDRESS ());
- return sp;
+static int
+rs6000_use_struct_convention (int gcc_p, struct type *value_type)
+{
+ if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
+ && TYPE_VECTOR (value_type))
+ return 0;
+ return 1;
}
-/* Extract a function return value of type TYPE from raw register array
- REGBUF, and copy that return value into VALBUF in virtual format. */
-
static void
-rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
+rs6000_extract_return_value (struct type *valtype, gdb_byte *regbuf,
+ gdb_byte *valbuf)
{
int offset = 0;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ /* The calling convention this function implements assumes the
+ processor has floating-point registers. We shouldn't be using it
+ on PPC variants that lack them. */
+ gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
{
- double dd;
- float ff;
/* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
We need to truncate the return value into float size (4 byte) if
- necessary. */
+ necessary. */
- if (TYPE_LENGTH (valtype) > 4) /* this is a double */
- memcpy (valbuf,
- ®buf[REGISTER_BYTE (FP0_REGNUM + 1)],
- TYPE_LENGTH (valtype));
- else
- { /* float */
- memcpy (&dd, ®buf[REGISTER_BYTE (FP0_REGNUM + 1)], 8);
- ff = (float) dd;
- memcpy (valbuf, &ff, sizeof (float));
- }
+ convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
+ (tdep->ppc_fp0_regnum + 1)],
+ builtin_type_double,
+ valbuf,
+ valtype);
+ }
+ else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
+ && TYPE_LENGTH (valtype) == 16
+ && TYPE_VECTOR (valtype))
+ {
+ memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
+ TYPE_LENGTH (valtype));
}
else
{
/* return value is copied starting from r3. */
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
- && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (3))
- offset = REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype);
+ && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3))
+ offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype);
memcpy (valbuf,
- regbuf + REGISTER_BYTE (3) + offset,
+ regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
TYPE_LENGTH (valtype));
}
}
-/* Keep structure return address in this variable.
- FIXME: This is a horrid kludge which should not be allowed to continue
- living. This only allows a single nested call to a structure-returning
- function. Come on, guys! -- gnu@cygnus.com, Aug 92 */
-
-static CORE_ADDR rs6000_struct_return_address;
-
/* Return whether handle_inferior_event() should proceed through code
starting at PC in function NAME when stepping.
back to where execution should continue.
GDB should silently step over @FIX code, just like AIX dbx does.
- Unfortunately, the linker uses the "b" instruction for the branches,
- meaning that the link register doesn't get set. Therefore, GDB's usual
- step_over_function() mechanism won't work.
+ Unfortunately, the linker uses the "b" instruction for the
+ branches, meaning that the link register doesn't get set.
+ Therefore, GDB's usual step_over_function () mechanism won't work.
- Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
- in handle_inferior_event() to skip past @FIX code. */
+ Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
+ SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
+ @FIX code. */
int
rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
CORE_ADDR
rs6000_skip_trampoline_code (CORE_ADDR pc)
{
- register unsigned int ii, op;
+ unsigned int ii, op;
int rel;
CORE_ADDR solib_target_pc;
struct minimal_symbol *msymbol;
/* Check for bigtoc fixup code. */
msymbol = lookup_minimal_symbol_by_pc (pc);
- if (msymbol && rs6000_in_solib_return_trampoline (pc, SYMBOL_NAME (msymbol)))
+ if (msymbol
+ && rs6000_in_solib_return_trampoline (pc,
+ DEPRECATED_SYMBOL_NAME (msymbol)))
{
/* Double-check that the third instruction from PC is relative "b". */
op = read_memory_integer (pc + 8, 4);
return 0;
}
ii = read_register (11); /* r11 holds destination addr */
- pc = read_memory_addr (ii, TDEP->wordsize); /* (r11) value */
+ pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
return pc;
}
-/* Determines whether the function FI has a frame on the stack or not. */
-
-int
-rs6000_frameless_function_invocation (struct frame_info *fi)
-{
- CORE_ADDR func_start;
- struct rs6000_framedata fdata;
-
- /* Don't even think about framelessness except on the innermost frame
- or if the function was interrupted by a signal. */
- if (fi->next != NULL && !fi->next->signal_handler_caller)
- return 0;
-
- func_start = get_pc_function_start (fi->pc);
-
- /* If we failed to find the start of the function, it is a mistake
- to inspect the instructions. */
-
- if (!func_start)
- {
- /* A frame with a zero PC is usually created by dereferencing a NULL
- function pointer, normally causing an immediate core dump of the
- inferior. Mark function as frameless, as the inferior has no chance
- of setting up a stack frame. */
- if (fi->pc == 0)
- return 1;
- else
- return 0;
- }
-
- (void) skip_prologue (func_start, fi->pc, &fdata);
- return fdata.frameless;
-}
-
-/* Return the PC saved in a frame */
-
-CORE_ADDR
-rs6000_frame_saved_pc (struct frame_info *fi)
-{
- CORE_ADDR func_start;
- struct rs6000_framedata fdata;
- struct gdbarch_tdep *tdep = TDEP;
- int wordsize = tdep->wordsize;
-
- if (fi->signal_handler_caller)
- return read_memory_addr (fi->frame + SIG_FRAME_PC_OFFSET, wordsize);
-
- if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
- return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
-
- func_start = get_pc_function_start (fi->pc);
-
- /* If we failed to find the start of the function, it is a mistake
- to inspect the instructions. */
- if (!func_start)
- return 0;
-
- (void) skip_prologue (func_start, fi->pc, &fdata);
-
- if (fdata.lr_offset == 0 && fi->next != NULL)
- {
- if (fi->next->signal_handler_caller)
- return read_memory_addr (fi->next->frame + SIG_FRAME_LR_OFFSET,
- wordsize);
- else
- return read_memory_addr (FRAME_CHAIN (fi) + tdep->lr_frame_offset,
- wordsize);
- }
-
- if (fdata.lr_offset == 0)
- return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
-
- return read_memory_addr (FRAME_CHAIN (fi) + fdata.lr_offset, wordsize);
-}
-
-/* If saved registers of frame FI are not known yet, read and cache them.
- &FDATAP contains rs6000_framedata; TDATAP can be NULL,
- in which case the framedata are read. */
-
-static void
-frame_get_saved_regs (struct frame_info *fi, struct rs6000_framedata *fdatap)
-{
- CORE_ADDR frame_addr;
- struct rs6000_framedata work_fdata;
- struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch);
- int wordsize = tdep->wordsize;
-
- if (fi->saved_regs)
- return;
-
- if (fdatap == NULL)
- {
- fdatap = &work_fdata;
- (void) skip_prologue (get_pc_function_start (fi->pc), fi->pc, fdatap);
- }
-
- frame_saved_regs_zalloc (fi);
-
- /* If there were any saved registers, figure out parent's stack
- pointer. */
- /* The following is true only if the frame doesn't have a call to
- alloca(), FIXME. */
-
- if (fdatap->saved_fpr == 0
- && fdatap->saved_gpr == 0
- && fdatap->saved_vr == 0
- && fdatap->lr_offset == 0
- && fdatap->cr_offset == 0
- && fdatap->vr_offset == 0)
- frame_addr = 0;
- else if (fi->prev && fi->prev->frame)
- frame_addr = fi->prev->frame;
- else
- frame_addr = read_memory_addr (fi->frame, wordsize);
-
- /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr.
- All fpr's from saved_fpr to fp31 are saved. */
-
- if (fdatap->saved_fpr >= 0)
- {
- int i;
- CORE_ADDR fpr_addr = frame_addr + fdatap->fpr_offset;
- for (i = fdatap->saved_fpr; i < 32; i++)
- {
- fi->saved_regs[FP0_REGNUM + i] = fpr_addr;
- fpr_addr += 8;
- }
- }
-
- /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr.
- All gpr's from saved_gpr to gpr31 are saved. */
-
- if (fdatap->saved_gpr >= 0)
- {
- int i;
- CORE_ADDR gpr_addr = frame_addr + fdatap->gpr_offset;
- for (i = fdatap->saved_gpr; i < 32; i++)
- {
- fi->saved_regs[i] = gpr_addr;
- gpr_addr += wordsize;
- }
- }
-
- /* if != -1, fdatap->saved_vr is the smallest number of saved_vr.
- All vr's from saved_vr to vr31 are saved. */
- if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
- {
- if (fdatap->saved_vr >= 0)
- {
- int i;
- CORE_ADDR vr_addr = frame_addr + fdatap->vr_offset;
- for (i = fdatap->saved_vr; i < 32; i++)
- {
- fi->saved_regs[tdep->ppc_vr0_regnum + i] = vr_addr;
- vr_addr += REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
- }
- }
- }
-
- /* If != 0, fdatap->cr_offset is the offset from the frame that holds
- the CR. */
- if (fdatap->cr_offset != 0)
- fi->saved_regs[tdep->ppc_cr_regnum] = frame_addr + fdatap->cr_offset;
-
- /* If != 0, fdatap->lr_offset is the offset from the frame that holds
- the LR. */
- if (fdatap->lr_offset != 0)
- fi->saved_regs[tdep->ppc_lr_regnum] = frame_addr + fdatap->lr_offset;
-
- /* If != 0, fdatap->vrsave_offset is the offset from the frame that holds
- the VRSAVE. */
- if (fdatap->vrsave_offset != 0)
- fi->saved_regs[tdep->ppc_vrsave_regnum] = frame_addr + fdatap->vrsave_offset;
-}
-
-/* Return the address of a frame. This is the inital %sp value when the frame
- was first allocated. For functions calling alloca(), it might be saved in
- an alloca register. */
-
-static CORE_ADDR
-frame_initial_stack_address (struct frame_info *fi)
-{
- CORE_ADDR tmpaddr;
- struct rs6000_framedata fdata;
- struct frame_info *callee_fi;
-
- /* if the initial stack pointer (frame address) of this frame is known,
- just return it. */
-
- if (fi->extra_info->initial_sp)
- return fi->extra_info->initial_sp;
-
- /* find out if this function is using an alloca register.. */
-
- (void) skip_prologue (get_pc_function_start (fi->pc), fi->pc, &fdata);
-
- /* if saved registers of this frame are not known yet, read and cache them. */
-
- if (!fi->saved_regs)
- frame_get_saved_regs (fi, &fdata);
-
- /* If no alloca register used, then fi->frame is the value of the %sp for
- this frame, and it is good enough. */
-
- if (fdata.alloca_reg < 0)
- {
- fi->extra_info->initial_sp = fi->frame;
- return fi->extra_info->initial_sp;
- }
-
- /* There is an alloca register, use its value, in the current frame,
- as the initial stack pointer. */
- {
- char *tmpbuf = alloca (MAX_REGISTER_RAW_SIZE);
- if (frame_register_read (fi, fdata.alloca_reg, tmpbuf))
- {
- fi->extra_info->initial_sp
- = extract_unsigned_integer (tmpbuf,
- REGISTER_RAW_SIZE (fdata.alloca_reg));
- }
- else
- /* NOTE: cagney/2002-04-17: At present the only time
- frame_register_read will fail is when the register isn't
- available. If that does happen, use the frame. */
- fi->extra_info->initial_sp = fi->frame;
- }
- return fi->extra_info->initial_sp;
-}
-
-/* Describe the pointer in each stack frame to the previous stack frame
- (its caller). */
-
-/* FRAME_CHAIN takes a frame's nominal address
- and produces the frame's chain-pointer. */
-
-/* In the case of the RS/6000, the frame's nominal address
- is the address of a 4-byte word containing the calling frame's address. */
-
-CORE_ADDR
-rs6000_frame_chain (struct frame_info *thisframe)
-{
- CORE_ADDR fp, fpp, lr;
- int wordsize = TDEP->wordsize;
-
- if (PC_IN_CALL_DUMMY (thisframe->pc, thisframe->frame, thisframe->frame))
- return thisframe->frame; /* dummy frame same as caller's frame */
-
- if (inside_entry_file (thisframe->pc) ||
- thisframe->pc == entry_point_address ())
- return 0;
-
- if (thisframe->signal_handler_caller)
- fp = read_memory_addr (thisframe->frame + SIG_FRAME_FP_OFFSET,
- wordsize);
- else if (thisframe->next != NULL
- && thisframe->next->signal_handler_caller
- && FRAMELESS_FUNCTION_INVOCATION (thisframe))
- /* A frameless function interrupted by a signal did not change the
- frame pointer. */
- fp = FRAME_FP (thisframe);
- else
- fp = read_memory_addr ((thisframe)->frame, wordsize);
-
- lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
- if (lr == entry_point_address ())
- if (fp != 0 && (fpp = read_memory_addr (fp, wordsize)) != 0)
- if (PC_IN_CALL_DUMMY (lr, fpp, fpp))
- return fpp;
-
- return fp;
-}
-
/* Return the size of register REG when words are WORDSIZE bytes long. If REG
- isn't available with that word size, return 0. */
+ isn't available with that word size, return 0. */
static int
regsize (const struct reg *reg, int wordsize)
}
/* Return the name of register number N, or null if no such register exists
- in the current architecture. */
+ in the current architecture. */
-static char *
+static const char *
rs6000_register_name (int n)
{
- struct gdbarch_tdep *tdep = TDEP;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
const struct reg *reg = tdep->regs + n;
if (!regsize (reg, tdep->wordsize))
return reg->name;
}
-/* Index within `registers' of the first byte of the space for
- register N. */
-
-static int
-rs6000_register_byte (int n)
-{
- return TDEP->regoff[n];
-}
-
-/* Return the number of bytes of storage in the actual machine representation
- for register N if that register is available, else return 0. */
-
-static int
-rs6000_register_raw_size (int n)
-{
- struct gdbarch_tdep *tdep = TDEP;
- const struct reg *reg = tdep->regs + n;
- return regsize (reg, tdep->wordsize);
-}
-
/* Return the GDB type object for the "standard" data type
of data in register N. */
static struct type *
-rs6000_register_virtual_type (int n)
+rs6000_register_type (struct gdbarch *gdbarch, int n)
{
- struct gdbarch_tdep *tdep = TDEP;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
const struct reg *reg = tdep->regs + n;
if (reg->fpr)
int size = regsize (reg, tdep->wordsize);
switch (size)
{
+ case 0:
+ return builtin_type_int0;
+ case 4:
+ return builtin_type_uint32;
case 8:
- return builtin_type_int64;
+ if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
+ return builtin_type_vec64;
+ else
+ return builtin_type_uint64;
break;
case 16:
return builtin_type_vec128;
break;
default:
- return builtin_type_int32;
- break;
+ internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"),
+ n, size);
}
}
}
-/* For the PowerPC, it appears that the debug info marks float parameters as
- floats regardless of whether the function is prototyped, but the actual
- values are always passed in as doubles. Tell gdb to always assume that
- floats are passed as doubles and then converted in the callee. */
-
+/* Is REGNUM a member of REGGROUP? */
static int
-rs6000_coerce_float_to_double (struct type *formal, struct type *actual)
+rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
+ struct reggroup *group)
{
- return 1;
-}
-
-/* Return whether register N requires conversion when moving from raw format
- to virtual format.
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int float_p;
+ int vector_p;
+ int general_p;
- The register format for RS/6000 floating point registers is always
- double, we need a conversion if the memory format is float. */
-
-static int
-rs6000_register_convertible (int n)
-{
- const struct reg *reg = TDEP->regs + n;
- return reg->fpr;
+ if (REGISTER_NAME (regnum) == NULL
+ || *REGISTER_NAME (regnum) == '\0')
+ return 0;
+ if (group == all_reggroup)
+ return 1;
+
+ float_p = (regnum == tdep->ppc_fpscr_regnum
+ || (regnum >= tdep->ppc_fp0_regnum
+ && regnum < tdep->ppc_fp0_regnum + 32));
+ if (group == float_reggroup)
+ return float_p;
+
+ vector_p = ((tdep->ppc_vr0_regnum >= 0
+ && regnum >= tdep->ppc_vr0_regnum
+ && regnum < tdep->ppc_vr0_regnum + 32)
+ || (tdep->ppc_ev0_regnum >= 0
+ && regnum >= tdep->ppc_ev0_regnum
+ && regnum < tdep->ppc_ev0_regnum + 32)
+ || regnum == tdep->ppc_vrsave_regnum
+ || regnum == tdep->ppc_acc_regnum
+ || regnum == tdep->ppc_spefscr_regnum);
+ if (group == vector_reggroup)
+ return vector_p;
+
+ /* Note that PS aka MSR isn't included - it's a system register (and
+ besides, due to GCC's CFI foobar you do not want to restore
+ it). */
+ general_p = ((regnum >= tdep->ppc_gp0_regnum
+ && regnum < tdep->ppc_gp0_regnum + 32)
+ || regnum == tdep->ppc_toc_regnum
+ || regnum == tdep->ppc_cr_regnum
+ || regnum == tdep->ppc_lr_regnum
+ || regnum == tdep->ppc_ctr_regnum
+ || regnum == tdep->ppc_xer_regnum
+ || regnum == PC_REGNUM);
+ if (group == general_reggroup)
+ return general_p;
+
+ if (group == save_reggroup || group == restore_reggroup)
+ return general_p || vector_p || float_p;
+
+ return 0;
}
-/* Convert data from raw format for register N in buffer FROM
- to virtual format with type TYPE in buffer TO. */
+/* The register format for RS/6000 floating point registers is always
+ double, we need a conversion if the memory format is float. */
-static void
-rs6000_register_convert_to_virtual (int n, struct type *type,
- char *from, char *to)
+static int
+rs6000_convert_register_p (int regnum, struct type *type)
{
- if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n))
- {
- double val = extract_floating (from, REGISTER_RAW_SIZE (n));
- store_floating (to, TYPE_LENGTH (type), val);
- }
- else
- memcpy (to, from, REGISTER_RAW_SIZE (n));
+ const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
+
+ return (reg->fpr
+ && TYPE_CODE (type) == TYPE_CODE_FLT
+ && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
}
-/* Convert data from virtual format with type TYPE in buffer FROM
- to raw format for register N in buffer TO. */
-
static void
-rs6000_register_convert_to_raw (struct type *type, int n,
- char *from, char *to)
+rs6000_register_to_value (struct frame_info *frame,
+ int regnum,
+ struct type *type,
+ gdb_byte *to)
{
- if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n))
- {
- double val = extract_floating (from, TYPE_LENGTH (type));
- store_floating (to, REGISTER_RAW_SIZE (n), val);
- }
- else
- memcpy (to, from, REGISTER_RAW_SIZE (n));
-}
+ const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
+ gdb_byte from[MAX_REGISTER_SIZE];
+
+ gdb_assert (reg->fpr);
+ gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
-int
-altivec_register_p (int regno)
-{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
- if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
- return 0;
- else
- return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
+ get_frame_register (frame, regnum, from);
+ convert_typed_floating (from, builtin_type_double, to, type);
}
static void
-rs6000_do_altivec_registers (int regnum)
+rs6000_value_to_register (struct frame_info *frame,
+ int regnum,
+ struct type *type,
+ const gdb_byte *from)
{
- int i;
- char *raw_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
- char *virtual_buffer = (char*) alloca (MAX_REGISTER_VIRTUAL_SIZE);
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- for (i = tdep->ppc_vr0_regnum; i <= tdep->ppc_vrsave_regnum; i++)
- {
- /* If we want just one reg, check that this is the one we want. */
- if (regnum != -1 && i != regnum)
- continue;
+ const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
+ gdb_byte to[MAX_REGISTER_SIZE];
- /* If the register name is empty, it is undefined for this
- processor, so don't display anything. */
- if (REGISTER_NAME (i) == NULL || *(REGISTER_NAME (i)) == '\0')
- continue;
+ gdb_assert (reg->fpr);
+ gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
- fputs_filtered (REGISTER_NAME (i), gdb_stdout);
- print_spaces_filtered (15 - strlen (REGISTER_NAME (i)), gdb_stdout);
-
- /* Get the data in raw format. */
- if (!frame_register_read (selected_frame, i, raw_buffer))
- {
- printf_filtered ("*value not available*\n");
- continue;
- }
-
- /* Convert raw data to virtual format if necessary. */
- if (REGISTER_CONVERTIBLE (i))
- REGISTER_CONVERT_TO_VIRTUAL (i, REGISTER_VIRTUAL_TYPE (i),
- raw_buffer, virtual_buffer);
- else
- memcpy (virtual_buffer, raw_buffer, REGISTER_VIRTUAL_SIZE (i));
-
- /* Print as integer in hex only. */
- val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
- gdb_stdout, 'x', 1, 0, Val_pretty_default);
- printf_filtered ("\n");
- }
+ convert_typed_floating (from, type, to, builtin_type_double);
+ put_frame_register (frame, regnum, to);
}
+/* Move SPE vector register values between a 64-bit buffer and the two
+ 32-bit raw register halves in a regcache. This function handles
+ both splitting a 64-bit value into two 32-bit halves, and joining
+ two halves into a whole 64-bit value, depending on the function
+ passed as the MOVE argument.
+
+ EV_REG must be the number of an SPE evN vector register --- a
+ pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
+ 64-bit buffer.
+
+ Call MOVE once for each 32-bit half of that register, passing
+ REGCACHE, the number of the raw register corresponding to that
+ half, and the address of the appropriate half of BUFFER.
+
+ For example, passing 'regcache_raw_read' as the MOVE function will
+ fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
+ 'regcache_raw_supply' will supply the contents of BUFFER to the
+ appropriate pair of raw registers in REGCACHE.
+
+ You may need to cast away some 'const' qualifiers when passing
+ MOVE, since this function can't tell at compile-time which of
+ REGCACHE or BUFFER is acting as the source of the data. If C had
+ co-variant type qualifiers, ... */
static void
-rs6000_altivec_registers_info (char *addr_exp, int from_tty)
+e500_move_ev_register (void (*move) (struct regcache *regcache,
+ int regnum, gdb_byte *buf),
+ struct regcache *regcache, int ev_reg,
+ gdb_byte *buffer)
{
- int regnum, numregs;
- register char *end;
+ struct gdbarch *arch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
+ int reg_index;
+ gdb_byte *byte_buffer = buffer;
- if (!target_has_registers)
- error ("The program has no registers now.");
- if (selected_frame == NULL)
- error ("No selected frame.");
+ gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
+ && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
- if (!addr_exp)
+ reg_index = ev_reg - tdep->ppc_ev0_regnum;
+
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
{
- rs6000_do_altivec_registers (-1);
- return;
+ move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
+ move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
}
-
- numregs = NUM_REGS + NUM_PSEUDO_REGS;
- do
+ else
{
- if (addr_exp[0] == '$')
- addr_exp++;
- end = addr_exp;
- while (*end != '\0' && *end != ' ' && *end != '\t')
- ++end;
-
- regnum = target_map_name_to_register (addr_exp, end - addr_exp);
- if (regnum < 0)
- {
- regnum = numregs;
- if (*addr_exp >= '0' && *addr_exp <= '9')
- regnum = atoi (addr_exp); /* Take a number */
- if (regnum >= numregs) /* Bad name, or bad number */
- error ("%.*s: invalid register", end - addr_exp, addr_exp);
- }
-
- rs6000_do_altivec_registers (regnum);
-
- addr_exp = end;
- while (*addr_exp == ' ' || *addr_exp == '\t')
- ++addr_exp;
+ move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
+ move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
}
- while (*addr_exp != '\0');
}
static void
-rs6000_do_registers_info (int regnum, int fpregs)
+e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
+ int reg_nr, gdb_byte *buffer)
{
- register int i;
- int numregs = NUM_REGS + NUM_PSEUDO_REGS;
- char *raw_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
- char *virtual_buffer = (char*) alloca (MAX_REGISTER_VIRTUAL_SIZE);
+ struct gdbarch *regcache_arch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- for (i = 0; i < numregs; i++)
- {
- /* Decide between printing all regs, nonfloat regs, or specific reg. */
- if (regnum == -1)
- {
- if ((TYPE_CODE (REGISTER_VIRTUAL_TYPE (i)) == TYPE_CODE_FLT && !fpregs)
- || (altivec_register_p (i) && !fpregs))
- continue;
- }
- else
- {
- if (i != regnum)
- continue;
- }
-
- /* If the register name is empty, it is undefined for this
- processor, so don't display anything. */
- if (REGISTER_NAME (i) == NULL || *(REGISTER_NAME (i)) == '\0')
- continue;
-
- fputs_filtered (REGISTER_NAME (i), gdb_stdout);
- print_spaces_filtered (15 - strlen (REGISTER_NAME (i)), gdb_stdout);
-
- /* Get the data in raw format. */
- if (!frame_register_read (selected_frame, i, raw_buffer))
- {
- printf_filtered ("*value not available*\n");
- continue;
- }
-
- /* Convert raw data to virtual format if necessary. */
- if (REGISTER_CONVERTIBLE (i))
- REGISTER_CONVERT_TO_VIRTUAL (i, REGISTER_VIRTUAL_TYPE (i),
- raw_buffer, virtual_buffer);
- else
- memcpy (virtual_buffer, raw_buffer, REGISTER_VIRTUAL_SIZE (i));
-
- /* If virtual format is floating, print it that way, and in raw hex. */
- if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (i)) == TYPE_CODE_FLT)
- {
- register int j;
+ gdb_assert (regcache_arch == gdbarch);
+
+ if (tdep->ppc_ev0_regnum <= reg_nr
+ && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
+ e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
+ else
+ internal_error (__FILE__, __LINE__,
+ _("e500_pseudo_register_read: "
+ "called on unexpected register '%s' (%d)"),
+ gdbarch_register_name (gdbarch, reg_nr), reg_nr);
+}
- val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
- gdb_stdout, 0, 1, 0, Val_pretty_default);
+static void
+e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
+ int reg_nr, const gdb_byte *buffer)
+{
+ struct gdbarch *regcache_arch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ gdb_assert (regcache_arch == gdbarch);
+
+ if (tdep->ppc_ev0_regnum <= reg_nr
+ && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
+ e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
+ regcache_raw_write,
+ regcache, reg_nr, (gdb_byte *) buffer);
+ else
+ internal_error (__FILE__, __LINE__,
+ _("e500_pseudo_register_read: "
+ "called on unexpected register '%s' (%d)"),
+ gdbarch_register_name (gdbarch, reg_nr), reg_nr);
+}
- printf_filtered ("\t(raw 0x");
- for (j = 0; j < REGISTER_RAW_SIZE (i); j++)
- {
- register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
- : REGISTER_RAW_SIZE (i) - 1 - j;
- printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
- }
- printf_filtered (")");
- }
- else
- {
- /* Print as integer in hex and in decimal. */
- if (!altivec_register_p (i))
- {
- val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
- gdb_stdout, 'x', 1, 0, Val_pretty_default);
- printf_filtered ("\t");
- val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
- gdb_stdout, 0, 1, 0, Val_pretty_default);
- }
- else
- /* Print as integer in hex only. */
- val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
- gdb_stdout, 'x', 1, 0, Val_pretty_default);
- }
- printf_filtered ("\n");
- }
+/* The E500 needs a custom reggroup function: it has anonymous raw
+ registers, and default_register_reggroup_p assumes that anonymous
+ registers are not members of any reggroup. */
+static int
+e500_register_reggroup_p (struct gdbarch *gdbarch,
+ int regnum,
+ struct reggroup *group)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ /* The save and restore register groups need to include the
+ upper-half registers, even though they're anonymous. */
+ if ((group == save_reggroup
+ || group == restore_reggroup)
+ && (tdep->ppc_ev0_upper_regnum <= regnum
+ && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
+ return 1;
+
+ /* In all other regards, the default reggroup definition is fine. */
+ return default_register_reggroup_p (gdbarch, regnum, group);
}
-/* Convert a dbx stab register number (from `r' declaration) to a gdb
- REGNUM. */
+/* Convert a DBX STABS register number to a GDB register number. */
static int
rs6000_stab_reg_to_regnum (int num)
{
- int regnum;
- switch (num)
- {
- case 64:
- regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum;
- break;
- case 65:
- regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum;
- break;
- case 66:
- regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum;
- break;
- case 76:
- regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum;
- break;
- default:
- regnum = num;
- break;
- }
- return regnum;
-}
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-/* Store the address of the place in which to copy the structure the
- subroutine will return. This is called from call_function.
+ if (0 <= num && num <= 31)
+ return tdep->ppc_gp0_regnum + num;
+ else if (32 <= num && num <= 63)
+ /* FIXME: jimb/2004-05-05: What should we do when the debug info
+ specifies registers the architecture doesn't have? Our
+ callers don't check the value we return. */
+ return tdep->ppc_fp0_regnum + (num - 32);
+ else if (77 <= num && num <= 108)
+ return tdep->ppc_vr0_regnum + (num - 77);
+ else if (1200 <= num && num < 1200 + 32)
+ return tdep->ppc_ev0_regnum + (num - 1200);
+ else
+ switch (num)
+ {
+ case 64:
+ return tdep->ppc_mq_regnum;
+ case 65:
+ return tdep->ppc_lr_regnum;
+ case 66:
+ return tdep->ppc_ctr_regnum;
+ case 76:
+ return tdep->ppc_xer_regnum;
+ case 109:
+ return tdep->ppc_vrsave_regnum;
+ case 110:
+ return tdep->ppc_vrsave_regnum - 1; /* vscr */
+ case 111:
+ return tdep->ppc_acc_regnum;
+ case 112:
+ return tdep->ppc_spefscr_regnum;
+ default:
+ return num;
+ }
+}
- In RS/6000, struct return addresses are passed as an extra parameter in r3.
- In function return, callee is not responsible of returning this address
- back. Since gdb needs to find it, we will store in a designated variable
- `rs6000_struct_return_address'. */
-static void
-rs6000_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
+/* Convert a Dwarf 2 register number to a GDB register number. */
+static int
+rs6000_dwarf2_reg_to_regnum (int num)
{
- write_register (3, addr);
- rs6000_struct_return_address = addr;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (0 <= num && num <= 31)
+ return tdep->ppc_gp0_regnum + num;
+ else if (32 <= num && num <= 63)
+ /* FIXME: jimb/2004-05-05: What should we do when the debug info
+ specifies registers the architecture doesn't have? Our
+ callers don't check the value we return. */
+ return tdep->ppc_fp0_regnum + (num - 32);
+ else if (1124 <= num && num < 1124 + 32)
+ return tdep->ppc_vr0_regnum + (num - 1124);
+ else if (1200 <= num && num < 1200 + 32)
+ return tdep->ppc_ev0_regnum + (num - 1200);
+ else
+ switch (num)
+ {
+ case 67:
+ return tdep->ppc_vrsave_regnum - 1; /* vscr */
+ case 99:
+ return tdep->ppc_acc_regnum;
+ case 100:
+ return tdep->ppc_mq_regnum;
+ case 101:
+ return tdep->ppc_xer_regnum;
+ case 108:
+ return tdep->ppc_lr_regnum;
+ case 109:
+ return tdep->ppc_ctr_regnum;
+ case 356:
+ return tdep->ppc_vrsave_regnum;
+ case 612:
+ return tdep->ppc_spefscr_regnum;
+ default:
+ return num;
+ }
}
-/* Write into appropriate registers a function return value
- of type TYPE, given in virtual format. */
static void
-rs6000_store_return_value (struct type *type, char *valbuf)
+rs6000_store_return_value (struct type *type,
+ struct regcache *regcache,
+ const gdb_byte *valbuf)
{
- if (TYPE_CODE (type) == TYPE_CODE_FLT)
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int regnum = -1;
+ /* The calling convention this function implements assumes the
+ processor has floating-point registers. We shouldn't be using it
+ on PPC variants that lack them. */
+ gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT)
/* Floating point values are returned starting from FPR1 and up.
Say a double_double_double type could be returned in
- FPR1/FPR2/FPR3 triple. */
-
- write_register_bytes (REGISTER_BYTE (FP0_REGNUM + 1), valbuf,
- TYPE_LENGTH (type));
+ FPR1/FPR2/FPR3 triple. */
+ regnum = tdep->ppc_fp0_regnum + 1;
+ else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
+ {
+ if (TYPE_LENGTH (type) == 16
+ && TYPE_VECTOR (type))
+ regnum = tdep->ppc_vr0_regnum + 2;
+ else
+ internal_error (__FILE__, __LINE__,
+ _("rs6000_store_return_value: "
+ "unexpected array return type"));
+ }
else
- /* Everything else is returned in GPR3 and up. */
- write_register_bytes (REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3),
- valbuf, TYPE_LENGTH (type));
+ /* Everything else is returned in GPR3 and up. */
+ regnum = tdep->ppc_gp0_regnum + 3;
+
+ {
+ size_t bytes_written = 0;
+
+ while (bytes_written < TYPE_LENGTH (type))
+ {
+ /* How much of this value can we write to this register? */
+ size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written,
+ register_size (gdbarch, regnum));
+ regcache_cooked_write_part (regcache, regnum,
+ 0, bytes_to_write,
+ valbuf + bytes_written);
+ regnum++;
+ bytes_written += bytes_to_write;
+ }
+ }
}
+
/* Extract from an array REGBUF containing the (raw) register state
the address in which a function should return its structure value,
as a CORE_ADDR (or an expression that can be used as one). */
static CORE_ADDR
-rs6000_extract_struct_value_address (char *regbuf)
-{
- return rs6000_struct_return_address;
-}
-
-/* Return whether PC is in a dummy function call.
-
- FIXME: This just checks for the end of the stack, which is broken
- for things like stepping through gcc nested function stubs. */
-
-static int
-rs6000_pc_in_call_dummy (CORE_ADDR pc, CORE_ADDR sp, CORE_ADDR fp)
-{
- return sp < pc && pc < fp;
+rs6000_extract_struct_value_address (struct regcache *regcache)
+{
+ /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
+ function call GDB knows the address of the struct return value
+ and hence, should not need to call this function. Unfortunately,
+ the current call_function_by_hand() code only saves the most
+ recent struct address leading to occasional calls. The code
+ should instead maintain a stack of such addresses (in the dummy
+ frame object). */
+ /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
+ really got no idea where the return value is being stored. While
+ r3, on function entry, contained the address it will have since
+ been reused (scratch) and hence wouldn't be valid */
+ return 0;
}
-/* Hook called when a new child process is started. */
+/* Hook called when a new child process is started. */
void
rs6000_create_inferior (int pid)
rs6000_set_host_arch_hook (pid);
}
\f
-/* Support for CONVERT_FROM_FUNC_PTR_ADDR(ADDR).
+/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
Usually a function pointer's representation is simply the address
of the function. On the RS/6000 however, a function pointer is
/* Return real function address if ADDR (a function pointer) is in the data
space and is therefore a special function pointer. */
-CORE_ADDR
-rs6000_convert_from_func_ptr_addr (CORE_ADDR addr)
+static CORE_ADDR
+rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
+ CORE_ADDR addr,
+ struct target_ops *targ)
{
struct obj_section *s;
return addr;
/* ADDR is in the data space, so it's a special function pointer. */
- return read_memory_addr (addr, TDEP->wordsize);
+ return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
}
\f
Most of these register groups aren't anything formal. I arrived at
them by looking at the registers that occurred in more than one
- processor. */
-
-/* Convenience macros for populating register arrays. */
-
-/* Within another macro, convert S to a string. */
+ processor.
+
+ Note: kevinb/2002-04-30: Support for the fpscr register was added
+ during April, 2002. Slot 70 is being used for PowerPC and slot 71
+ for Power. For PowerPC, slot 70 was unused and was already in the
+ PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
+ slot 70 was being used for "mq", so the next available slot (71)
+ was chosen. It would have been nice to be able to make the
+ register numbers the same across processor cores, but this wasn't
+ possible without either 1) renumbering some registers for some
+ processors or 2) assigning fpscr to a really high slot that's
+ larger than any current register number. Doing (1) is bad because
+ existing stubs would break. Doing (2) is undesirable because it
+ would introduce a really large gap between fpscr and the rest of
+ the registers for most processors. */
+
+/* Convenience macros for populating register arrays. */
+
+/* Within another macro, convert S to a string. */
#define STR(s) #s
/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
- and 64 bits on 64-bit systems. */
-#define R(name) { STR(name), 4, 8, 0 }
+ and 64 bits on 64-bit systems. */
+#define R(name) { STR(name), 4, 8, 0, 0, -1 }
/* Return a struct reg defining register NAME that's 32 bits on all
- systems. */
-#define R4(name) { STR(name), 4, 4, 0 }
+ systems. */
+#define R4(name) { STR(name), 4, 4, 0, 0, -1 }
/* Return a struct reg defining register NAME that's 64 bits on all
- systems. */
-#define R8(name) { STR(name), 8, 8, 0 }
+ systems. */
+#define R8(name) { STR(name), 8, 8, 0, 0, -1 }
/* Return a struct reg defining register NAME that's 128 bits on all
- systems. */
-#define R16(name) { STR(name), 16, 16, 0 }
+ systems. */
+#define R16(name) { STR(name), 16, 16, 0, 0, -1 }
-/* Return a struct reg defining floating-point register NAME. */
-#define F(name) { STR(name), 8, 8, 1 }
+/* Return a struct reg defining floating-point register NAME. */
+#define F(name) { STR(name), 8, 8, 1, 0, -1 }
+
+/* Return a struct reg defining a pseudo register NAME that is 64 bits
+ long on all systems. */
+#define P8(name) { STR(name), 8, 8, 0, 1, -1 }
/* Return a struct reg defining register NAME that's 32 bits on 32-bit
- systems and that doesn't exist on 64-bit systems. */
-#define R32(name) { STR(name), 4, 0, 0 }
+ systems and that doesn't exist on 64-bit systems. */
+#define R32(name) { STR(name), 4, 0, 0, 0, -1 }
/* Return a struct reg defining register NAME that's 64 bits on 64-bit
- systems and that doesn't exist on 32-bit systems. */
-#define R64(name) { STR(name), 0, 8, 0 }
+ systems and that doesn't exist on 32-bit systems. */
+#define R64(name) { STR(name), 0, 8, 0, 0, -1 }
+
+/* Return a struct reg placeholder for a register that doesn't exist. */
+#define R0 { 0, 0, 0, 0, 0, -1 }
-/* Return a struct reg placeholder for a register that doesn't exist. */
-#define R0 { 0, 0, 0, 0 }
+/* Return a struct reg defining an anonymous raw register that's 32
+ bits on all systems. */
+#define A4 { 0, 4, 4, 0, 0, -1 }
+/* Return a struct reg defining an SPR named NAME that is 32 bits on
+ 32-bit systems and 64 bits on 64-bit systems. */
+#define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
+
+/* Return a struct reg defining an SPR named NAME that is 32 bits on
+ all systems. */
+#define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
+
+/* Return a struct reg defining an SPR named NAME that is 32 bits on
+ all systems, and whose SPR number is NUMBER. */
+#define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
+
+/* Return a struct reg defining an SPR named NAME that's 64 bits on
+ 64-bit systems and that doesn't exist on 32-bit systems. */
+#define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
+
/* UISA registers common across all architectures, including POWER. */
#define COMMON_UISA_REGS \
/* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
/* 64 */ R(pc), R(ps)
-#define COMMON_UISA_NOFP_REGS \
- /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
- /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
- /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
- /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
- /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
- /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
- /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
- /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
- /* 64 */ R(pc), R(ps)
-
/* UISA-level SPRs for PowerPC. */
#define PPC_UISA_SPRS \
- /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
+ /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
+
+/* UISA-level SPRs for PowerPC without floating point support. */
+#define PPC_UISA_NOFP_SPRS \
+ /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
/* Segment registers, for PowerPC. */
#define PPC_SEGMENT_REGS \
/* OEA SPRs for PowerPC. */
#define PPC_OEA_SPRS \
- /* 87 */ R4(pvr), \
- /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
- /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
- /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
- /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
- /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
- /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
- /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
- /* 116 */ R4(dec), R(dabr), R4(ear)
-
-/* AltiVec registers */
+ /* 87 */ S4(pvr), \
+ /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
+ /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
+ /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
+ /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
+ /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
+ /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
+ /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
+ /* 116 */ S4(dec), S(dabr), S4(ear)
+
+/* AltiVec registers. */
#define PPC_ALTIVEC_REGS \
/*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
/*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
/*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
/*151*/R4(vscr), R4(vrsave)
+
+/* On machines supporting the SPE APU, the general-purpose registers
+ are 64 bits long. There are SIMD vector instructions to treat them
+ as pairs of floats, but the rest of the instruction set treats them
+ as 32-bit registers, and only operates on their lower halves.
+
+ In the GDB regcache, we treat their high and low halves as separate
+ registers. The low halves we present as the general-purpose
+ registers, and then we have pseudo-registers that stitch together
+ the upper and lower halves and present them as pseudo-registers. */
+
+/* SPE GPR lower halves --- raw registers. */
+#define PPC_SPE_GP_REGS \
+ /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
+ /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
+ /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
+ /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
+
+/* SPE GPR upper halves --- anonymous raw registers. */
+#define PPC_SPE_UPPER_GP_REGS \
+ /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
+ /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
+ /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
+ /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
+
+/* SPE GPR vector registers --- pseudo registers based on underlying
+ gprs and the anonymous upper half raw registers. */
+#define PPC_EV_PSEUDO_REGS \
+/* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
+/* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
+/*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
+/*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
+
/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
- user-level SPR's. */
+ user-level SPR's. */
static const struct reg registers_power[] =
{
COMMON_UISA_REGS,
- /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
+ /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
/* 71 */ R4(fpscr)
};
/* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
- view of the PowerPC. */
+ view of the PowerPC. */
static const struct reg registers_powerpc[] =
{
COMMON_UISA_REGS,
PPC_ALTIVEC_REGS
};
-/* PowerPC UISA - a PPC processor as viewed by user-level
- code, but without floating point registers. */
-static const struct reg registers_powerpc_nofp[] =
-{
- COMMON_UISA_NOFP_REGS,
- PPC_UISA_SPRS
-};
+/* IBM PowerPC 403.
+
+ Some notes about the "tcr" special-purpose register:
+ - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
+ 403's programmable interval timer, fixed interval timer, and
+ watchdog timer.
+ - On the 602, SPR 984 is named "tcr", and it controls the 602's
+ watchdog timer, and nothing else.
-/* IBM PowerPC 403. */
+ Some of the fields are similar between the two, but they're not
+ compatible with each other. Since the two variants have different
+ registers, with different numbers, but the same name, we can't
+ splice the register name to get the SPR number. */
static const struct reg registers_403[] =
{
COMMON_UISA_REGS,
PPC_UISA_SPRS,
PPC_SEGMENT_REGS,
PPC_OEA_SPRS,
- /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
- /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
- /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
- /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
- /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
- /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2)
+ /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
+ /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
+ /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
+ /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
+ /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
+ /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
};
-/* IBM PowerPC 403GC. */
+/* IBM PowerPC 403GC.
+ See the comments about 'tcr' for the 403, above. */
static const struct reg registers_403GC[] =
{
COMMON_UISA_REGS,
PPC_UISA_SPRS,
PPC_SEGMENT_REGS,
PPC_OEA_SPRS,
- /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
- /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
- /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
- /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
- /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
- /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2),
- /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr),
- /* 147 */ R(tbhu), R(tblu)
+ /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
+ /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
+ /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
+ /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
+ /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
+ /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
+ /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
+ /* 147 */ S(tbhu), S(tblu)
};
-/* Motorola PowerPC 505. */
+/* Motorola PowerPC 505. */
static const struct reg registers_505[] =
{
COMMON_UISA_REGS,
PPC_UISA_SPRS,
PPC_SEGMENT_REGS,
PPC_OEA_SPRS,
- /* 119 */ R(eie), R(eid), R(nri)
+ /* 119 */ S(eie), S(eid), S(nri)
};
-/* Motorola PowerPC 860 or 850. */
+/* Motorola PowerPC 860 or 850. */
static const struct reg registers_860[] =
{
COMMON_UISA_REGS,
PPC_UISA_SPRS,
PPC_SEGMENT_REGS,
PPC_OEA_SPRS,
- /* 119 */ R(eie), R(eid), R(nri), R(cmpa),
- /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr),
- /* 127 */ R(der), R(counta), R(countb), R(cmpe),
- /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1),
- /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst),
- /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr),
- /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr),
- /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc),
- /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap),
- /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn),
- /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1),
- /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1)
+ /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
+ /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
+ /* 127 */ S(der), S(counta), S(countb), S(cmpe),
+ /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
+ /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
+ /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
+ /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
+ /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
+ /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
+ /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
+ /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
+ /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
};
/* Motorola PowerPC 601. Note that the 601 has different register numbers
PPC_UISA_SPRS,
PPC_SEGMENT_REGS,
PPC_OEA_SPRS,
- /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
- /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl)
+ /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
+ /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
};
-/* Motorola PowerPC 602. */
+/* Motorola PowerPC 602.
+ See the notes under the 403 about 'tcr'. */
static const struct reg registers_602[] =
{
COMMON_UISA_REGS,
PPC_UISA_SPRS,
PPC_SEGMENT_REGS,
PPC_OEA_SPRS,
- /* 119 */ R(hid0), R(hid1), R(iabr), R0,
- /* 123 */ R0, R(tcr), R(ibr), R(esassr),
- /* 127 */ R(sebr), R(ser), R(sp), R(lt)
+ /* 119 */ S(hid0), S(hid1), S(iabr), R0,
+ /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
+ /* 127 */ S(sebr), S(ser), S(sp), S(lt)
};
-/* Motorola/IBM PowerPC 603 or 603e. */
+/* Motorola/IBM PowerPC 603 or 603e. */
static const struct reg registers_603[] =
{
COMMON_UISA_REGS,
PPC_UISA_SPRS,
PPC_SEGMENT_REGS,
PPC_OEA_SPRS,
- /* 119 */ R(hid0), R(hid1), R(iabr), R0,
- /* 123 */ R0, R(dmiss), R(dcmp), R(hash1),
- /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa)
+ /* 119 */ S(hid0), S(hid1), S(iabr), R0,
+ /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
+ /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
};
-/* Motorola PowerPC 604 or 604e. */
+/* Motorola PowerPC 604 or 604e. */
static const struct reg registers_604[] =
{
COMMON_UISA_REGS,
PPC_UISA_SPRS,
PPC_SEGMENT_REGS,
PPC_OEA_SPRS,
- /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
- /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2),
- /* 127 */ R(sia), R(sda)
+ /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
+ /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
+ /* 127 */ S(sia), S(sda)
};
-/* Motorola/IBM PowerPC 750 or 740. */
+/* Motorola/IBM PowerPC 750 or 740. */
static const struct reg registers_750[] =
{
COMMON_UISA_REGS,
PPC_UISA_SPRS,
PPC_SEGMENT_REGS,
PPC_OEA_SPRS,
- /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
- /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2),
- /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4),
- /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia),
- /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr),
- /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3)
+ /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
+ /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
+ /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
+ /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
+ /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
+ /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
};
-/* Motorola PowerPC 7400. */
+/* Motorola PowerPC 7400. */
static const struct reg registers_7400[] =
{
/* gpr0-gpr31, fpr0-fpr31 */
COMMON_UISA_REGS,
- /* ctr, xre, lr, cr */
+ /* cr, lr, ctr, xer, fpscr */
PPC_UISA_SPRS,
/* sr0-sr15 */
PPC_SEGMENT_REGS,
/* FIXME? Add more registers? */
};
+/* Motorola e500. */
+static const struct reg registers_e500[] =
+{
+ /* 0 .. 31 */ PPC_SPE_GP_REGS,
+ /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
+ /* 64 .. 65 */ R(pc), R(ps),
+ /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
+ /* 71 .. 72 */ R8(acc), S4(spefscr),
+ /* NOTE: Add new registers here the end of the raw register
+ list and just before the first pseudo register. */
+ /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
+};
+
/* Information about a particular processor variant. */
struct variant
/* English description of the variant. */
char *description;
- /* bfd_arch_info.arch corresponding to variant. */
+ /* bfd_arch_info.arch corresponding to variant. */
enum bfd_architecture arch;
- /* bfd_arch_info.mach corresponding to variant. */
+ /* bfd_arch_info.mach corresponding to variant. */
unsigned long mach;
+ /* Number of real registers. */
+ int nregs;
+
+ /* Number of pseudo registers. */
+ int npregs;
+
+ /* Number of total registers (the sum of nregs and npregs). */
+ int num_tot_regs;
+
/* Table of register names; registers[R] is the name of the register
number R. */
- int nregs;
const struct reg *regs;
};
-#define num_registers(list) (sizeof (list) / sizeof((list)[0]))
+#define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
+
+static int
+num_registers (const struct reg *reg_list, int num_tot_regs)
+{
+ int i;
+ int nregs = 0;
+
+ for (i = 0; i < num_tot_regs; i++)
+ if (!reg_list[i].pseudo)
+ nregs++;
+
+ return nregs;
+}
+
+static int
+num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
+{
+ int i;
+ int npregs = 0;
+
+ for (i = 0; i < num_tot_regs; i++)
+ if (reg_list[i].pseudo)
+ npregs ++;
+ return npregs;
+}
/* Information in this table comes from the following web sites:
IBM: http://www.chips.ibm.com:80/products/embedded/
If you add entries to this table, please be sure to allow the new
value as an argument to the --with-cpu flag, in configure.in. */
-static const struct variant variants[] =
+static struct variant variants[] =
{
+
{"powerpc", "PowerPC user-level", bfd_arch_powerpc,
- bfd_mach_ppc, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
{"power", "POWER user-level", bfd_arch_rs6000,
- bfd_mach_rs6k, num_registers (registers_power), registers_power},
+ bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
+ registers_power},
{"403", "IBM PowerPC 403", bfd_arch_powerpc,
- bfd_mach_ppc_403, num_registers (registers_403), registers_403},
+ bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
+ registers_403},
{"601", "Motorola PowerPC 601", bfd_arch_powerpc,
- bfd_mach_ppc_601, num_registers (registers_601), registers_601},
+ bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
+ registers_601},
{"602", "Motorola PowerPC 602", bfd_arch_powerpc,
- bfd_mach_ppc_602, num_registers (registers_602), registers_602},
+ bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
+ registers_602},
{"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
- bfd_mach_ppc_603, num_registers (registers_603), registers_603},
+ bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
+ registers_603},
{"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
- 604, num_registers (registers_604), registers_604},
+ 604, -1, -1, tot_num_registers (registers_604),
+ registers_604},
{"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
- bfd_mach_ppc_403gc, num_registers (registers_403GC), registers_403GC},
+ bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
+ registers_403GC},
{"505", "Motorola PowerPC 505", bfd_arch_powerpc,
- bfd_mach_ppc_505, num_registers (registers_505), registers_505},
+ bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
+ registers_505},
{"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
- bfd_mach_ppc_860, num_registers (registers_860), registers_860},
+ bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
+ registers_860},
{"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
- bfd_mach_ppc_750, num_registers (registers_750), registers_750},
+ bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
+ registers_750},
{"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
- bfd_mach_ppc_7400, num_registers (registers_7400), registers_7400},
+ bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
+ registers_7400},
+ {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
+ bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
+ registers_e500},
/* 64-bit */
{"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
- bfd_mach_ppc64, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
{"620", "Motorola PowerPC 620", bfd_arch_powerpc,
- bfd_mach_ppc_620, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
{"630", "Motorola PowerPC 630", bfd_arch_powerpc,
- bfd_mach_ppc_630, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
{"a35", "PowerPC A35", bfd_arch_powerpc,
- bfd_mach_ppc_a35, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
{"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
- bfd_mach_ppc_rs64ii, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
{"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
- bfd_mach_ppc_rs64iii, num_registers (registers_powerpc), registers_powerpc},
+ bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
+ registers_powerpc},
- /* FIXME: I haven't checked the register sets of the following. */
+ /* FIXME: I haven't checked the register sets of the following. */
{"rs1", "IBM POWER RS1", bfd_arch_rs6000,
- bfd_mach_rs6k_rs1, num_registers (registers_power), registers_power},
+ bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
+ registers_power},
{"rsc", "IBM POWER RSC", bfd_arch_rs6000,
- bfd_mach_rs6k_rsc, num_registers (registers_power), registers_power},
+ bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
+ registers_power},
{"rs2", "IBM POWER RS2", bfd_arch_rs6000,
- bfd_mach_rs6k_rs2, num_registers (registers_power), registers_power},
+ bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
+ registers_power},
- {0, 0, 0, 0}
+ {0, 0, 0, 0, 0, 0, 0, 0}
};
-#undef num_registers
+/* Initialize the number of registers and pseudo registers in each variant. */
+
+static void
+init_variants (void)
+{
+ struct variant *v;
+
+ for (v = variants; v->name; v++)
+ {
+ if (v->nregs == -1)
+ v->nregs = num_registers (v->regs, v->num_tot_regs);
+ if (v->npregs == -1)
+ v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
+ }
+}
/* Return the variant corresponding to architecture ARCH and machine number
- MACH. If no such variant exists, return null. */
+ MACH. If no such variant exists, return null. */
static const struct variant *
find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
return NULL;
}
+static int
+gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
+{
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ return print_insn_big_powerpc (memaddr, info);
+ else
+ return print_insn_little_powerpc (memaddr, info);
+}
+\f
+static CORE_ADDR
+rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+ return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
+}
+
+static struct frame_id
+rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+ return frame_id_build (frame_unwind_register_unsigned (next_frame,
+ SP_REGNUM),
+ frame_pc_unwind (next_frame));
+}
+struct rs6000_frame_cache
+{
+ CORE_ADDR base;
+ CORE_ADDR initial_sp;
+ struct trad_frame_saved_reg *saved_regs;
+};
-\f
-static void
-process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj)
+static struct rs6000_frame_cache *
+rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
{
- int *os_ident_ptr = obj;
- const char *name;
- unsigned int sectsize;
+ struct rs6000_frame_cache *cache;
+ struct gdbarch *gdbarch = get_frame_arch (next_frame);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ struct rs6000_framedata fdata;
+ int wordsize = tdep->wordsize;
+
+ if ((*this_cache) != NULL)
+ return (*this_cache);
+ cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
+ (*this_cache) = cache;
+ cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
- name = bfd_get_section_name (abfd, sect);
- sectsize = bfd_section_size (abfd, sect);
- if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0)
+ skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame),
+ &fdata);
+
+ /* If there were any saved registers, figure out parent's stack
+ pointer. */
+ /* The following is true only if the frame doesn't have a call to
+ alloca(), FIXME. */
+
+ if (fdata.saved_fpr == 0
+ && fdata.saved_gpr == 0
+ && fdata.saved_vr == 0
+ && fdata.saved_ev == 0
+ && fdata.lr_offset == 0
+ && fdata.cr_offset == 0
+ && fdata.vr_offset == 0
+ && fdata.ev_offset == 0)
+ cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
+ else
{
- unsigned int name_length, data_length, note_type;
- char *note = alloca (sectsize);
+ /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
+ address of the current frame. Things might be easier if the
+ ->frame pointed to the outer-most address of the frame. In
+ the mean time, the address of the prev frame is used as the
+ base address of this frame. */
+ cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
+ if (!fdata.frameless)
+ /* Frameless really means stackless. */
+ cache->base = read_memory_addr (cache->base, wordsize);
+ }
+ trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
+
+ /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
+ All fpr's from saved_fpr to fp31 are saved. */
- bfd_get_section_contents (abfd, sect, note,
- (file_ptr) 0, (bfd_size_type) sectsize);
+ if (fdata.saved_fpr >= 0)
+ {
+ int i;
+ CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
+
+ /* If skip_prologue says floating-point registers were saved,
+ but the current architecture has no floating-point registers,
+ then that's strange. But we have no indices to even record
+ the addresses under, so we just ignore it. */
+ if (ppc_floating_point_unit_p (gdbarch))
+ for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
+ {
+ cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
+ fpr_addr += 8;
+ }
+ }
- name_length = bfd_h_get_32 (abfd, note);
- data_length = bfd_h_get_32 (abfd, note + 4);
- note_type = bfd_h_get_32 (abfd, note + 8);
+ /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
+ All gpr's from saved_gpr to gpr31 are saved. */
- if (name_length == 4 && data_length == 16 && note_type == 1
- && strcmp (note + 12, "GNU") == 0)
+ if (fdata.saved_gpr >= 0)
+ {
+ int i;
+ CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
+ for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
{
- int os_number = bfd_h_get_32 (abfd, note + 16);
+ cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
+ gpr_addr += wordsize;
+ }
+ }
- /* The case numbers are from abi-tags in glibc */
- switch (os_number)
+ /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
+ All vr's from saved_vr to vr31 are saved. */
+ if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
+ {
+ if (fdata.saved_vr >= 0)
+ {
+ int i;
+ CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
+ for (i = fdata.saved_vr; i < 32; i++)
{
- case 0 :
- *os_ident_ptr = ELFOSABI_LINUX;
- break;
- case 1 :
- *os_ident_ptr = ELFOSABI_HURD;
- break;
- case 2 :
- *os_ident_ptr = ELFOSABI_SOLARIS;
- break;
- default :
- internal_error (__FILE__, __LINE__,
- "process_note_abi_sections: unknown OS number %d",
- os_number);
- break;
+ cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
+ vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
}
}
}
-}
-
-/* Return one of the ELFOSABI_ constants for BFDs representing ELF
- executables. If it's not an ELF executable or if the OS/ABI couldn't
- be determined, simply return -1. */
-
-static int
-get_elfosabi (bfd *abfd)
-{
- int elfosabi = -1;
- if (abfd != NULL && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
+ /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
+ All vr's from saved_ev to ev31 are saved. ????? */
+ if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
{
- elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
-
- /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate
- that we're on a SYSV system. However, GNU/Linux uses a note section
- to record OS/ABI info, but leaves e_ident[EI_OSABI] zero. So we
- have to check the note sections too. */
- if (elfosabi == 0)
+ if (fdata.saved_ev >= 0)
{
- bfd_map_over_sections (abfd,
- process_note_abi_tag_sections,
- &elfosabi);
+ int i;
+ CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
+ for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
+ {
+ cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
+ cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
+ ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
+ }
}
}
- return elfosabi;
+ /* If != 0, fdata.cr_offset is the offset from the frame that
+ holds the CR. */
+ if (fdata.cr_offset != 0)
+ cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
+
+ /* If != 0, fdata.lr_offset is the offset from the frame that
+ holds the LR. */
+ if (fdata.lr_offset != 0)
+ cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
+ /* The PC is found in the link register. */
+ cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
+
+ /* If != 0, fdata.vrsave_offset is the offset from the frame that
+ holds the VRSAVE. */
+ if (fdata.vrsave_offset != 0)
+ cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
+
+ if (fdata.alloca_reg < 0)
+ /* If no alloca register used, then fi->frame is the value of the
+ %sp for this frame, and it is good enough. */
+ cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
+ else
+ cache->initial_sp = frame_unwind_register_unsigned (next_frame,
+ fdata.alloca_reg);
+
+ return cache;
+}
+
+static void
+rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
+ struct frame_id *this_id)
+{
+ struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
+ this_cache);
+ (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
+}
+
+static void
+rs6000_frame_prev_register (struct frame_info *next_frame,
+ void **this_cache,
+ int regnum, int *optimizedp,
+ enum lval_type *lvalp, CORE_ADDR *addrp,
+ int *realnump, gdb_byte *valuep)
+{
+ struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
+ this_cache);
+ trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
+ optimizedp, lvalp, addrp, realnump, valuep);
+}
+
+static const struct frame_unwind rs6000_frame_unwind =
+{
+ NORMAL_FRAME,
+ rs6000_frame_this_id,
+ rs6000_frame_prev_register
+};
+
+static const struct frame_unwind *
+rs6000_frame_sniffer (struct frame_info *next_frame)
+{
+ return &rs6000_frame_unwind;
}
\f
+static CORE_ADDR
+rs6000_frame_base_address (struct frame_info *next_frame,
+ void **this_cache)
+{
+ struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
+ this_cache);
+ return info->initial_sp;
+}
+
+static const struct frame_base rs6000_frame_base = {
+ &rs6000_frame_unwind,
+ rs6000_frame_base_address,
+ rs6000_frame_base_address,
+ rs6000_frame_base_address
+};
+
+static const struct frame_base *
+rs6000_frame_base_sniffer (struct frame_info *next_frame)
+{
+ return &rs6000_frame_base;
+}
+
/* Initialize the current architecture based on INFO. If possible, re-use an
architecture from ARCHES, which is a list of architectures already created
during this debugging session.
Called e.g. at program startup, when reading a core file, and when reading
- a binary file. */
+ a binary file. */
static struct gdbarch *
rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
struct gdbarch *gdbarch;
struct gdbarch_tdep *tdep;
- int wordsize, from_xcoff_exec, from_elf_exec, power, i, off;
+ int wordsize, from_xcoff_exec, from_elf_exec, i, off;
struct reg *regs;
const struct variant *v;
enum bfd_architecture arch;
unsigned long mach;
bfd abfd;
- int osabi, sysv_abi;
- gdbarch_print_insn_ftype *print_insn;
+ int sysv_abi;
+ asection *sect;
from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
- osabi = get_elfosabi (info.abfd);
-
/* Check word size. If INFO is from a binary file, infer it from
- that, else choose a likely default. */
+ that, else choose a likely default. */
if (from_xcoff_exec)
{
- if (xcoff_data (info.abfd)->xcoff64)
+ if (bfd_xcoff_is_xcoff64 (info.abfd))
wordsize = 8;
else
wordsize = 4;
wordsize = 4;
}
- /* Find a candidate among extant architectures. */
+ /* Find a candidate among extant architectures. */
for (arches = gdbarch_list_lookup_by_info (arches, &info);
arches != NULL;
arches = gdbarch_list_lookup_by_info (arches->next, &info))
{
/* Word size in the various PowerPC bfd_arch_info structs isn't
meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
- separate word size check. */
+ separate word size check. */
tdep = gdbarch_tdep (arches->gdbarch);
- if (tdep && tdep->wordsize == wordsize && tdep->osabi == osabi)
+ if (tdep && tdep->wordsize == wordsize)
return arches->gdbarch;
}
else
{
arch = bfd_arch_powerpc;
- mach = 0;
- bfd_default_set_arch_mach (&abfd, arch, mach);
+ bfd_default_set_arch_mach (&abfd, arch, 0);
info.bfd_arch_info = bfd_get_arch_info (&abfd);
+ mach = info.bfd_arch_info->mach;
}
tdep = xmalloc (sizeof (struct gdbarch_tdep));
tdep->wordsize = wordsize;
- tdep->osabi = osabi;
+
+ /* For e500 executables, the apuinfo section is of help here. Such
+ section contains the identifier and revision number of each
+ Application-specific Processing Unit that is present on the
+ chip. The content of the section is determined by the assembler
+ which looks at each instruction and determines which unit (and
+ which version of it) can execute it. In our case we just look for
+ the existance of the section. */
+
+ if (info.abfd)
+ {
+ sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
+ if (sect)
+ {
+ arch = info.bfd_arch_info->arch;
+ mach = bfd_mach_ppc_e500;
+ bfd_default_set_arch_mach (&abfd, arch, mach);
+ info.bfd_arch_info = bfd_get_arch_info (&abfd);
+ }
+ }
+
gdbarch = gdbarch_alloc (&info, tdep);
- power = arch == bfd_arch_rs6000;
- /* Choose variant. */
+ /* Initialize the number of real and pseudo registers in each variant. */
+ init_variants ();
+
+ /* Choose variant. */
v = find_variant_by_arch (arch, mach);
if (!v)
return NULL;
tdep->regs = v->regs;
tdep->ppc_gp0_regnum = 0;
- tdep->ppc_gplast_regnum = 31;
tdep->ppc_toc_regnum = 2;
tdep->ppc_ps_regnum = 65;
tdep->ppc_cr_regnum = 66;
tdep->ppc_xer_regnum = 69;
if (v->mach == bfd_mach_ppc_601)
tdep->ppc_mq_regnum = 124;
- else if (power)
+ else if (arch == bfd_arch_rs6000)
tdep->ppc_mq_regnum = 70;
else
tdep->ppc_mq_regnum = -1;
- tdep->ppc_fpscr_regnum = power ? 71 : 70;
+ tdep->ppc_fp0_regnum = 32;
+ tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
+ tdep->ppc_sr0_regnum = 71;
+ tdep->ppc_vr0_regnum = -1;
+ tdep->ppc_vrsave_regnum = -1;
+ tdep->ppc_ev0_upper_regnum = -1;
+ tdep->ppc_ev0_regnum = -1;
+ tdep->ppc_ev31_regnum = -1;
+ tdep->ppc_acc_regnum = -1;
+ tdep->ppc_spefscr_regnum = -1;
+
+ set_gdbarch_pc_regnum (gdbarch, 64);
+ set_gdbarch_sp_regnum (gdbarch, 1);
+ set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
+ set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
+ if (sysv_abi && wordsize == 8)
+ set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
+ else if (sysv_abi && wordsize == 4)
+ set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
+ else
+ {
+ set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
+ set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
+ }
+
+ /* Set lr_frame_offset. */
+ if (wordsize == 8)
+ tdep->lr_frame_offset = 16;
+ else if (sysv_abi)
+ tdep->lr_frame_offset = 4;
+ else
+ tdep->lr_frame_offset = 8;
- if (v->arch == bfd_arch_powerpc)
+ if (v->arch == bfd_arch_rs6000)
+ tdep->ppc_sr0_regnum = -1;
+ else if (v->arch == bfd_arch_powerpc)
switch (v->mach)
{
case bfd_mach_ppc:
+ tdep->ppc_sr0_regnum = -1;
tdep->ppc_vr0_regnum = 71;
tdep->ppc_vrsave_regnum = 104;
break;
case bfd_mach_ppc_7400:
tdep->ppc_vr0_regnum = 119;
- tdep->ppc_vrsave_regnum = 153;
+ tdep->ppc_vrsave_regnum = 152;
break;
- default:
- tdep->ppc_vr0_regnum = -1;
- tdep->ppc_vrsave_regnum = -1;
+ case bfd_mach_ppc_e500:
+ tdep->ppc_toc_regnum = -1;
+ tdep->ppc_ev0_upper_regnum = 32;
+ tdep->ppc_ev0_regnum = 73;
+ tdep->ppc_ev31_regnum = 104;
+ tdep->ppc_acc_regnum = 71;
+ tdep->ppc_spefscr_regnum = 72;
+ tdep->ppc_fp0_regnum = -1;
+ tdep->ppc_fpscr_regnum = -1;
+ tdep->ppc_sr0_regnum = -1;
+ set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
+ set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
+ set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
break;
- }
- /* Set lr_frame_offset. */
- if (wordsize == 8)
- tdep->lr_frame_offset = 16;
- else if (sysv_abi)
- tdep->lr_frame_offset = 4;
+ case bfd_mach_ppc64:
+ case bfd_mach_ppc_620:
+ case bfd_mach_ppc_630:
+ case bfd_mach_ppc_a35:
+ case bfd_mach_ppc_rs64ii:
+ case bfd_mach_ppc_rs64iii:
+ /* These processor's register sets don't have segment registers. */
+ tdep->ppc_sr0_regnum = -1;
+ break;
+ }
else
- tdep->lr_frame_offset = 8;
+ internal_error (__FILE__, __LINE__,
+ _("rs6000_gdbarch_init: "
+ "received unexpected BFD 'arch' value"));
- /* Calculate byte offsets in raw register array. */
- tdep->regoff = xmalloc (v->nregs * sizeof (int));
- for (i = off = 0; i < v->nregs; i++)
- {
- tdep->regoff[i] = off;
- off += regsize (v->regs + i, wordsize);
- }
+ /* Sanity check on registers. */
+ gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
/* Select instruction printer. */
- if (arch == power)
- print_insn = print_insn_rs6000;
- else if (info.byte_order == BFD_ENDIAN_BIG)
- print_insn = print_insn_big_powerpc;
+ if (arch == bfd_arch_rs6000)
+ set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
else
- print_insn = print_insn_little_powerpc;
- set_gdbarch_print_insn (gdbarch, print_insn);
+ set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
- set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
- set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
- set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
- set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
set_gdbarch_num_regs (gdbarch, v->nregs);
- set_gdbarch_sp_regnum (gdbarch, 1);
- set_gdbarch_fp_regnum (gdbarch, 1);
- set_gdbarch_pc_regnum (gdbarch, 64);
+ set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
set_gdbarch_register_name (gdbarch, rs6000_register_name);
- set_gdbarch_register_size (gdbarch, wordsize);
- set_gdbarch_register_bytes (gdbarch, off);
- set_gdbarch_register_byte (gdbarch, rs6000_register_byte);
- set_gdbarch_register_raw_size (gdbarch, rs6000_register_raw_size);
- set_gdbarch_max_register_raw_size (gdbarch, 16);
- set_gdbarch_register_virtual_size (gdbarch, generic_register_virtual_size);
- set_gdbarch_max_register_virtual_size (gdbarch, 16);
- set_gdbarch_register_virtual_type (gdbarch, rs6000_register_virtual_type);
- set_gdbarch_do_registers_info (gdbarch, rs6000_do_registers_info);
+ set_gdbarch_register_type (gdbarch, rs6000_register_type);
+ set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p);
set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
- set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+ if (sysv_abi)
+ set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
+ else
+ set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
set_gdbarch_char_signed (gdbarch, 0);
- set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
- set_gdbarch_call_dummy_length (gdbarch, 0);
- set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
- set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
- set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
- set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
- set_gdbarch_call_dummy_start_offset (gdbarch, 0);
- set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
- set_gdbarch_call_dummy_p (gdbarch, 1);
- set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
- set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
- set_gdbarch_fix_call_dummy (gdbarch, rs6000_fix_call_dummy);
- set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
- set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
- set_gdbarch_push_return_address (gdbarch, ppc_push_return_address);
- set_gdbarch_believe_pcc_promotion (gdbarch, 1);
- set_gdbarch_coerce_float_to_double (gdbarch, rs6000_coerce_float_to_double);
-
- set_gdbarch_register_convertible (gdbarch, rs6000_register_convertible);
- set_gdbarch_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual);
- set_gdbarch_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw);
- set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
+ set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
+ if (sysv_abi && wordsize == 8)
+ /* PPC64 SYSV. */
+ set_gdbarch_frame_red_zone_size (gdbarch, 288);
+ else if (!sysv_abi && wordsize == 4)
+ /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
+ 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
+ Problem is, 220 isn't frame (16 byte) aligned. Round it up to
+ 224. */
+ set_gdbarch_frame_red_zone_size (gdbarch, 224);
+
+ set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
+ set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
+ set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
- set_gdbarch_extract_return_value (gdbarch, rs6000_extract_return_value);
-
+ set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
/* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
is correct for the SysV ABI when the wordsize is 8, but I'm also
fairly certain that ppc_sysv_abi_push_arguments() will give even
64-bit code. At some point in the future, this matter needs to be
revisited. */
if (sysv_abi && wordsize == 4)
- set_gdbarch_push_arguments (gdbarch, ppc_sysv_abi_push_arguments);
+ set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
+ else if (sysv_abi && wordsize == 8)
+ set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
else
- set_gdbarch_push_arguments (gdbarch, rs6000_push_arguments);
+ set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
- set_gdbarch_store_struct_return (gdbarch, rs6000_store_struct_return);
- set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
- set_gdbarch_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
- set_gdbarch_pop_frame (gdbarch, rs6000_pop_frame);
+ set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
- set_gdbarch_decr_pc_after_break (gdbarch, 0);
- set_gdbarch_function_start_offset (gdbarch, 0);
set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
+ /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
+ for the descriptor and ".FN" for the entry-point -- a user
+ specifying "break FN" will unexpectedly end up with a breakpoint
+ on the descriptor and not the function. This architecture method
+ transforms any breakpoints on descriptors into breakpoints on the
+ corresponding entry point. */
+ if (sysv_abi && wordsize == 8)
+ set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
+
/* Not sure on this. FIXMEmgo */
set_gdbarch_frame_args_skip (gdbarch, 8);
- /* Until November 2001, gcc was not complying to the SYSV ABI for
- returning structures less than or equal to 8 bytes in size. It was
- returning everything in memory. When this was corrected, it wasn't
- fixed for native platforms. */
- if (sysv_abi)
+ if (!sysv_abi)
+ set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention);
+
+ if (!sysv_abi)
{
- if (osabi == ELFOSABI_LINUX
- || osabi == ELFOSABI_NETBSD
- || osabi == ELFOSABI_FREEBSD)
- set_gdbarch_use_struct_convention (gdbarch,
- generic_use_struct_convention);
- else
- set_gdbarch_use_struct_convention (gdbarch,
- ppc_sysv_abi_use_struct_convention);
+ /* Handle RS/6000 function pointers (which are really function
+ descriptors). */
+ set_gdbarch_convert_from_func_ptr_addr (gdbarch,
+ rs6000_convert_from_func_ptr_addr);
}
- else
+
+ /* Helpers for function argument information. */
+ set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
+
+ /* Hook in ABI-specific overrides, if they have been registered. */
+ gdbarch_init_osabi (info, gdbarch);
+
+ switch (info.osabi)
{
- set_gdbarch_use_struct_convention (gdbarch,
- generic_use_struct_convention);
+ case GDB_OSABI_NETBSD_AOUT:
+ case GDB_OSABI_NETBSD_ELF:
+ case GDB_OSABI_UNKNOWN:
+ case GDB_OSABI_LINUX:
+ set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
+ frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
+ set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
+ frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
+ break;
+ default:
+ set_gdbarch_believe_pcc_promotion (gdbarch, 1);
+
+ set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
+ frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
+ set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
+ frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
}
- set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
- /* Note: kevinb/2002-04-12: See note above regarding *_push_arguments().
- The same remarks hold for the methods below. */
- if (osabi == ELFOSABI_LINUX && wordsize == 4)
+ if (from_xcoff_exec)
{
- set_gdbarch_frameless_function_invocation (gdbarch,
- ppc_linux_frameless_function_invocation);
- set_gdbarch_frame_chain (gdbarch, ppc_linux_frame_chain);
- set_gdbarch_frame_saved_pc (gdbarch, ppc_linux_frame_saved_pc);
-
- set_gdbarch_frame_init_saved_regs (gdbarch,
- ppc_linux_frame_init_saved_regs);
- set_gdbarch_init_extra_frame_info (gdbarch,
- ppc_linux_init_extra_frame_info);
-
- set_gdbarch_memory_remove_breakpoint (gdbarch,
- ppc_linux_memory_remove_breakpoint);
- set_solib_svr4_fetch_link_map_offsets
- (gdbarch, ppc_linux_svr4_fetch_link_map_offsets);
+ /* NOTE: jimix/2003-06-09: This test should really check for
+ GDB_OSABI_AIX when that is defined and becomes
+ available. (Actually, once things are properly split apart,
+ the test goes away.) */
+ /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
+ set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
}
- else
- {
- set_gdbarch_frameless_function_invocation (gdbarch,
- rs6000_frameless_function_invocation);
- set_gdbarch_frame_chain (gdbarch, rs6000_frame_chain);
- set_gdbarch_frame_saved_pc (gdbarch, rs6000_frame_saved_pc);
- set_gdbarch_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs);
- set_gdbarch_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info);
+ init_sim_regno_table (gdbarch);
- /* Handle RS/6000 function pointers. */
- set_gdbarch_convert_from_func_ptr_addr (gdbarch,
- rs6000_convert_from_func_ptr_addr);
- }
- set_gdbarch_frame_args_address (gdbarch, rs6000_frame_args_address);
- set_gdbarch_frame_locals_address (gdbarch, rs6000_frame_args_address);
- set_gdbarch_saved_pc_after_call (gdbarch, rs6000_saved_pc_after_call);
+ return gdbarch;
+}
+
+static void
+rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
- /* We can't tell how many args there are
- now that the C compiler delays popping them. */
- set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
+ if (tdep == NULL)
+ return;
- return gdbarch;
+ /* FIXME: Dump gdbarch_tdep. */
}
static struct cmd_list_element *info_powerpc_cmdlist = NULL;
/* Initialization code. */
+extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
+
void
_initialize_rs6000_tdep (void)
{
- register_gdbarch_init (bfd_arch_rs6000, rs6000_gdbarch_init);
- register_gdbarch_init (bfd_arch_powerpc, rs6000_gdbarch_init);
+ gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
+ gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
/* Add root prefix command for "info powerpc" commands */
add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
- "Various POWERPC info specific commands.",
+ _("Various POWERPC info specific commands."),
&info_powerpc_cmdlist, "info powerpc ", 0, &infolist);
-
- add_cmd ("altivec", class_info, rs6000_altivec_registers_info,
- "Display the contents of the AltiVec registers.",
- &info_powerpc_cmdlist);
-
}
projects / deliverable / binutils-gdb.git / blobdiff