/* Target-dependent code for Renesas Super-H, for GDB.
Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
+ 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
This file is part of GDB.
/* sh flags */
#include "elf/sh.h"
-#include "elf/dwarf2.h"
+#include "dwarf2.h"
/* registers numbers shared with the simulator */
#include "gdb/sim-sh.h"
#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
-/* Disassemble an instruction. */
-static int
-gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
-{
- info->endian = gdbarch_byte_order (current_gdbarch);
- return print_insn_sh (memaddr, info);
-}
-
static CORE_ADDR
-sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
+sh_analyze_prologue (struct gdbarch *gdbarch,
+ CORE_ADDR pc, CORE_ADDR current_pc,
struct sh_frame_cache *cache, ULONGEST fpscr)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST inst;
CORE_ADDR opc;
int offset;
cache->uses_fp = 0;
for (opc = pc + (2 * 28); pc < opc; pc += 2)
{
- inst = read_memory_unsigned_integer (pc, 2);
+ inst = read_memory_unsigned_integer (pc, 2, byte_order);
/* See where the registers will be saved to */
if (IS_PUSH (inst))
{
sav_reg = reg;
offset = (inst & 0xff) << 1;
sav_offset =
- read_memory_integer ((pc + 4) + offset, 2);
+ read_memory_integer ((pc + 4) + offset, 2, byte_order);
}
}
}
sav_reg = reg;
offset = (inst & 0xff) << 2;
sav_offset =
- read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
+ read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
+ 4, byte_order);
}
}
}
sav_offset = GET_SOURCE_REG (inst) << 16;
/* MOVI20 is a 32 bit instruction! */
pc += 2;
- sav_offset |= read_memory_unsigned_integer (pc, 2);
+ sav_offset
+ |= read_memory_unsigned_integer (pc, 2, byte_order);
/* Now sav_offset contains an unsigned 20 bit value.
It must still get sign extended. */
if (sav_offset & 0x00080000)
pc += 2;
for (opc = pc + 12; pc < opc; pc += 2)
{
- inst = read_memory_integer (pc, 2);
+ inst = read_memory_integer (pc, 2, byte_order);
if (IS_MOV_ARG_TO_IND_R14 (inst))
{
reg = GET_SOURCE_REG (inst);
jsr, which will be very confusing. Most likely the next
instruction is going to be IS_MOV_SP_FP in the delay slot. If
so, note that before returning the current pc. */
- inst = read_memory_integer (pc + 2, 2);
+ inst = read_memory_integer (pc + 2, 2, byte_order);
if (IS_MOV_SP_FP (inst))
cache->uses_fp = 1;
break;
return max (pc, start_pc);
cache.sp_offset = -4;
- pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache, 0);
+ pc = sh_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, 0);
if (!cache.uses_fp)
return start_pc;
CORE_ADDR sp, int struct_return,
CORE_ADDR struct_addr)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int stack_offset = 0;
int argreg = ARG0_REGNUM;
int flt_argreg = 0;
{
/* Argument goes in a float argument register. */
reg_size = register_size (gdbarch, flt_argreg);
- regval = extract_unsigned_integer (val, reg_size);
+ regval = extract_unsigned_integer (val, reg_size, byte_order);
/* In little endian mode, float types taking two registers
(doubles on sh4, long doubles on sh2e, sh3e and sh4) must
be stored swapped in the argument registers. The below
regval);
val += reg_size;
len -= reg_size;
- regval = extract_unsigned_integer (val, reg_size);
+ regval = extract_unsigned_integer (val, reg_size, byte_order);
}
regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
}
{
/* there's room in a register */
reg_size = register_size (gdbarch, argreg);
- regval = extract_unsigned_integer (val, reg_size);
+ regval = extract_unsigned_integer (val, reg_size, byte_order);
regcache_cooked_write_unsigned (regcache, argreg++, regval);
}
/* Store the value one register at a time or in one step on stack. */
if (sh_is_renesas_calling_convention (func_type))
/* If the function uses the Renesas ABI, subtract another 4 bytes from
the stack and store the struct return address there. */
- write_memory_unsigned_integer (sp -= 4, 4, struct_addr);
+ write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
else
/* Using the gcc ABI, the "struct return pointer" pseudo-argument has
its own dedicated register. */
CORE_ADDR sp, int struct_return,
CORE_ADDR struct_addr)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int stack_offset = 0;
int argreg = ARG0_REGNUM;
int argnum;
{
/* there's room in a register */
reg_size = register_size (gdbarch, argreg);
- regval = extract_unsigned_integer (val, reg_size);
+ regval = extract_unsigned_integer (val, reg_size, byte_order);
regcache_cooked_write_unsigned (regcache, argreg++, regval);
}
/* Store the value reg_size bytes at a time. This means that things
if (sh_is_renesas_calling_convention (func_type))
/* If the function uses the Renesas ABI, subtract another 4 bytes from
the stack and store the struct return address there. */
- write_memory_unsigned_integer (sp -= 4, 4, struct_addr);
+ write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
else
/* Using the gcc ABI, the "struct return pointer" pseudo-argument has
its own dedicated register. */
sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
void *valbuf)
{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int len = TYPE_LENGTH (type);
int return_register = R0_REGNUM;
int offset;
ULONGEST c;
regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
- store_unsigned_integer (valbuf, len, c);
+ store_unsigned_integer (valbuf, len, byte_order, c);
}
else if (len == 8)
{
sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
const void *valbuf)
{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST val;
int len = TYPE_LENGTH (type);
if (len <= 4)
{
- val = extract_unsigned_integer (valbuf, len);
+ val = extract_unsigned_integer (valbuf, len, byte_order);
regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
}
else
{
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum
- (get_frame_arch (frame)))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum
+ (get_frame_arch (frame))), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
{
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum
- (get_frame_arch (frame)))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum
+ (get_frame_arch (frame))), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
struct gdbarch *gdbarch = get_frame_arch (frame);
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum (gdbarch))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum (gdbarch)), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum (gdbarch))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum (gdbarch)), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum
- (get_frame_arch (frame)))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum
+ (get_frame_arch (frame))), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
struct gdbarch *gdbarch = get_frame_arch (frame);
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum (gdbarch))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum (gdbarch)), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
{
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum
- (get_frame_arch (frame)))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum
+ (get_frame_arch (frame))), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum (gdbarch))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum (gdbarch)), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
{
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum
- (get_frame_arch (frame)))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum
+ (get_frame_arch (frame))), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
{
printf_filtered
(" PC %s SR %08lx PR %08lx MACH %08lx\n",
- paddr (get_frame_register_unsigned (frame,
- gdbarch_pc_regnum
- (get_frame_arch (frame)))),
+ phex (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum
+ (get_frame_arch (frame))), 4),
(long) get_frame_register_unsigned (frame, SR_REGNUM),
(long) get_frame_register_unsigned (frame, PR_REGNUM),
(long) get_frame_register_unsigned (frame, MACH_REGNUM));
{
if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
&& (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
- return builtin_type_float;
+ return builtin_type (gdbarch)->builtin_float;
else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
- return builtin_type_double;
+ return builtin_type (gdbarch)->builtin_double;
else
- return builtin_type_int;
+ return builtin_type (gdbarch)->builtin_int;
}
/* Return the GDB type object for the "standard" data type
{
if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
&& (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
- return builtin_type_float;
+ return builtin_type (gdbarch)->builtin_float;
else
- return builtin_type_int;
+ return builtin_type (gdbarch)->builtin_int;
}
static struct type *
-sh_sh4_build_float_register_type (int high)
+sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
{
- struct type *temp;
-
- temp = create_range_type (NULL, builtin_type_int, 0, high);
- return create_array_type (NULL, builtin_type_float, temp);
+ return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
+ 0, high);
}
static struct type *
{
if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
&& (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
- return builtin_type_float;
+ return builtin_type (gdbarch)->builtin_float;
else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
- return builtin_type_double;
+ return builtin_type (gdbarch)->builtin_double;
else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
- return sh_sh4_build_float_register_type (3);
+ return sh_sh4_build_float_register_type (gdbarch, 3);
else
- return builtin_type_int;
+ return builtin_type (gdbarch)->builtin_int;
}
static struct type *
sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
{
- return builtin_type_int;
+ return builtin_type (gdbarch)->builtin_int;
}
/* Is a register in a reggroup?
The default code in reggroup.c doesn't identify system registers, some
float registers or any of the vector registers.
TODO: sh2a and dsp registers. */
-int
+static int
sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *reggroup)
{
static struct sh_frame_cache *
sh_frame_cache (struct frame_info *this_frame, void **this_cache)
{
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct sh_frame_cache *cache;
CORE_ADDR current_pc;
int i;
{
ULONGEST fpscr;
fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
- sh_analyze_prologue (cache->pc, current_pc, cache, fpscr);
+ sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
}
if (!cache->uses_fp)
frame by looking at the stack pointer. For truly "frameless"
functions this might work too. */
cache->base = get_frame_register_unsigned
- (this_frame,
- gdbarch_sp_regnum (get_frame_arch (this_frame)));
+ (this_frame, gdbarch_sp_regnum (gdbarch));
}
/* Now that we have the base address for the stack frame we can
static int
sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR func_addr = 0, func_end = 0;
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
/* First search forward until hitting an rts. */
while (addr < func_end
- && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
+ && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
addr += 2;
if (addr >= func_end)
return 0;
/* At this point we should find a mov.l @r15+,r14 instruction,
either before or after the rts. If not, then the function has
probably no "normal" epilogue and we bail out here. */
- inst = read_memory_unsigned_integer (addr - 2, 2);
- if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
+ inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
+ if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
+ byte_order)))
addr -= 2;
- else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
+ else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
+ byte_order)))
return 0;
- inst = read_memory_unsigned_integer (addr - 2, 2);
+ inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
/* Step over possible lds.l @r15+,macl. */
if (IS_MACL_LDS (inst))
{
addr -= 2;
- inst = read_memory_unsigned_integer (addr - 2, 2);
+ inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
}
/* Step over possible lds.l @r15+,pr. */
if (IS_LDS (inst))
{
addr -= 2;
- inst = read_memory_unsigned_integer (addr - 2, 2);
+ inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
}
/* Step over possible mov r14,r15. */
if (IS_MOV_FP_SP (inst))
{
addr -= 2;
- inst = read_memory_unsigned_integer (addr - 2, 2);
+ inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
}
/* Now check for FP adjustments, using add #imm,r14 or add rX, r14
&& (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
{
addr -= 2;
- inst = read_memory_unsigned_integer (addr - 2, 2);
+ inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
}
/* On SH2a check if the previous instruction was perhaps a MOVI20.
if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
|| gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
&& addr > func_addr + 6
- && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
+ && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
+ byte_order)))
addr -= 4;
if (pc >= addr)
break;
case bfd_mach_sh3:
+ case bfd_mach_sh3_nommu:
+ case bfd_mach_sh2a_nofpu_or_sh3_nommu:
sh_show_regs = sh3_show_regs;
break;
case bfd_mach_sh3e:
+ case bfd_mach_sh2a_or_sh3e:
sh_show_regs = sh3e_show_regs;
break;
case bfd_mach_sh4:
case bfd_mach_sh4a:
+ case bfd_mach_sh2a_or_sh4:
sh_show_regs = sh4_show_regs;
break;
case bfd_mach_sh4_nofpu:
+ case bfd_mach_sh4_nommu_nofpu:
case bfd_mach_sh4a_nofpu:
+ case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
sh_show_regs = sh4_nofpu_show_regs;
break;
set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
- set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
+ set_gdbarch_print_insn (gdbarch, print_insn_sh);
set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
case bfd_mach_sh4:
case bfd_mach_sh4a:
+ case bfd_mach_sh2a_or_sh4:
set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
set_gdbarch_fp0_regnum (gdbarch, 25);
case bfd_mach_sh4a_nofpu:
case bfd_mach_sh4_nommu_nofpu:
case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
- case bfd_mach_sh2a_or_sh4:
set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
break;
projects / deliverable / binutils-gdb.git / blobdiff