/* Target-dependent code for the SPARC for GDB, the GNU debugger.
- Copyright 1986, 1987, 1989, 1991, 1992 Free Software Foundation, Inc.
+ Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
+ Free Software Foundation, Inc.
This file is part of GDB.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
-Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Support for calling functions from gdb in sparc64 is unfinished. */
#include "defs.h"
#include "frame.h"
#include "inferior.h"
#include "obstack.h"
#include "target.h"
-#include "ieee-float.h"
+#include "value.h"
#ifdef USE_PROC_FS
#include <sys/procfs.h>
-#else
-#include <sys/ptrace.h>
#endif
#include "gdbcore.h"
+#ifdef GDB_TARGET_IS_SPARC64
+#define NUM_SPARC_FPREGS 64
+#else
+#define NUM_SPARC_FPREGS 32
+#endif
+
+#define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
+
/* From infrun.c */
extern int stop_after_trap;
+/* We don't store all registers immediately when requested, since they
+ get sent over in large chunks anyway. Instead, we accumulate most
+ of the changes and send them over once. "deferred_stores" keeps
+ track of which sets of registers we have locally-changed copies of,
+ so we only need send the groups that have changed. */
+
+int deferred_stores = 0; /* Cumulates stores we want to do eventually. */
+
+/* Branches with prediction are treated like their non-predicting cousins. */
+/* FIXME: What about floating point branches? */
+
+/* Macros to extract fields from sparc instructions. */
+#define X_OP(i) (((i) >> 30) & 0x3)
+#define X_RD(i) (((i) >> 25) & 0x1f)
+#define X_A(i) (((i) >> 29) & 1)
+#define X_COND(i) (((i) >> 25) & 0xf)
+#define X_OP2(i) (((i) >> 22) & 0x7)
+#define X_IMM22(i) ((i) & 0x3fffff)
+#define X_OP3(i) (((i) >> 19) & 0x3f)
+#define X_RS1(i) (((i) >> 14) & 0x1f)
+#define X_I(i) (((i) >> 13) & 1)
+#define X_IMM13(i) ((i) & 0x1fff)
+/* Sign extension macros. */
+#define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
+#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
+#ifdef GDB_TARGET_IS_SPARC64
+#define X_CC(i) (((i) >> 20) & 3)
+#define X_P(i) (((i) >> 19) & 1)
+#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
+#define X_RCOND(i) (((i) >> 25) & 7)
+#define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
+#define X_FCN(i) (((i) >> 25) & 31)
+#endif
+
typedef enum
{
- Error, not_branch, bicc, bicca, ba, baa, ticc, ta
+ Error, not_branch, bicc, bicca, ba, baa, ticc, ta,
+#ifdef GDB_TARGET_IS_SPARC64
+ done_retry
+#endif
} branch_type;
/* Simulate single-step ptrace call for sun4. Code written by Gary
single_step (ignore)
int ignore; /* pid, but we don't need it */
{
- branch_type br, isannulled();
+ branch_type br, isbranch();
CORE_ADDR pc;
long pc_instruction;
npc4 = next_pc + 4; /* branch not taken */
target_insert_breakpoint (next_pc, break_mem[0]);
- /* printf ("set break at %x\n",next_pc); */
+ /* printf_unfiltered ("set break at %x\n",next_pc); */
pc = read_register (PC_REGNUM);
- pc_instruction = read_memory_integer (pc, sizeof(pc_instruction));
- br = isannulled (pc_instruction, pc, &target);
+ pc_instruction = read_memory_integer (pc, 4);
+ br = isbranch (pc_instruction, pc, &target);
brknpc4 = brktrg = 0;
if (br == bicca)
brktrg = 1;
target_insert_breakpoint (target, break_mem[2]);
}
+#ifdef GDB_TARGET_IS_SPARC64
+ else if (br == done_retry)
+ {
+ brktrg = 1;
+ target_insert_breakpoint (target, break_mem[2]);
+ }
+#endif
/* We are ready to let it go */
one_stepped = 1;
}
}
\f
-#define FRAME_SAVED_L0 0 /* Byte offset from SP */
-#define FRAME_SAVED_I0 32 /* Byte offset from SP */
+/* Call this for each newly created frame. For SPARC, we need to calculate
+ the bottom of the frame, and do some extra work if the prologue
+ has been generated via the -mflat option to GCC. In particular,
+ we need to know where the previous fp and the pc have been stashed,
+ since their exact position within the frame may vary. */
-CORE_ADDR
-sparc_frame_chain (thisframe)
- FRAME thisframe;
+void
+sparc_init_extra_frame_info (fromleaf, fi)
+ int fromleaf;
+ struct frame_info *fi;
{
- CORE_ADDR retval;
- int err;
+ char *name;
CORE_ADDR addr;
+ int insn;
- addr = thisframe->frame + FRAME_SAVED_I0 +
- REGISTER_RAW_SIZE(FP_REGNUM) * (FP_REGNUM - I0_REGNUM);
- err = target_read_memory (addr, (char *) &retval, sizeof (CORE_ADDR));
- if (err)
- return 0;
- SWAP_TARGET_AND_HOST (&retval, sizeof (retval));
- return retval;
+ fi->bottom =
+ (fi->next ?
+ (fi->frame == fi->next->frame ? fi->next->bottom : fi->next->frame) :
+ read_register (SP_REGNUM));
+
+ /* If fi->next is NULL, then we already set ->frame by passing read_fp()
+ to create_new_frame. */
+ if (fi->next)
+ {
+ char buf[MAX_REGISTER_RAW_SIZE];
+ int err;
+
+ /* Compute ->frame as if not flat. If it is flat, we'll change
+ it later. */
+ /* FIXME: If error reading memory, should just stop backtracing, rather
+ than error(). */
+ get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0);
+ fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM));
+ }
+
+ /* Decide whether this is a function with a ``flat register window''
+ frame. For such functions, the frame pointer is actually in %i7. */
+ fi->flat = 0;
+ if (find_pc_partial_function (fi->pc, &name, &addr, NULL))
+ {
+ /* See if the function starts with an add (which will be of a
+ negative number if a flat frame) to the sp. FIXME: Does not
+ handle large frames which will need more than one instruction
+ to adjust the sp. */
+ insn = read_memory_integer (addr, 4);
+ if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0
+ && X_I (insn) && X_SIMM13 (insn) < 0)
+ {
+ int offset = X_SIMM13 (insn);
+
+ /* Then look for a save of %i7 into the frame. */
+ insn = read_memory_integer (addr + 4, 4);
+ if (X_OP (insn) == 3
+ && X_RD (insn) == 31
+ && X_OP3 (insn) == 4
+ && X_RS1 (insn) == 14)
+ {
+ char buf[MAX_REGISTER_RAW_SIZE];
+
+ /* We definitely have a flat frame now. */
+ fi->flat = 1;
+
+ fi->sp_offset = offset;
+
+ /* Overwrite the frame's address with the value in %i7. */
+ get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0);
+ fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM));
+
+ /* Record where the fp got saved. */
+ fi->fp_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn);
+
+ /* Also try to collect where the pc got saved to. */
+ fi->pc_addr = 0;
+ insn = read_memory_integer (addr + 12, 4);
+ if (X_OP (insn) == 3
+ && X_RD (insn) == 15
+ && X_OP3 (insn) == 4
+ && X_RS1 (insn) == 14)
+ fi->pc_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn);
+ }
+ }
+ }
+ if (fi->next && fi->frame == 0)
+ {
+ /* Kludge to cause init_prev_frame_info to destroy the new frame. */
+ fi->frame = fi->next->frame;
+ fi->pc = fi->next->pc;
+ }
+}
+
+CORE_ADDR
+sparc_frame_chain (frame)
+ struct frame_info *frame;
+{
+ /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
+ value. If it realy is zero, we detect it later in
+ sparc_init_prev_frame. */
+ return (CORE_ADDR)1;
}
CORE_ADDR
sparc_extract_struct_value_address (regbuf)
char regbuf[REGISTER_BYTES];
{
- /* FIXME, handle byte swapping */
- return read_memory_integer (((int *)(regbuf))[SP_REGNUM]+(16*4),
- sizeof (CORE_ADDR));
+#ifdef GDB_TARGET_IS_SPARC64
+ return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM),
+ REGISTER_RAW_SIZE (O0_REGNUM));
+#else
+ return read_memory_integer (((int *)(regbuf)) [SP_REGNUM] + (16 * SPARC_INTREG_SIZE),
+ TARGET_PTR_BIT / TARGET_CHAR_BIT);
+#endif
}
/* Find the pc saved in frame FRAME. */
CORE_ADDR
-frame_saved_pc (frame)
- FRAME frame;
+sparc_frame_saved_pc (frame)
+ struct frame_info *frame;
{
- CORE_ADDR prev_pc;
+ char buf[MAX_REGISTER_RAW_SIZE];
+ CORE_ADDR addr;
- if (get_current_frame () == frame) /* FIXME, debug check. Remove >=gdb-4.6 */
+ if (frame->signal_handler_caller)
{
- if (read_register (SP_REGNUM) != frame->bottom) abort();
- }
-
- read_memory ((CORE_ADDR) (frame->bottom + FRAME_SAVED_I0 +
- REGISTER_RAW_SIZE(I7_REGNUM) * (I7_REGNUM - I0_REGNUM)),
- (char *) &prev_pc,
- sizeof (CORE_ADDR));
+ /* This is the signal trampoline frame.
+ Get the saved PC from the sigcontext structure. */
- SWAP_TARGET_AND_HOST (&prev_pc, sizeof (prev_pc));
- return PC_ADJUST (prev_pc);
-}
-
-/*
- * Since an individual frame in the frame cache is defined by two
- * arguments (a frame pointer and a stack pointer), we need two
- * arguments to get info for an arbitrary stack frame. This routine
- * takes two arguments and makes the cached frames look as if these
- * two arguments defined a frame on the cache. This allows the rest
- * of info frame to extract the important arguments without
- * difficulty.
- */
-FRAME
-setup_arbitrary_frame (frame, stack)
- FRAME_ADDR frame, stack;
-{
- FRAME fid = create_new_frame (frame, 0);
-
- if (!fid)
- fatal ("internal: create_new_frame returned invalid frame id");
-
- fid->bottom = stack;
- fid->pc = FRAME_SAVED_PC (fid);
- return fid;
-}
+#ifndef SIGCONTEXT_PC_OFFSET
+#define SIGCONTEXT_PC_OFFSET 12
+#endif
-/* This code was written by Gary Beihl (beihl@mcc.com).
- It was modified by Michael Tiemann (tiemann@corto.inria.fr). */
-
-/*
- * This routine appears to be passed a size by which to increase the
- * stack. It then executes a save instruction in the inferior to
- * increase the stack by this amount. Only the register window system
- * should be affected by this; the program counter & etc. will not be.
- *
- * This instructions used for this purpose are:
- *
- * sethi %hi(0x0),g1 *
- * add g1,0x1ee0,g1 *
- * save sp,g1,sp
- * sethi %hi(0x0),g1 *
- * add g1,0x1ee0,g1 *
- * t g0,0x1,o0
- * sethi %hi(0x0),g0 (nop)
- *
- * I presume that these set g1 to be the negative of the size, do a
- * save (putting the stack pointer at sp - size) and restore the
- * original contents of g1. A * indicates that the actual value of
- * the instruction is modified below.
- */
-static int save_insn_opcodes[] = {
- 0x03000000, 0x82007ee0, 0x9de38001, 0x03000000,
- 0x82007ee0, 0x91d02001, 0x01000000 };
+ CORE_ADDR sigcontext_addr;
+ char scbuf[TARGET_PTR_BIT / HOST_CHAR_BIT];
+ int saved_pc_offset = SIGCONTEXT_PC_OFFSET;
+ char *name = NULL;
+
+ /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
+ as the third parameter. The offset to the saved pc is 12. */
+ find_pc_partial_function (frame->pc, &name,
+ (CORE_ADDR *)NULL,(CORE_ADDR *)NULL);
+ if (name && STREQ (name, "ucbsigvechandler"))
+ saved_pc_offset = 12;
+
+ /* The sigcontext address is contained in register O2. */
+ get_saved_register (buf, (int *)NULL, (CORE_ADDR *)NULL,
+ frame, O0_REGNUM + 2, (enum lval_type *)NULL);
+ sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM + 2));
+
+ /* Don't cause a memory_error when accessing sigcontext in case the
+ stack layout has changed or the stack is corrupt. */
+ target_read_memory (sigcontext_addr + saved_pc_offset,
+ scbuf, sizeof (scbuf));
+ return extract_address (scbuf, sizeof (scbuf));
+ }
+ if (frame->flat)
+ addr = frame->pc_addr;
+ else
+ addr = frame->bottom + FRAME_SAVED_I0 +
+ SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM);
-/* Neither do_save_insn or do_restore_insn save stack configuration
- (current_frame, etc),
- since the stack is in an indeterminate state through the call to
- each of them. That responsibility of the routine which calls them. */
+ if (addr == 0)
+ /* A flat frame leaf function might not save the PC anywhere,
+ just leave it in %o7. */
+ return PC_ADJUST (read_register (O7_REGNUM));
-static void
-do_save_insn (size)
- int size;
-{
- int g1 = read_register (G1_REGNUM);
- CORE_ADDR sp = read_register (SP_REGNUM);
- CORE_ADDR pc = read_register (PC_REGNUM);
- CORE_ADDR npc = read_register (NPC_REGNUM);
- CORE_ADDR fake_pc = sp - sizeof (save_insn_opcodes);
- struct inferior_status inf_status;
-
- save_inferior_status (&inf_status, 0); /* Don't restore stack info */
- /*
- * See above.
- */
- save_insn_opcodes[0] = 0x03000000 | ((-size >> 10) & 0x3fffff);
- save_insn_opcodes[1] = 0x82006000 | (-size & 0x3ff);
- save_insn_opcodes[3] = 0x03000000 | ((g1 >> 10) & 0x3fffff);
- save_insn_opcodes[4] = 0x82006000 | (g1 & 0x3ff);
- write_memory (fake_pc, (char *)save_insn_opcodes, sizeof (save_insn_opcodes));
-
- clear_proceed_status ();
- stop_after_trap = 1;
- proceed (fake_pc, 0, 0);
-
- write_register (PC_REGNUM, pc);
- write_register (NPC_REGNUM, npc);
- restore_inferior_status (&inf_status);
+ read_memory (addr, buf, SPARC_INTREG_SIZE);
+ return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE));
}
-/*
- * This routine takes a program counter value. It restores the
- * register window system to the frame above the current one.
- * THIS ROUTINE CLOBBERS PC AND NPC IN THE TARGET!
- */
-
-/* The following insns translate to:
-
- restore %g0,%g0,%g0
- t %g0,1
- sethi %hi(0),%g0 */
-
-static int restore_insn_opcodes[] = { 0x81e80000, 0x91d02001, 0x01000000 };
-
-static void
-do_restore_insn ()
+/* Since an individual frame in the frame cache is defined by two
+ arguments (a frame pointer and a stack pointer), we need two
+ arguments to get info for an arbitrary stack frame. This routine
+ takes two arguments and makes the cached frames look as if these
+ two arguments defined a frame on the cache. This allows the rest
+ of info frame to extract the important arguments without
+ difficulty. */
+
+struct frame_info *
+setup_arbitrary_frame (argc, argv)
+ int argc;
+ CORE_ADDR *argv;
{
- CORE_ADDR sp = read_register (SP_REGNUM);
- CORE_ADDR fake_pc = sp - sizeof (restore_insn_opcodes);
- struct inferior_status inf_status;
-
- save_inferior_status (&inf_status, 0); /* Don't restore stack info */
+ struct frame_info *frame;
- write_memory (fake_pc, (char *)restore_insn_opcodes,
- sizeof (restore_insn_opcodes));
+ if (argc != 2)
+ error ("Sparc frame specifications require two arguments: fp and sp");
- clear_proceed_status ();
- stop_after_trap = 1;
- proceed (fake_pc, 0, 0);
+ frame = create_new_frame (argv[0], 0);
- restore_inferior_status (&inf_status);
+ if (!frame)
+ fatal ("internal: create_new_frame returned invalid frame");
+
+ frame->bottom = argv[1];
+ frame->pc = FRAME_SAVED_PC (frame);
+ return frame;
}
/* Given a pc value, skip it forward past the function prologue by
This routine should be more specific in its actions; making sure
that it uses the same register in the initial prologue section. */
-CORE_ADDR
-skip_prologue (start_pc, frameless_p)
+
+static CORE_ADDR examine_prologue PARAMS ((CORE_ADDR, int, struct frame_info *,
+ struct frame_saved_regs *));
+
+static CORE_ADDR
+examine_prologue (start_pc, frameless_p, fi, saved_regs)
CORE_ADDR start_pc;
int frameless_p;
+ struct frame_info *fi;
+ struct frame_saved_regs *saved_regs;
{
- union
- {
- unsigned long int code;
- struct
- {
- unsigned int op:2;
- unsigned int rd:5;
- unsigned int op2:3;
- unsigned int imm22:22;
- } sethi;
- struct
- {
- unsigned int op:2;
- unsigned int rd:5;
- unsigned int op3:6;
- unsigned int rs1:5;
- unsigned int i:1;
- unsigned int simm13:13;
- } add;
- int i;
- } x;
+ int insn;
int dest = -1;
CORE_ADDR pc = start_pc;
+ int is_flat = 0;
- x.i = read_memory_integer (pc, 4);
+ insn = read_memory_integer (pc, 4);
/* Recognize the `sethi' insn and record its destination. */
- if (x.sethi.op == 0 && x.sethi.op2 == 4)
+ if (X_OP (insn) == 0 && X_OP2 (insn) == 4)
{
- dest = x.sethi.rd;
+ dest = X_RD (insn);
pc += 4;
- x.i = read_memory_integer (pc, 4);
+ insn = read_memory_integer (pc, 4);
}
/* Recognize an add immediate value to register to either %g1 or
It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
followed by "save %sp, %g1, %sp" is a valid prologue (Not that
I imagine any compiler really does that, however). */
- if (x.add.op == 2 && x.add.i && (x.add.rd == 1 || x.add.rd == dest))
+ if (X_OP (insn) == 2
+ && X_I (insn)
+ && (X_RD (insn) == 1 || X_RD (insn) == dest))
{
pc += 4;
- x.i = read_memory_integer (pc, 4);
+ insn = read_memory_integer (pc, 4);
}
- /* This recognizes any SAVE insn. But why do the XOR and then
- the compare? That's identical to comparing against 60 (as long
- as there isn't any sign extension). */
- if (x.add.op == 2 && (x.add.op3 ^ 32) == 28)
+ /* Recognize any SAVE insn. */
+ if (X_OP (insn) == 2 && X_OP3 (insn) == 60)
{
pc += 4;
if (frameless_p) /* If the save is all we care about, */
return pc; /* return before doing more work */
- x.i = read_memory_integer (pc, 4);
+ insn = read_memory_integer (pc, 4);
}
- else
+ /* Recognize add to %sp. */
+ else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0)
{
- /* Without a save instruction, it's not a prologue. */
- return start_pc;
+ pc += 4;
+ if (frameless_p) /* If the add is all we care about, */
+ return pc; /* return before doing more work */
+ is_flat = 1;
+ insn = read_memory_integer (pc, 4);
+ /* Recognize store of frame pointer (i7). */
+ if (X_OP (insn) == 3
+ && X_RD (insn) == 31
+ && X_OP3 (insn) == 4
+ && X_RS1 (insn) == 14)
+ {
+ pc += 4;
+ insn = read_memory_integer (pc, 4);
+
+ /* Recognize sub %sp, <anything>, %i7. */
+ if (X_OP (insn) == 2
+ && X_OP3 (insn) == 4
+ && X_RS1 (insn) == 14
+ && X_RD (insn) == 31)
+ {
+ pc += 4;
+ insn = read_memory_integer (pc, 4);
+ }
+ else
+ return pc;
+ }
+ else
+ return pc;
}
+ else
+ /* Without a save or add instruction, it's not a prologue. */
+ return start_pc;
- /* Now we need to recognize stores into the frame from the input
- registers. This recognizes all non alternate stores of input
- register, into a location offset from the frame pointer. */
- while (x.add.op == 3
- && (x.add.op3 & 0x3c) == 4 /* Store, non-alternate. */
- && (x.add.rd & 0x18) == 0x18 /* Input register. */
- && x.add.i /* Immediate mode. */
- && x.add.rs1 == 30 /* Off of frame pointer. */
- /* Into reserved stack space. */
- && x.add.simm13 >= 0x44
- && x.add.simm13 < 0x5b)
+ while (1)
{
+ /* Recognize stores into the frame from the input registers.
+ This recognizes all non alternate stores of input register,
+ into a location offset from the frame pointer. */
+ if ((X_OP (insn) == 3
+ && (X_OP3 (insn) & 0x3c) == 4 /* Store, non-alternate. */
+ && (X_RD (insn) & 0x18) == 0x18 /* Input register. */
+ && X_I (insn) /* Immediate mode. */
+ && X_RS1 (insn) == 30 /* Off of frame pointer. */
+ /* Into reserved stack space. */
+ && X_SIMM13 (insn) >= 0x44
+ && X_SIMM13 (insn) < 0x5b))
+ ;
+ else if (is_flat
+ && X_OP (insn) == 3
+ && X_OP3 (insn) == 4
+ && X_RS1 (insn) == 14
+ )
+ {
+ if (saved_regs && X_I (insn))
+ saved_regs->regs[X_RD (insn)] =
+ fi->frame + fi->sp_offset + X_SIMM13 (insn);
+ }
+ else
+ break;
pc += 4;
- x.i = read_memory_integer (pc, 4);
+ insn = read_memory_integer (pc, 4);
}
+
return pc;
}
-/* Check instruction at ADDR to see if it is an annulled branch.
- All other instructions will go to NPC or will trap.
- Set *TARGET if we find a canidate branch; set to zero if not. */
-
+CORE_ADDR
+skip_prologue (start_pc, frameless_p)
+ CORE_ADDR start_pc;
+ int frameless_p;
+{
+ return examine_prologue (start_pc, frameless_p, NULL, NULL);
+}
+
+/* Check instruction at ADDR to see if it is a branch.
+ All non-annulled instructions will go to NPC or will trap.
+ Set *TARGET if we find a candidate branch; set to zero if not.
+
+ This isn't static as it's used by remote-sa.sparc.c. */
+
branch_type
-isannulled (instruction, addr, target)
+isbranch (instruction, addr, target)
long instruction;
CORE_ADDR addr, *target;
{
branch_type val = not_branch;
long int offset; /* Must be signed for sign-extend. */
- union
- {
- unsigned long int code;
- struct
- {
- unsigned int op:2;
- unsigned int a:1;
- unsigned int cond:4;
- unsigned int op2:3;
- unsigned int disp22:22;
- } b;
- } insn;
*target = 0;
- insn.code = instruction;
- if (insn.b.op == 0
- && (insn.b.op2 == 2 || insn.b.op2 == 6 || insn.b.op2 == 7))
+ if (X_OP (instruction) == 0
+ && (X_OP2 (instruction) == 2
+ || X_OP2 (instruction) == 6
+#ifdef GDB_TARGET_IS_SPARC64
+ || X_OP2 (instruction) == 1
+ || X_OP2 (instruction) == 3
+ || X_OP2 (instruction) == 5
+#else
+ || X_OP2 (instruction) == 7
+#endif
+ ))
{
- if (insn.b.cond == 8)
- val = insn.b.a ? baa : ba;
+ if (X_COND (instruction) == 8)
+ val = X_A (instruction) ? baa : ba;
else
- val = insn.b.a ? bicca : bicc;
- offset = 4 * ((int) (insn.b.disp22 << 10) >> 10);
+ val = X_A (instruction) ? bicca : bicc;
+ switch (X_OP2 (instruction))
+ {
+ case 2:
+ case 6:
+#ifndef GDB_TARGET_IS_SPARC64
+ case 7:
+#endif
+ offset = 4 * X_DISP22 (instruction);
+ break;
+#ifdef GDB_TARGET_IS_SPARC64
+ case 1:
+ case 5:
+ offset = 4 * X_DISP19 (instruction);
+ break;
+ case 3:
+ offset = 4 * X_DISP16 (instruction);
+ break;
+#endif
+ }
*target = addr + offset;
}
+#ifdef GDB_TARGET_IS_SPARC64
+ else if (X_OP (instruction) == 2
+ && X_OP3 (instruction) == 62)
+ {
+ if (X_FCN (instruction) == 0)
+ {
+ /* done */
+ *target = read_register (TNPC_REGNUM);
+ val = done_retry;
+ }
+ else if (X_FCN (instruction) == 1)
+ {
+ /* retry */
+ *target = read_register (TPC_REGNUM);
+ val = done_retry;
+ }
+ }
+#endif
return val;
}
+\f
+/* Find register number REGNUM relative to FRAME and put its
+ (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
+ was optimized out (and thus can't be fetched). If the variable
+ was fetched from memory, set *ADDRP to where it was fetched from,
+ otherwise it was fetched from a register.
+
+ The argument RAW_BUFFER must point to aligned memory. */
-/* sparc_frame_find_saved_regs ()
+void
+get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
+ char *raw_buffer;
+ int *optimized;
+ CORE_ADDR *addrp;
+ struct frame_info *frame;
+ int regnum;
+ enum lval_type *lval;
+{
+ struct frame_info *frame1;
+ CORE_ADDR addr;
+
+ if (!target_has_registers)
+ error ("No registers.");
+
+ if (optimized)
+ *optimized = 0;
+
+ addr = 0;
+ frame1 = frame->next;
+ while (frame1 != NULL)
+ {
+ if (frame1->pc >= (frame1->bottom ? frame1->bottom :
+ read_register (SP_REGNUM))
+ && frame1->pc <= FRAME_FP (frame1))
+ {
+ /* Dummy frame. All but the window regs are in there somewhere. */
+ /* FIXME: The offsets are wrong for sparc64 (eg: 0xa0). */
+ if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7)
+ addr = frame1->frame + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE
+ - (NUM_SPARC_FPREGS * 4 + 8 * SPARC_INTREG_SIZE);
+ else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8)
+ addr = frame1->frame + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
+ - (NUM_SPARC_FPREGS * 4 + 16 * SPARC_INTREG_SIZE);
+ else if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM + NUM_SPARC_FPREGS)
+ addr = frame1->frame + (regnum - FP0_REGNUM) * 4
+ - (NUM_SPARC_FPREGS * 4);
+ else if (regnum >= Y_REGNUM && regnum < NUM_REGS)
+ addr = frame1->frame + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE
+ - (NUM_SPARC_FPREGS * 4 + 24 * SPARC_INTREG_SIZE);
+ }
+ else if (frame1->flat)
+ {
+
+ if (regnum == RP_REGNUM)
+ addr = frame1->pc_addr;
+ else if (regnum == I7_REGNUM)
+ addr = frame1->fp_addr;
+ else
+ {
+ CORE_ADDR func_start;
+ struct frame_saved_regs regs;
+ memset (®s, 0, sizeof (regs));
+
+ find_pc_partial_function (frame1->pc, NULL, &func_start, NULL);
+ examine_prologue (func_start, 0, frame1, ®s);
+ addr = regs.regs[regnum];
+ }
+ }
+ else
+ {
+ /* Normal frame. Local and In registers are saved on stack. */
+ if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8)
+ addr = (frame1->prev->bottom
+ + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
+ + FRAME_SAVED_I0);
+ else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8)
+ addr = (frame1->prev->bottom
+ + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE
+ + FRAME_SAVED_L0);
+ else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8)
+ {
+ /* Outs become ins. */
+ get_saved_register (raw_buffer, optimized, addrp, frame1,
+ (regnum - O0_REGNUM + I0_REGNUM), lval);
+ return;
+ }
+ }
+ if (addr != 0)
+ break;
+ frame1 = frame1->next;
+ }
+ if (addr != 0)
+ {
+ if (lval != NULL)
+ *lval = lval_memory;
+ if (regnum == SP_REGNUM)
+ {
+ if (raw_buffer != NULL)
+ {
+ /* Put it back in target format. */
+ store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), addr);
+ }
+ if (addrp != NULL)
+ *addrp = 0;
+ return;
+ }
+ if (raw_buffer != NULL)
+ read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum));
+ }
+ else
+ {
+ if (lval != NULL)
+ *lval = lval_register;
+ addr = REGISTER_BYTE (regnum);
+ if (raw_buffer != NULL)
+ read_register_gen (regnum, raw_buffer);
+ }
+ if (addrp != NULL)
+ *addrp = addr;
+}
+
+/* Push an empty stack frame, and record in it the current PC, regs, etc.
+
+ We save the non-windowed registers and the ins. The locals and outs
+ are new; they don't need to be saved. The i's and l's of
+ the last frame were already saved on the stack. */
+
+/* Definitely see tm-sparc.h for more doc of the frame format here. */
+
+#ifdef GDB_TARGET_IS_SPARC64
+#define DUMMY_REG_SAVE_OFFSET (128 + 16)
+#else
+#define DUMMY_REG_SAVE_OFFSET 0x60
+#endif
+
+/* See tm-sparc.h for how this is calculated. */
+#define DUMMY_STACK_REG_BUF_SIZE \
+(((8+8+8) * SPARC_INTREG_SIZE) + (32 * REGISTER_RAW_SIZE (FP0_REGNUM)))
+#define DUMMY_STACK_SIZE (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
+
+void
+sparc_push_dummy_frame ()
+{
+ CORE_ADDR sp, old_sp;
+ char register_temp[DUMMY_STACK_SIZE];
+
+ old_sp = sp = read_register (SP_REGNUM);
+
+#ifdef GDB_TARGET_IS_SPARC64
+ /* FIXME: not sure what needs to be saved here. */
+#else
+ /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
+ read_register_bytes (REGISTER_BYTE (Y_REGNUM), ®ister_temp[0],
+ REGISTER_RAW_SIZE (Y_REGNUM) * 8);
+#endif
+
+ read_register_bytes (REGISTER_BYTE (O0_REGNUM),
+ ®ister_temp[8 * SPARC_INTREG_SIZE],
+ SPARC_INTREG_SIZE * 8);
+
+ read_register_bytes (REGISTER_BYTE (G0_REGNUM),
+ ®ister_temp[16 * SPARC_INTREG_SIZE],
+ SPARC_INTREG_SIZE * 8);
+
+ /* ??? The 32 here should be NUM_SPARC_FPREGS, but until we decide what
+ REGISTER_RAW_SIZE should be for fp regs, it's left as is. */
+ read_register_bytes (REGISTER_BYTE (FP0_REGNUM),
+ ®ister_temp[24 * SPARC_INTREG_SIZE],
+ REGISTER_RAW_SIZE (FP0_REGNUM) * 32);
+
+ sp -= DUMMY_STACK_SIZE;
+
+ write_register (SP_REGNUM, sp);
+
+ write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0],
+ DUMMY_STACK_REG_BUF_SIZE);
+
+ write_register (FP_REGNUM, old_sp);
+
+ /* Set return address register for the call dummy to the current PC. */
+ write_register (I7_REGNUM, read_pc() - 8);
+}
+
+/* sparc_frame_find_saved_regs (). This function is here only because
+ pop_frame uses it. Note there is an interesting corner case which
+ I think few ports of GDB get right--if you are popping a frame
+ which does not save some register that *is* saved by a more inner
+ frame (such a frame will never be a dummy frame because dummy
+ frames save all registers). Rewriting pop_frame to use
+ get_saved_register would solve this problem and also get rid of the
+ ugly duplication between sparc_frame_find_saved_regs and
+ get_saved_register.
Stores, into a struct frame_saved_regs,
the addresses of the saved registers of frame described by FRAME_INFO.
See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information
about how this works. */
-void
+static void sparc_frame_find_saved_regs PARAMS ((struct frame_info *,
+ struct frame_saved_regs *));
+
+static void
sparc_frame_find_saved_regs (fi, saved_regs_addr)
struct frame_info *fi;
struct frame_saved_regs *saved_regs_addr;
{
register int regnum;
- FRAME_ADDR frame = read_register (FP_REGNUM);
- FRAME fid = FRAME_INFO_ID (fi);
+ CORE_ADDR frame_addr = FRAME_FP (fi);
- if (!fid)
+ if (!fi)
fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS");
- (void) memset (saved_regs_addr, 0, sizeof (*saved_regs_addr));
-
- /* Old test.
- if (fi->pc >= frame - CALL_DUMMY_LENGTH - 0x140
- && fi->pc <= frame) */
+ memset (saved_regs_addr, 0, sizeof (*saved_regs_addr));
if (fi->pc >= (fi->bottom ? fi->bottom :
read_register (SP_REGNUM))
/* Dummy frame. All but the window regs are in there somewhere. */
for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++)
saved_regs_addr->regs[regnum] =
- frame + (regnum - G0_REGNUM) * 4 - 0xa0;
+ frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE
+ - (NUM_SPARC_FPREGS * 4 + 8 * SPARC_INTREG_SIZE);
for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++)
saved_regs_addr->regs[regnum] =
- frame + (regnum - I0_REGNUM) * 4 - 0xc0;
+ frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
+ - (NUM_SPARC_FPREGS * 4 + 16 * SPARC_INTREG_SIZE);
for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++)
saved_regs_addr->regs[regnum] =
- frame + (regnum - FP0_REGNUM) * 4 - 0x80;
+ frame_addr + (regnum - FP0_REGNUM) * 4
+ - (NUM_SPARC_FPREGS * 4);
for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++)
saved_regs_addr->regs[regnum] =
- frame + (regnum - Y_REGNUM) * 4 - 0xe0;
- frame = fi->bottom ?
+ frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE - 0xe0;
+ - (NUM_SPARC_FPREGS * 4 + 24 * SPARC_INTREG_SIZE);
+ frame_addr = fi->bottom ?
fi->bottom : read_register (SP_REGNUM);
}
+ else if (fi->flat)
+ {
+ CORE_ADDR func_start;
+ find_pc_partial_function (fi->pc, NULL, &func_start, NULL);
+ examine_prologue (func_start, 0, fi, saved_regs_addr);
+
+ /* Flat register window frame. */
+ saved_regs_addr->regs[RP_REGNUM] = fi->pc_addr;
+ saved_regs_addr->regs[I7_REGNUM] = fi->fp_addr;
+ }
else
{
/* Normal frame. Just Local and In registers */
- frame = fi->bottom ?
+ frame_addr = fi->bottom ?
fi->bottom : read_register (SP_REGNUM);
- for (regnum = L0_REGNUM; regnum < L0_REGNUM+16; regnum++)
- saved_regs_addr->regs[regnum] = frame + (regnum-L0_REGNUM) * 4;
+ for (regnum = L0_REGNUM; regnum < L0_REGNUM+8; regnum++)
+ saved_regs_addr->regs[regnum] =
+ (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE
+ + FRAME_SAVED_L0);
+ for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++)
+ saved_regs_addr->regs[regnum] =
+ (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
+ + FRAME_SAVED_I0);
}
if (fi->next)
{
- /* Pull off either the next frame pointer or the stack pointer */
- FRAME_ADDR next_next_frame =
- (fi->next->bottom ?
- fi->next->bottom :
- read_register (SP_REGNUM));
- for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++)
- saved_regs_addr->regs[regnum] = next_next_frame + regnum * 4;
+ if (fi->flat)
+ {
+ saved_regs_addr->regs[O7_REGNUM] = fi->pc_addr;
+ }
+ else
+ {
+ /* Pull off either the next frame pointer or the stack pointer */
+ CORE_ADDR next_next_frame_addr =
+ (fi->next->bottom ?
+ fi->next->bottom :
+ read_register (SP_REGNUM));
+ for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++)
+ saved_regs_addr->regs[regnum] =
+ (next_next_frame_addr
+ + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE
+ + FRAME_SAVED_I0);
+ }
}
/* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi);
}
-/* Push an empty stack frame, and record in it the current PC, regs, etc.
-
- Note that the write's are of registers in the context of the newly
- pushed frame. Thus the the fp*'s, the g*'s, the i*'s, and
- the randoms, of the new frame, are being saved. The locals and outs
- are new; they don't need to be saved. The i's and l's of
- the last frame were saved by the do_save_insn in the register
- file (now on the stack, since a context switch happended imm after).
-
- The return pointer register %i7 does not have
- the pc saved into it (return from this frame will be accomplished
- by a POP_FRAME). In fact, we must leave it unclobbered, since we
- must preserve it in the calling routine except across call instructions. */
-
-/* Definitely see tm-sparc.h for more doc of the frame format here. */
-
-void
-sparc_push_dummy_frame ()
-{
- CORE_ADDR fp;
- char register_temp[REGISTER_BYTES];
-
- do_save_insn (0x140); /* FIXME where does this value come from? */
- fp = read_register (FP_REGNUM);
-
- read_register_bytes (REGISTER_BYTE (FP0_REGNUM), register_temp, 32 * 4);
- write_memory (fp - 0x80, register_temp, 32 * 4);
-
- read_register_bytes (REGISTER_BYTE (G0_REGNUM), register_temp, 8 * 4);
- write_memory (fp - 0xa0, register_temp, 8 * 4);
-
- read_register_bytes (REGISTER_BYTE (I0_REGNUM), register_temp, 8 * 4);
- write_memory (fp - 0xc0, register_temp, 8 * 4);
-
- /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
- read_register_bytes (REGISTER_BYTE (Y_REGNUM), register_temp, 8 * 4);
- write_memory (fp - 0xe0, register_temp, 8 * 4);
-}
-
/* Discard from the stack the innermost frame, restoring all saved registers.
Note that the values stored in fsr by get_frame_saved_regs are *in
void
sparc_pop_frame ()
{
- register FRAME frame = get_current_frame ();
+ register struct frame_info *frame = get_current_frame ();
register CORE_ADDR pc;
struct frame_saved_regs fsr;
- struct frame_info *fi;
char raw_buffer[REGISTER_BYTES];
+ int regnum;
- fi = get_frame_info (frame);
- get_frame_saved_regs (fi, &fsr);
- do_restore_insn ();
+ sparc_frame_find_saved_regs (frame, &fsr);
if (fsr.regs[FP0_REGNUM])
{
- read_memory (fsr.regs[FP0_REGNUM], raw_buffer, 32 * 4);
- write_register_bytes (REGISTER_BYTE (FP0_REGNUM), raw_buffer, 32 * 4);
+ read_memory (fsr.regs[FP0_REGNUM], raw_buffer, NUM_SPARC_FPREGS * 4);
+ write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
+ raw_buffer, NUM_SPARC_FPREGS * 4);
+ }
+#ifndef GDB_TARGET_IS_SPARC64
+ if (fsr.regs[FPS_REGNUM])
+ {
+ read_memory (fsr.regs[FPS_REGNUM], raw_buffer, 4);
+ write_register_bytes (REGISTER_BYTE (FPS_REGNUM), raw_buffer, 4);
+ }
+ if (fsr.regs[CPS_REGNUM])
+ {
+ read_memory (fsr.regs[CPS_REGNUM], raw_buffer, 4);
+ write_register_bytes (REGISTER_BYTE (CPS_REGNUM), raw_buffer, 4);
}
+#endif
if (fsr.regs[G1_REGNUM])
{
- read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * 4);
- write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, 7 * 4);
+ read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE);
+ write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer,
+ 7 * SPARC_INTREG_SIZE);
+ }
+
+ if (frame->flat)
+ {
+ /* Each register might or might not have been saved, need to test
+ individually. */
+ for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum)
+ if (fsr.regs[regnum])
+ write_register (regnum, read_memory_integer (fsr.regs[regnum],
+ SPARC_INTREG_SIZE));
+ for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum)
+ if (fsr.regs[regnum])
+ write_register (regnum, read_memory_integer (fsr.regs[regnum],
+ SPARC_INTREG_SIZE));
+
+ /* Handle all outs except stack pointer (o0-o5; o7). */
+ for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum)
+ if (fsr.regs[regnum])
+ write_register (regnum, read_memory_integer (fsr.regs[regnum],
+ SPARC_INTREG_SIZE));
+ if (fsr.regs[O0_REGNUM + 7])
+ write_register (O0_REGNUM + 7,
+ read_memory_integer (fsr.regs[O0_REGNUM + 7],
+ SPARC_INTREG_SIZE));
+
+ write_register (SP_REGNUM, frame->frame);
}
- if (fsr.regs[I0_REGNUM])
+ else if (fsr.regs[I0_REGNUM])
{
- read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * 4);
- write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, 8 * 4);
+ CORE_ADDR sp;
+
+ char reg_temp[REGISTER_BYTES];
+
+ read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE);
+
+ /* Get the ins and locals which we are about to restore. Just
+ moving the stack pointer is all that is really needed, except
+ store_inferior_registers is then going to write the ins and
+ locals from the registers array, so we need to muck with the
+ registers array. */
+ sp = fsr.regs[SP_REGNUM];
+ read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16);
+
+ /* Restore the out registers.
+ Among other things this writes the new stack pointer. */
+ write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer,
+ SPARC_INTREG_SIZE * 8);
+
+ write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp,
+ SPARC_INTREG_SIZE * 16);
}
+#ifndef GDB_TARGET_IS_SPARC64
if (fsr.regs[PS_REGNUM])
write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4));
+#endif
if (fsr.regs[Y_REGNUM])
- write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], 4));
+ write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], REGISTER_RAW_SIZE (Y_REGNUM)));
if (fsr.regs[PC_REGNUM])
{
/* Explicitly specified PC (and maybe NPC) -- just restore them. */
- write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], 4));
+ write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM],
+ REGISTER_RAW_SIZE (PC_REGNUM)));
if (fsr.regs[NPC_REGNUM])
write_register (NPC_REGNUM,
- read_memory_integer (fsr.regs[NPC_REGNUM], 4));
+ read_memory_integer (fsr.regs[NPC_REGNUM],
+ REGISTER_RAW_SIZE (NPC_REGNUM)));
+ }
+ else if (frame->flat)
+ {
+ if (frame->pc_addr)
+ pc = PC_ADJUST ((CORE_ADDR)
+ read_memory_integer (frame->pc_addr,
+ REGISTER_RAW_SIZE (PC_REGNUM)));
+ else
+ {
+ /* I think this happens only in the innermost frame, if so then
+ it is a complicated way of saying
+ "pc = read_register (O7_REGNUM);". */
+ char buf[MAX_REGISTER_RAW_SIZE];
+ get_saved_register (buf, 0, 0, frame, O7_REGNUM, 0);
+ pc = PC_ADJUST (extract_address
+ (buf, REGISTER_RAW_SIZE (O7_REGNUM)));
+ }
+
+ write_register (PC_REGNUM, pc);
+ write_register (NPC_REGNUM, pc + 4);
}
else if (fsr.regs[I7_REGNUM])
{
/* Return address in %i7 -- adjust it, then restore PC and NPC from it */
- pc = PC_ADJUST (read_memory_integer (fsr.regs[I7_REGNUM], 4));
+ pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr.regs[I7_REGNUM],
+ SPARC_INTREG_SIZE));
write_register (PC_REGNUM, pc);
write_register (NPC_REGNUM, pc + 4);
}
flush_cached_frames ();
- set_current_frame ( create_new_frame (read_register (FP_REGNUM),
- read_pc ()));
}
/* On the Sun 4 under SunOS, the compile will leave a fake insn which
sparc_pc_adjust(pc)
CORE_ADDR pc;
{
- long insn;
+ unsigned long insn;
+ char buf[4];
int err;
- err = target_read_memory (pc + 8, (char *)&insn, sizeof(long));
- SWAP_TARGET_AND_HOST (&insn, sizeof(long));
- if ((err == 0) && (insn & 0xfffffe00) == 0)
+ err = target_read_memory (pc + 8, buf, sizeof(long));
+ insn = extract_unsigned_integer (buf, 4);
+ if ((err == 0) && (insn & 0xffc00000) == 0)
return pc+12;
else
return pc+8;
}
+/* If pc is in a shared library trampoline, return its target.
+ The SunOs 4.x linker rewrites the jump table entries for PIC
+ compiled modules in the main executable to bypass the dynamic linker
+ with jumps of the form
+ sethi %hi(addr),%g1
+ jmp %g1+%lo(addr)
+ and removes the corresponding jump table relocation entry in the
+ dynamic relocations.
+ find_solib_trampoline_target relies on the presence of the jump
+ table relocation entry, so we have to detect these jump instructions
+ by hand. */
+
+CORE_ADDR
+sunos4_skip_trampoline_code (pc)
+ CORE_ADDR pc;
+{
+ unsigned long insn1;
+ char buf[4];
+ int err;
+
+ err = target_read_memory (pc, buf, 4);
+ insn1 = extract_unsigned_integer (buf, 4);
+ if (err == 0 && (insn1 & 0xffc00000) == 0x03000000)
+ {
+ unsigned long insn2;
-/* Structure of SPARC extended floating point numbers.
- This information is not currently used by GDB, since no current SPARC
- implementations support extended float. */
+ err = target_read_memory (pc + 4, buf, 4);
+ insn2 = extract_unsigned_integer (buf, 4);
+ if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000)
+ {
+ CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10;
+ int delta = insn2 & 0x1fff;
-const struct ext_format ext_format_sparc = {
-/* tot sbyte smask expbyte manbyte */
- 16, 0, 0x80, 0,1, 4,8, /* sparc */
-};
+ /* Sign extend the displacement. */
+ if (delta & 0x1000)
+ delta |= ~0x1fff;
+ return target_pc + delta;
+ }
+ }
+ return find_solib_trampoline_target (pc);
+}
\f
#ifdef USE_PROC_FS /* Target dependent support for /proc */
*/
-
-/* Given a pointer to a general register set in /proc format (gregset_t *),
- unpack the register contents and supply them as gdb's idea of the current
- register values. */
+/* Given a pointer to a general register set in /proc format (gregset_t *),
+ unpack the register contents and supply them as gdb's idea of the current
+ register values. */
void
supply_gregset (gregsetp)
prgregset_t *gregsetp;
{
- register int regno;
+ register int regi;
register prgreg_t *regp = (prgreg_t *) gregsetp;
+ static char zerobuf[MAX_REGISTER_RAW_SIZE] = {0};
/* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
- for (regno = G0_REGNUM ; regno <= I7_REGNUM ; regno++)
+ for (regi = G0_REGNUM ; regi <= I7_REGNUM ; regi++)
{
- supply_register (regno, (char *) (regp + regno));
+ supply_register (regi, (char *) (regp + regi));
}
/* These require a bit more care. */
supply_register (PC_REGNUM, (char *) (regp + R_PC));
supply_register (NPC_REGNUM,(char *) (regp + R_nPC));
supply_register (Y_REGNUM, (char *) (regp + R_Y));
+
+ /* Fill inaccessible registers with zero. */
+ supply_register (WIM_REGNUM, zerobuf);
+ supply_register (TBR_REGNUM, zerobuf);
+ supply_register (CPS_REGNUM, zerobuf);
}
void
{
int regi;
register prgreg_t *regp = (prgreg_t *) gregsetp;
- extern char registers[];
for (regi = 0 ; regi <= R_I7 ; regi++)
{
if ((regno == -1) || (regno == regi))
{
- *(regp + regno) = *(int *) ®isters[REGISTER_BYTE (regi)];
+ *(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)];
}
}
if ((regno == -1) || (regno == PS_REGNUM))
(fpregset_t *), update the register specified by REGNO from gdb's idea
of the current floating point register set. If REGNO is -1, update
them all. */
+/* ??? This will probably need some changes for sparc64. */
void
fill_fpregset (fpregsetp, regno)
int regi;
char *to;
char *from;
- extern char registers[];
- for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++)
+ /* ??? The 32 should probably be NUM_SPARC_FPREGS, but again we're
+ waiting on what REGISTER_RAW_SIZE should be for fp regs. */
+ for (regi = FP0_REGNUM ; regi < FP0_REGNUM + 32 ; regi++)
{
if ((regno == -1) || (regno == regi))
{
from = (char *) ®isters[REGISTER_BYTE (regi)];
to = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM];
- bcopy (from, to, REGISTER_RAW_SIZE (regno));
+ memcpy (to, from, REGISTER_RAW_SIZE (regi));
}
}
if ((regno == -1) || (regno == FPS_REGNUM))
This routine returns true on success */
int
-get_longjmp_target(pc)
+get_longjmp_target (pc)
CORE_ADDR *pc;
{
CORE_ADDR jb_addr;
+#define LONGJMP_TARGET_SIZE 4
+ char buf[LONGJMP_TARGET_SIZE];
- jb_addr = read_register(O0_REGNUM);
+ jb_addr = read_register (O0_REGNUM);
- if (target_read_memory(jb_addr + JB_PC * JB_ELEMENT_SIZE, (char *) pc,
- sizeof(CORE_ADDR)))
+ if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
+ LONGJMP_TARGET_SIZE))
return 0;
- SWAP_TARGET_AND_HOST(pc, sizeof(CORE_ADDR));
+ *pc = extract_address (buf, LONGJMP_TARGET_SIZE);
return 1;
}
#endif /* GET_LONGJMP_TARGET */
+\f
+#ifdef STATIC_TRANSFORM_NAME
+/* SunPRO (3.0 at least), encodes the static variables. This is not
+ related to C++ mangling, it is done for C too. */
+
+char *
+sunpro_static_transform_name (name)
+ char *name;
+{
+ char *p;
+ if (name[0] == '$')
+ {
+ /* For file-local statics there will be a dollar sign, a bunch
+ of junk (the contents of which match a string given in the
+ N_OPT), a period and the name. For function-local statics
+ there will be a bunch of junk (which seems to change the
+ second character from 'A' to 'B'), a period, the name of the
+ function, and the name. So just skip everything before the
+ last period. */
+ p = strrchr (name, '.');
+ if (p != NULL)
+ name = p + 1;
+ }
+ return name;
+}
+#endif /* STATIC_TRANSFORM_NAME */
+\f
+#ifdef GDB_TARGET_IS_SPARC64
+
+/* Utilities for printing registers.
+ Page numbers refer to the SPARC Architecture Manual. */
+
+static void dump_ccreg PARAMS ((char *, int));
+
+static void
+dump_ccreg (reg, val)
+ char *reg;
+ int val;
+{
+ /* page 41 */
+ printf_unfiltered ("%s:%s,%s,%s,%s", reg,
+ val & 8 ? "N" : "NN",
+ val & 4 ? "Z" : "NZ",
+ val & 2 ? "O" : "NO",
+ val & 1 ? "C" : "NC"
+ );
+}
+
+static char *
+decode_asi (val)
+ int val;
+{
+ /* page 72 */
+ switch (val)
+ {
+ case 4 : return "ASI_NUCLEUS";
+ case 0x0c : return "ASI_NUCLEUS_LITTLE";
+ case 0x10 : return "ASI_AS_IF_USER_PRIMARY";
+ case 0x11 : return "ASI_AS_IF_USER_SECONDARY";
+ case 0x18 : return "ASI_AS_IF_USER_PRIMARY_LITTLE";
+ case 0x19 : return "ASI_AS_IF_USER_SECONDARY_LITTLE";
+ case 0x80 : return "ASI_PRIMARY";
+ case 0x81 : return "ASI_SECONDARY";
+ case 0x82 : return "ASI_PRIMARY_NOFAULT";
+ case 0x83 : return "ASI_SECONDARY_NOFAULT";
+ case 0x88 : return "ASI_PRIMARY_LITTLE";
+ case 0x89 : return "ASI_SECONDARY_LITTLE";
+ case 0x8a : return "ASI_PRIMARY_NOFAULT_LITTLE";
+ case 0x8b : return "ASI_SECONDARY_NOFAULT_LITTLE";
+ default : return NULL;
+ }
+}
+
+/* PRINT_REGISTER_HOOK routine.
+ Pretty print various registers. */
+/* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
+
+void
+sparc_print_register_hook (regno)
+ int regno;
+{
+ unsigned LONGEST val;
+
+ if (((unsigned) (regno) - FP0_REGNUM < FP_MAX_REGNUM - FP0_REGNUM)
+ && ((regno) & 1) == 0)
+ {
+ char doublereg[8]; /* two float regs */
+ if (!read_relative_register_raw_bytes ((regno), doublereg))
+ {
+ printf_unfiltered("\t");
+ print_floating (doublereg, builtin_type_double, gdb_stdout);
+ }
+ return;
+ }
+
+ /* FIXME: Some of these are priviledged registers.
+ Not sure how they should be handled. */
+
+#define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
+
+ val = read_register (regno);
+
+ /* pages 40 - 60 */
+ switch (regno)
+ {
+ case CCR_REGNUM :
+ printf_unfiltered("\t");
+ dump_ccreg ("xcc", val >> 4);
+ printf_unfiltered(", ");
+ dump_ccreg ("icc", val & 15);
+ break;
+ case FPRS_REGNUM :
+ printf ("\tfef:%d, du:%d, dl:%d",
+ BITS (2, 1), BITS (1, 1), BITS (0, 1));
+ break;
+ case FSR_REGNUM :
+ {
+ static char *fcc[4] = { "=", "<", ">", "?" };
+ static char *rd[4] = { "N", "0", "+", "-" };
+ /* Long, yes, but I'd rather leave it as is and use a wide screen. */
+ printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
+ fcc[BITS (10, 3)], fcc[BITS (32, 3)],
+ fcc[BITS (34, 3)], fcc[BITS (36, 3)],
+ rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
+ BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31));
+ break;
+ }
+ case ASI_REGNUM :
+ {
+ char *asi = decode_asi (val);
+ if (asi != NULL)
+ printf ("\t%s", asi);
+ break;
+ }
+ case VER_REGNUM :
+ printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
+ BITS (48, 0xffff), BITS (32, 0xffff),
+ BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
+ break;
+ case PSTATE_REGNUM :
+ {
+ static char *mm[4] = { "tso", "pso", "rso", "?" };
+ printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
+ BITS (9, 1), BITS (8, 1), mm[BITS (6, 3)], BITS (5, 1),
+ BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1),
+ BITS (0, 1));
+ break;
+ }
+ case TSTATE_REGNUM :
+ /* FIXME: print all 4? */
+ break;
+ case TT_REGNUM :
+ /* FIXME: print all 4? */
+ break;
+ case TPC_REGNUM :
+ /* FIXME: print all 4? */
+ break;
+ case TNPC_REGNUM :
+ /* FIXME: print all 4? */
+ break;
+ case WSTATE_REGNUM :
+ printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
+ break;
+ case CWP_REGNUM :
+ printf ("\t%d", BITS (0, 31));
+ break;
+ case CANSAVE_REGNUM :
+ printf ("\t%-2d before spill", BITS (0, 31));
+ break;
+ case CANRESTORE_REGNUM :
+ printf ("\t%-2d before fill", BITS (0, 31));
+ break;
+ case CLEANWIN_REGNUM :
+ printf ("\t%-2d before clean", BITS (0, 31));
+ break;
+ case OTHERWIN_REGNUM :
+ printf ("\t%d", BITS (0, 31));
+ break;
+ }
+
+#undef BITS
+}
+
+#endif
+\f
+void
+_initialize_sparc_tdep ()
+{
+ tm_print_insn = print_insn_sparc;
+}
projects / deliverable / binutils-gdb.git / blobdiff