/* Target-dependent code for SPARC.
- Copyright (C) 2003-2013 Free Software Foundation, Inc.
+ Copyright (C) 2003-2016 Free Software Foundation, Inc.
This file is part of GDB.
#include "target.h"
#include "value.h"
-#include "gdb_assert.h"
-#include "gdb_string.h"
-
#include "sparc-tdep.h"
#include "sparc-ravenscar-thread.h"
+#include <algorithm>
struct regset;
#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
#define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
#define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
+/* Macros to identify some instructions. */
+/* RETURN (RETT in V8) */
+#define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
/* Fetch the instruction at PC. Instructions are always big-endian
even if the processor operates in little-endian mode. */
return ((insn & 0xc1c00000) == 0);
}
+/* Return non-zero if the instruction corresponding to PC is an
+ "annulled" branch, i.e. the annul bit is set. */
+
+int
+sparc_is_annulled_branch_insn (CORE_ADDR pc)
+{
+ /* The branch instructions featuring an annul bit can be identified
+ by the following bit patterns:
+
+ OP=0
+ OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
+ OP2=2: Branch on Integer Condition Codes (Bcc).
+ OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
+ OP2=6: Branch on FP Condition Codes (FBcc).
+ OP2=3 && Bit28=0:
+ Branch on Integer Register with Prediction (BPr).
+
+ This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
+ coprocessor branch instructions (Op2=7). */
+
+ const unsigned long insn = sparc_fetch_instruction (pc);
+ const unsigned op2 = X_OP2 (insn);
+
+ if ((X_OP (insn) == 0)
+ && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6)
+ || ((op2 == 3) && ((insn & 0x10000000) == 0))))
+ return X_A (insn);
+ else
+ return 0;
+}
+
/* OpenBSD/sparc includes StackGhost, which according to the author's
website http://stackghost.cerias.purdue.edu "... transparently and
automatically protects applications' stack frames; more
regcache_raw_write (regcache, regnum + 1, buf + 4);
}
\f
+/* Implement the stack_frame_destroyed_p gdbarch method. */
+
+int
+sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+ /* This function must return true if we are one instruction after an
+ instruction that destroyed the stack frame of the current
+ function. The SPARC instructions used to restore the callers
+ stack frame are RESTORE and RETURN/RETT.
+
+ Of these RETURN/RETT is a branch instruction and thus we return
+ true if we are in its delay slot.
+
+ RESTORE is almost always found in the delay slot of a branch
+ instruction that transfers control to the caller, such as JMPL.
+ Thus the next instruction is in the caller frame and we don't
+ need to do anything about it. */
+
+ unsigned int insn = sparc_fetch_instruction (pc - 4);
+
+ return X_RETTURN (insn);
+}
+\f
static CORE_ADDR
sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
}
/* Always allocate at least six words. */
- sp -= max (6, num_elements) * 4;
+ sp -= std::max (6, num_elements) * 4;
/* The psABI says that "Software convention requires space for the
struct/union return value pointer, even if the word is unused." */
encode a breakpoint instruction, store the length of the string in
*LEN and optionally adjust *PC to point to the correct memory
location for inserting the breakpoint. */
-
-static const gdb_byte *
-sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
-{
- static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
+constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
- *len = sizeof (break_insn);
- return break_insn;
-}
+typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint;
\f
/* Allocate and initialize a frame cache. */
{
CORE_ADDR pc = start_pc;
unsigned long insn;
- int offset_stack_checking_sequence = 0;
int probing_loop = 0;
/* With GCC, all stack checking sequences begin with the same two
struct sparc_frame_cache *cache;
if (*this_cache)
- return *this_cache;
+ return (struct sparc_frame_cache *) *this_cache;
cache = sparc_alloc_frame_cache ();
*this_cache = cache;
struct symbol *sym;
if (*this_cache)
- return *this_cache;
+ return (struct sparc_frame_cache *) *this_cache;
cache = sparc_frame_cache (this_frame, this_cache);
software single-step mechanism. */
static CORE_ADDR
-sparc_analyze_control_transfer (struct frame_info *frame,
+sparc_analyze_control_transfer (struct regcache *regcache,
CORE_ADDR pc, CORE_ADDR *npc)
{
unsigned long insn = sparc_fetch_instruction (pc);
}
else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
{
+ struct frame_info *frame = get_current_frame ();
+
/* Trap instruction (TRAP). */
- return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn);
+ return gdbarch_tdep (get_regcache_arch (regcache))->step_trap (frame,
+ insn);
}
/* FIXME: Handle DONE and RETRY instructions. */
return 0;
}
-int
-sparc_software_single_step (struct frame_info *frame)
+static VEC (CORE_ADDR) *
+sparc_software_single_step (struct regcache *regcache)
{
- struct gdbarch *arch = get_frame_arch (frame);
+ struct gdbarch *arch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
- struct address_space *aspace = get_frame_address_space (frame);
CORE_ADDR npc, nnpc;
CORE_ADDR pc, orig_npc;
+ VEC (CORE_ADDR) *next_pcs = NULL;
- pc = get_frame_register_unsigned (frame, tdep->pc_regnum);
- orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum);
+ pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum);
+ orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum);
/* Analyze the instruction at PC. */
- nnpc = sparc_analyze_control_transfer (frame, pc, &npc);
+ nnpc = sparc_analyze_control_transfer (regcache, pc, &npc);
if (npc != 0)
- insert_single_step_breakpoint (arch, aspace, npc);
+ VEC_safe_push (CORE_ADDR, next_pcs, npc);
if (nnpc != 0)
- insert_single_step_breakpoint (arch, aspace, nnpc);
+ VEC_safe_push (CORE_ADDR, next_pcs, nnpc);
/* Assert that we have set at least one breakpoint, and that
they're not set at the same spot - unless we're going
gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
gdb_assert (nnpc != npc || orig_npc == 0);
- return 1;
+ return next_pcs;
}
static void
}
\f
-/* Return the appropriate register set for the core section identified
- by SECT_NAME and SECT_SIZE. */
+/* Iterate over core file register note sections. */
-static const struct regset *
-sparc_regset_from_core_section (struct gdbarch *gdbarch,
- const char *sect_name, size_t sect_size)
+static void
+sparc_iterate_over_regset_sections (struct gdbarch *gdbarch,
+ iterate_over_regset_sections_cb *cb,
+ void *cb_data,
+ const struct regcache *regcache)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
- return tdep->gregset;
-
- if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
- return tdep->fpregset;
-
- return NULL;
+ cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
+ cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
}
\f
return arches->gdbarch;
/* Allocate space for the new architecture. */
- tdep = XZALLOC (struct gdbarch_tdep);
+ tdep = XCNEW (struct gdbarch_tdep);
gdbarch = gdbarch_alloc (&info, tdep);
tdep->pc_regnum = SPARC32_PC_REGNUM;
/* Stack grows downward. */
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
- set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
+ set_gdbarch_breakpoint_kind_from_pc (gdbarch,
+ sparc_breakpoint::kind_from_pc);
+ set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+ sparc_breakpoint::bp_from_kind);
set_gdbarch_frame_args_skip (gdbarch, 8);
/* If we have register sets, enable the generic core file support. */
if (tdep->gregset)
- set_gdbarch_regset_from_core_section (gdbarch,
- sparc_regset_from_core_section);
+ set_gdbarch_iterate_over_regset_sections
+ (gdbarch, sparc_iterate_over_regset_sections);
register_sparc_ravenscar_ops (gdbarch);
/* Helper functions for dealing with register sets. */
void
-sparc32_supply_gregset (const struct sparc_gregset *gregset,
+sparc32_supply_gregset (const struct sparc_gregmap *gregmap,
struct regcache *regcache,
int regnum, const void *gregs)
{
- const gdb_byte *regs = gregs;
+ const gdb_byte *regs = (const gdb_byte *) gregs;
gdb_byte zero[4] = { 0 };
int i;
if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
- regs + gregset->r_psr_offset);
+ regs + gregmap->r_psr_offset);
if (regnum == SPARC32_PC_REGNUM || regnum == -1)
regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
- regs + gregset->r_pc_offset);
+ regs + gregmap->r_pc_offset);
if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
- regs + gregset->r_npc_offset);
+ regs + gregmap->r_npc_offset);
if (regnum == SPARC32_Y_REGNUM || regnum == -1)
regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
- regs + gregset->r_y_offset);
+ regs + gregmap->r_y_offset);
if (regnum == SPARC_G0_REGNUM || regnum == -1)
regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero);
if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
{
- int offset = gregset->r_g1_offset;
+ int offset = gregmap->r_g1_offset;
for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
{
{
/* Not all of the register set variants include Locals and
Inputs. For those that don't, we read them off the stack. */
- if (gregset->r_l0_offset == -1)
+ if (gregmap->r_l0_offset == -1)
{
ULONGEST sp;
}
else
{
- int offset = gregset->r_l0_offset;
+ int offset = gregmap->r_l0_offset;
for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
{
}
void
-sparc32_collect_gregset (const struct sparc_gregset *gregset,
+sparc32_collect_gregset (const struct sparc_gregmap *gregmap,
const struct regcache *regcache,
int regnum, void *gregs)
{
- gdb_byte *regs = gregs;
+ gdb_byte *regs = (gdb_byte *) gregs;
int i;
if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
- regs + gregset->r_psr_offset);
+ regs + gregmap->r_psr_offset);
if (regnum == SPARC32_PC_REGNUM || regnum == -1)
regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
- regs + gregset->r_pc_offset);
+ regs + gregmap->r_pc_offset);
if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
- regs + gregset->r_npc_offset);
+ regs + gregmap->r_npc_offset);
if (regnum == SPARC32_Y_REGNUM || regnum == -1)
regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
- regs + gregset->r_y_offset);
+ regs + gregmap->r_y_offset);
if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
{
- int offset = gregset->r_g1_offset;
+ int offset = gregmap->r_g1_offset;
/* %g0 is always zero. */
for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
{
/* Not all of the register set variants include Locals and
Inputs. For those that don't, we read them off the stack. */
- if (gregset->r_l0_offset != -1)
+ if (gregmap->r_l0_offset != -1)
{
- int offset = gregset->r_l0_offset;
+ int offset = gregmap->r_l0_offset;
for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
{
}
void
-sparc32_supply_fpregset (const struct sparc_fpregset *fpregset,
+sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap,
struct regcache *regcache,
int regnum, const void *fpregs)
{
- const gdb_byte *regs = fpregs;
+ const gdb_byte *regs = (const gdb_byte *) fpregs;
int i;
for (i = 0; i < 32; i++)
{
if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
regcache_raw_supply (regcache, SPARC_F0_REGNUM + i,
- regs + fpregset->r_f0_offset + (i * 4));
+ regs + fpregmap->r_f0_offset + (i * 4));
}
if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
regcache_raw_supply (regcache, SPARC32_FSR_REGNUM,
- regs + fpregset->r_fsr_offset);
+ regs + fpregmap->r_fsr_offset);
}
void
-sparc32_collect_fpregset (const struct sparc_fpregset *fpregset,
+sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap,
const struct regcache *regcache,
int regnum, void *fpregs)
{
- gdb_byte *regs = fpregs;
+ gdb_byte *regs = (gdb_byte *) fpregs;
int i;
for (i = 0; i < 32; i++)
{
if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
regcache_raw_collect (regcache, SPARC_F0_REGNUM + i,
- regs + fpregset->r_f0_offset + (i * 4));
+ regs + fpregmap->r_f0_offset + (i * 4));
}
if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
regcache_raw_collect (regcache, SPARC32_FSR_REGNUM,
- regs + fpregset->r_fsr_offset);
+ regs + fpregmap->r_fsr_offset);
}
\f
/* SunOS 4. */
/* From <machine/reg.h>. */
-const struct sparc_gregset sparc32_sunos4_gregset =
+const struct sparc_gregmap sparc32_sunos4_gregmap =
{
0 * 4, /* %psr */
1 * 4, /* %pc */
-1 /* %l0 */
};
-const struct sparc_fpregset sparc32_sunos4_fpregset =
+const struct sparc_fpregmap sparc32_sunos4_fpregmap =
{
0 * 4, /* %f0 */
33 * 4, /* %fsr */
};
-const struct sparc_fpregset sparc32_bsd_fpregset =
+const struct sparc_fpregmap sparc32_bsd_fpregmap =
{
0 * 4, /* %f0 */
32 * 4, /* %fsr */
projects / deliverable / binutils-gdb.git / blobdiff