gdb: add cmd_list_element::is_command_class_help

[deliverable/binutils-gdb.git] / gdb / tilegx-tdep.c

diff --git a/gdb/tilegx-tdep.c b/gdb/tilegx-tdep.c
index dfa2eece104bbb056d0b3f8a74d35a18fbe44761..9bd982f49f50f1ce0fc9895b40cf6d5f4d6c0dda 100644 (file)
--- a/gdb/tilegx-tdep.c
+++ b/gdb/tilegx-tdep.c
@@ -1,6 +1,6 @@
 /* Target-dependent code for the Tilera TILE-Gx processor.
 
-   Copyright (C) 2012-2020 Free Software Foundation, Inc.
+   Copyright (C) 2012-2021 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -50,7 +50,7 @@ struct tilegx_frame_cache
   CORE_ADDR start_pc;
 
   /* Table of saved registers.  */
-  struct trad_frame_saved_reg *saved_regs;
+  trad_frame_saved_reg *saved_regs;
 };
 
 /* Register state values used by analyze_prologue.  */
@@ -429,7 +429,7 @@ tilegx_analyze_prologue (struct gdbarch* gdbarch,
          instbuf_start = next_addr;
 
          status = safe_frame_unwind_memory (next_frame, instbuf_start,
-                                            instbuf, instbuf_size);
+                                            {instbuf, instbuf_size});
          if (status == 0)
            memory_error (TARGET_XFER_E_IO, next_addr);
        }
@@ -459,13 +459,7 @@ tilegx_analyze_prologue (struct gdbarch* gdbarch,
                  unsigned saved_register
                    = (unsigned) reverse_frame[operands[1]].value;
 
-                 /* realreg >= 0 and addr != -1 indicates that the
-                    value of saved_register is in memory location
-                    saved_address.  The value of realreg is not
-                    meaningful in this case but it must be >= 0.
-                    See trad-frame.h.  */
-                 cache->saved_regs[saved_register].realreg = saved_register;
-                 cache->saved_regs[saved_register].addr = saved_address;
+                 cache->saved_regs[saved_register].set_addr (saved_address);
                } 
              else if (cache
                       && (operands[0] == TILEGX_SP_REGNUM) 
@@ -488,14 +482,13 @@ tilegx_analyze_prologue (struct gdbarch* gdbarch,
                  /* Fix up the sign-extension.  */
                  if (opcode->mnemonic == TILEGX_OPC_ADDI)
                    op2_as_short = op2_as_char;
-                 prev_sp_value = (cache->saved_regs[hopefully_sp].addr
+                 prev_sp_value = (cache->saved_regs[hopefully_sp].addr ()
                                   - op2_as_short);
 
                  new_reverse_frame[i].state = REVERSE_STATE_VALUE;
                  new_reverse_frame[i].value
-                   = cache->saved_regs[hopefully_sp].addr;
-                 trad_frame_set_value (cache->saved_regs,
-                                       hopefully_sp, prev_sp_value);
+                   = cache->saved_regs[hopefully_sp].addr ();
+                 cache->saved_regs[hopefully_sp].set_value (prev_sp_value);
                }
              else
                {
@@ -717,17 +710,15 @@ tilegx_analyze_prologue (struct gdbarch* gdbarch,
            {
              unsigned saved_register = (unsigned) reverse_frame[i].value;
 
-             cache->saved_regs[saved_register].realreg = i;
-             cache->saved_regs[saved_register].addr = (LONGEST) -1;
+             cache->saved_regs[saved_register].set_realreg (i);
            }
        }
     }
 
   if (lr_saved_on_stack_p)
     {
-      cache->saved_regs[TILEGX_LR_REGNUM].realreg = TILEGX_LR_REGNUM;
-      cache->saved_regs[TILEGX_LR_REGNUM].addr =
-       cache->saved_regs[TILEGX_SP_REGNUM].addr;
+      CORE_ADDR addr = cache->saved_regs[TILEGX_SP_REGNUM].addr ();
+      cache->saved_regs[TILEGX_LR_REGNUM].set_addr (addr);
     }
 
   return prolog_end;
@@ -863,7 +854,7 @@ tilegx_frame_cache (struct frame_info *this_frame, void **this_cache)
   current_pc = get_frame_pc (this_frame);
 
   cache->base = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
-  trad_frame_set_value (cache->saved_regs, TILEGX_SP_REGNUM, cache->base);
+  cache->saved_regs[TILEGX_SP_REGNUM].set_value (cache->base);
 
   if (cache->start_pc)
     tilegx_analyze_prologue (gdbarch, cache->start_pc, current_pc,