Boston, MA 02111-1307, USA. */
#include "defs.h"
+#include "arch-utils.h"
+#include "block.h"
+#include "dummy-frame.h"
+#include "frame.h"
+#include "frame-base.h"
+#include "frame-unwind.h"
#include "inferior.h"
-#include "gdbcore.h"
#include "gdbcmd.h"
-#include "arch-utils.h"
+#include "gdbcore.h"
+#include "objfiles.h"
#include "regcache.h"
+#include "regset.h"
#include "symfile.h"
-#include "objfiles.h"
-#include "x86-64-tdep.h"
-#include "dwarf2cfi.h"
+
#include "gdb_assert.h"
-#include "block.h"
-/* Register numbers of various important registers. */
-#define RAX_REGNUM 0
-#define RDX_REGNUM 3
-#define RDI_REGNUM 5
-#define EFLAGS_REGNUM 17
-#define ST0_REGNUM 22
-#define XMM1_REGNUM 39
+#include "x86-64-tdep.h"
+#include "i387-tdep.h"
+
+/* Register information. */
-struct register_info
+struct x86_64_register_info
{
- int size;
char *name;
struct type **type;
};
-/* x86_64_register_raw_size_table[i] is the number of bytes of storage in
- GDB's register array occupied by register i. */
-static struct register_info x86_64_register_info_table[] = {
- /* 0 */ {8, "rax", &builtin_type_int64},
- /* 1 */ {8, "rbx", &builtin_type_int64},
- /* 2 */ {8, "rcx", &builtin_type_int64},
- /* 3 */ {8, "rdx", &builtin_type_int64},
- /* 4 */ {8, "rsi", &builtin_type_int64},
- /* 5 */ {8, "rdi", &builtin_type_int64},
- /* 6 */ {8, "rbp", &builtin_type_void_func_ptr},
- /* 7 */ {8, "rsp", &builtin_type_void_func_ptr},
- /* 8 */ {8, "r8", &builtin_type_int64},
- /* 9 */ {8, "r9", &builtin_type_int64},
- /* 10 */ {8, "r10", &builtin_type_int64},
- /* 11 */ {8, "r11", &builtin_type_int64},
- /* 12 */ {8, "r12", &builtin_type_int64},
- /* 13 */ {8, "r13", &builtin_type_int64},
- /* 14 */ {8, "r14", &builtin_type_int64},
- /* 15 */ {8, "r15", &builtin_type_int64},
- /* 16 */ {8, "rip", &builtin_type_void_func_ptr},
- /* 17 */ {4, "eflags", &builtin_type_int32},
- /* 18 */ {4, "ds", &builtin_type_int32},
- /* 19 */ {4, "es", &builtin_type_int32},
- /* 20 */ {4, "fs", &builtin_type_int32},
- /* 21 */ {4, "gs", &builtin_type_int32},
- /* 22 */ {10, "st0", &builtin_type_i387_ext},
- /* 23 */ {10, "st1", &builtin_type_i387_ext},
- /* 24 */ {10, "st2", &builtin_type_i387_ext},
- /* 25 */ {10, "st3", &builtin_type_i387_ext},
- /* 26 */ {10, "st4", &builtin_type_i387_ext},
- /* 27 */ {10, "st5", &builtin_type_i387_ext},
- /* 28 */ {10, "st6", &builtin_type_i387_ext},
- /* 29 */ {10, "st7", &builtin_type_i387_ext},
- /* 30 */ {4, "fctrl", &builtin_type_int32},
- /* 31 */ {4, "fstat", &builtin_type_int32},
- /* 32 */ {4, "ftag", &builtin_type_int32},
- /* 33 */ {4, "fiseg", &builtin_type_int32},
- /* 34 */ {4, "fioff", &builtin_type_int32},
- /* 35 */ {4, "foseg", &builtin_type_int32},
- /* 36 */ {4, "fooff", &builtin_type_int32},
- /* 37 */ {4, "fop", &builtin_type_int32},
- /* 38 */ {16, "xmm0", &builtin_type_v4sf},
- /* 39 */ {16, "xmm1", &builtin_type_v4sf},
- /* 40 */ {16, "xmm2", &builtin_type_v4sf},
- /* 41 */ {16, "xmm3", &builtin_type_v4sf},
- /* 42 */ {16, "xmm4", &builtin_type_v4sf},
- /* 43 */ {16, "xmm5", &builtin_type_v4sf},
- /* 44 */ {16, "xmm6", &builtin_type_v4sf},
- /* 45 */ {16, "xmm7", &builtin_type_v4sf},
- /* 46 */ {16, "xmm8", &builtin_type_v4sf},
- /* 47 */ {16, "xmm9", &builtin_type_v4sf},
- /* 48 */ {16, "xmm10", &builtin_type_v4sf},
- /* 49 */ {16, "xmm11", &builtin_type_v4sf},
- /* 50 */ {16, "xmm12", &builtin_type_v4sf},
- /* 51 */ {16, "xmm13", &builtin_type_v4sf},
- /* 52 */ {16, "xmm14", &builtin_type_v4sf},
- /* 53 */ {16, "xmm15", &builtin_type_v4sf},
- /* 54 */ {4, "mxcsr", &builtin_type_int32}
-};
-
-/* This array is a mapping from Dwarf-2 register
- numbering to GDB's one. Dwarf-2 numbering is
- defined in x86-64 ABI, section 3.6. */
-static int x86_64_dwarf2gdb_regno_map[] = {
- 0, 1, 2, 3, /* RAX - RDX */
- 4, 5, 6, 7, /* RSI, RDI, RBP, RSP */
- 8, 9, 10, 11, /* R8 - R11 */
- 12, 13, 14, 15, /* R12 - R15 */
- -1, /* RA - not mapped */
- XMM1_REGNUM - 1, XMM1_REGNUM, /* XMM0 ... */
- XMM1_REGNUM + 1, XMM1_REGNUM + 2,
- XMM1_REGNUM + 3, XMM1_REGNUM + 4,
- XMM1_REGNUM + 5, XMM1_REGNUM + 6,
- XMM1_REGNUM + 7, XMM1_REGNUM + 8,
- XMM1_REGNUM + 9, XMM1_REGNUM + 10,
- XMM1_REGNUM + 11, XMM1_REGNUM + 12,
- XMM1_REGNUM + 13, XMM1_REGNUM + 14, /* ... XMM15 */
- ST0_REGNUM + 0, ST0_REGNUM + 1, /* ST0 ... */
- ST0_REGNUM + 2, ST0_REGNUM + 3,
- ST0_REGNUM + 4, ST0_REGNUM + 5,
- ST0_REGNUM + 6, ST0_REGNUM + 7 /* ... ST7 */
+static struct x86_64_register_info x86_64_register_info[] =
+{
+ { "rax", &builtin_type_int64 },
+ { "rbx", &builtin_type_int64 },
+ { "rcx", &builtin_type_int64 },
+ { "rdx", &builtin_type_int64 },
+ { "rsi", &builtin_type_int64 },
+ { "rdi", &builtin_type_int64 },
+ { "rbp", &builtin_type_void_data_ptr },
+ { "rsp", &builtin_type_void_data_ptr },
+
+ /* %r8 is indeed register number 8. */
+ { "r8", &builtin_type_int64 },
+ { "r9", &builtin_type_int64 },
+ { "r10", &builtin_type_int64 },
+ { "r11", &builtin_type_int64 },
+ { "r12", &builtin_type_int64 },
+ { "r13", &builtin_type_int64 },
+ { "r14", &builtin_type_int64 },
+ { "r15", &builtin_type_int64 },
+ { "rip", &builtin_type_void_func_ptr },
+ { "eflags", &builtin_type_int32 },
+ { "ds", &builtin_type_int32 },
+ { "es", &builtin_type_int32 },
+ { "fs", &builtin_type_int32 },
+ { "gs", &builtin_type_int32 },
+
+ /* %st0 is register number 22. */
+ { "st0", &builtin_type_i387_ext },
+ { "st1", &builtin_type_i387_ext },
+ { "st2", &builtin_type_i387_ext },
+ { "st3", &builtin_type_i387_ext },
+ { "st4", &builtin_type_i387_ext },
+ { "st5", &builtin_type_i387_ext },
+ { "st6", &builtin_type_i387_ext },
+ { "st7", &builtin_type_i387_ext },
+ { "fctrl", &builtin_type_int32 },
+ { "fstat", &builtin_type_int32 },
+ { "ftag", &builtin_type_int32 },
+ { "fiseg", &builtin_type_int32 },
+ { "fioff", &builtin_type_int32 },
+ { "foseg", &builtin_type_int32 },
+ { "fooff", &builtin_type_int32 },
+ { "fop", &builtin_type_int32 },
+
+ /* %xmm0 is register number 38. */
+ { "xmm0", &builtin_type_v4sf },
+ { "xmm1", &builtin_type_v4sf },
+ { "xmm2", &builtin_type_v4sf },
+ { "xmm3", &builtin_type_v4sf },
+ { "xmm4", &builtin_type_v4sf },
+ { "xmm5", &builtin_type_v4sf },
+ { "xmm6", &builtin_type_v4sf },
+ { "xmm7", &builtin_type_v4sf },
+ { "xmm8", &builtin_type_v4sf },
+ { "xmm9", &builtin_type_v4sf },
+ { "xmm10", &builtin_type_v4sf },
+ { "xmm11", &builtin_type_v4sf },
+ { "xmm12", &builtin_type_v4sf },
+ { "xmm13", &builtin_type_v4sf },
+ { "xmm14", &builtin_type_v4sf },
+ { "xmm15", &builtin_type_v4sf },
+ { "mxcsr", &builtin_type_int32 }
};
-static int x86_64_dwarf2gdb_regno_map_length =
- sizeof (x86_64_dwarf2gdb_regno_map) /
- sizeof (x86_64_dwarf2gdb_regno_map[0]);
-
-/* Number of all registers */
-#define X86_64_NUM_REGS (sizeof (x86_64_register_info_table) / \
- sizeof (x86_64_register_info_table[0]))
-
-/* Number of general registers. */
-#define X86_64_NUM_GREGS (22)
+/* Total number of registers. */
+#define X86_64_NUM_REGS \
+ (sizeof (x86_64_register_info) / sizeof (x86_64_register_info[0]))
-int x86_64_num_regs = X86_64_NUM_REGS;
-int x86_64_num_gregs = X86_64_NUM_GREGS;
+/* Return the name of register REGNUM. */
-/* Did we already print a note about frame pointer? */
-int omit_fp_note_printed = 0;
-
-/* Number of bytes of storage in the actual machine representation for
- register REGNO. */
-int
-x86_64_register_raw_size (int regno)
+static const char *
+x86_64_register_name (int regnum)
{
- return x86_64_register_info_table[regno].size;
-}
-
-/* x86_64_register_byte_table[i] is the offset into the register file of the
- start of register number i. We initialize this from
- x86_64_register_info_table. */
-int x86_64_register_byte_table[X86_64_NUM_REGS];
+ if (regnum >= 0 && regnum < X86_64_NUM_REGS)
+ return x86_64_register_info[regnum].name;
-/* Index within `registers' of the first byte of the space for register REGNO. */
-int
-x86_64_register_byte (int regno)
-{
- return x86_64_register_byte_table[regno];
+ return NULL;
}
/* Return the GDB type object for the "standard" data type of data in
- register N. */
-static struct type *
-x86_64_register_virtual_type (int regno)
-{
- return *x86_64_register_info_table[regno].type;
-}
-
-/* x86_64_register_convertible is true if register N's virtual format is
- different from its raw format. Note that this definition assumes
- that the host supports IEEE 32-bit floats, since it doesn't say
- that SSE registers need conversion. Even if we can't find a
- counterexample, this is still sloppy. */
-int
-x86_64_register_convertible (int regno)
-{
- return IS_FP_REGNUM (regno);
-}
+ register REGNUM. */
-/* Convert data from raw format for register REGNUM in buffer FROM to
- virtual format with type TYPE in buffer TO. In principle both
- formats are identical except that the virtual format has two extra
- bytes appended that aren't used. We set these to zero. */
-void
-x86_64_register_convert_to_virtual (int regnum, struct type *type,
- char *from, char *to)
+static struct type *
+x86_64_register_type (struct gdbarch *gdbarch, int regnum)
{
- char buf[12];
+ gdb_assert (regnum >= 0 && regnum < X86_64_NUM_REGS);
- /* We only support floating-point values. */
- if (TYPE_CODE (type) != TYPE_CODE_FLT)
- {
- warning ("Cannot convert floating-point register value "
- "to non-floating-point type.");
- memset (to, 0, TYPE_LENGTH (type));
- return;
- }
- /* First add the necessary padding. */
- memcpy (buf, from, FPU_REG_RAW_SIZE);
- memset (buf + FPU_REG_RAW_SIZE, 0, sizeof buf - FPU_REG_RAW_SIZE);
- /* Convert to TYPE. This should be a no-op, if TYPE is equivalent
- to the extended floating-point format used by the FPU. */
- convert_typed_floating (to, type, buf,
- x86_64_register_virtual_type (regnum));
+ return *x86_64_register_info[regnum].type;
}
-/* Convert data from virtual format with type TYPE in buffer FROM to
- raw format for register REGNUM in buffer TO. Simply omit the two
- unused bytes. */
+/* DWARF Register Number Mapping as defined in the System V psABI,
+ section 3.6. */
-void
-x86_64_register_convert_to_raw (struct type *type, int regnum,
- char *from, char *to)
+static int x86_64_dwarf_regmap[] =
{
- gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 12);
- /* Simply omit the two unused bytes. */
- memcpy (to, from, FPU_REG_RAW_SIZE);
-}
+ /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
+ X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, 2, 1,
+ 4, X86_64_RDI_REGNUM,
+
+ /* Frame Pointer Register RBP. */
+ X86_64_RBP_REGNUM,
+
+ /* Stack Pointer Register RSP. */
+ X86_64_RSP_REGNUM,
+
+ /* Extended Integer Registers 8 - 15. */
+ 8, 9, 10, 11, 12, 13, 14, 15,
+
+ /* Return Address RA. Not mapped. */
+ -1,
+
+ /* SSE Registers 0 - 7. */
+ X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
+ X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
+ X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
+ X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
+
+ /* Extended SSE Registers 8 - 15. */
+ X86_64_XMM0_REGNUM + 8, X86_64_XMM0_REGNUM + 9,
+ X86_64_XMM0_REGNUM + 10, X86_64_XMM0_REGNUM + 11,
+ X86_64_XMM0_REGNUM + 12, X86_64_XMM0_REGNUM + 13,
+ X86_64_XMM0_REGNUM + 14, X86_64_XMM0_REGNUM + 15,
+
+ /* Floating Point Registers 0-7. */
+ X86_64_ST0_REGNUM + 0, X86_64_ST0_REGNUM + 1,
+ X86_64_ST0_REGNUM + 2, X86_64_ST0_REGNUM + 3,
+ X86_64_ST0_REGNUM + 4, X86_64_ST0_REGNUM + 5,
+ X86_64_ST0_REGNUM + 6, X86_64_ST0_REGNUM + 7
+};
-/* Dwarf-2 <-> GDB register numbers mapping. */
-int
-x86_64_dwarf2_reg_to_regnum (int dw_reg)
-{
- if (dw_reg < 0 || dw_reg > x86_64_dwarf2gdb_regno_map_length)
- {
- warning ("Dwarf-2 uses unmapped register #%d\n", dw_reg);
- return dw_reg;
- }
+static const int x86_64_dwarf_regmap_len =
+ (sizeof (x86_64_dwarf_regmap) / sizeof (x86_64_dwarf_regmap[0]));
- return x86_64_dwarf2gdb_regno_map[dw_reg];
-}
+/* Convert DWARF register number REG to the appropriate register
+ number used by GDB. */
-/* This is the variable that is set with "set disassembly-flavour", and
- its legitimate values. */
-static const char att_flavour[] = "att";
-static const char intel_flavour[] = "intel";
-static const char *valid_flavours[] = {
- att_flavour,
- intel_flavour,
- NULL
-};
-static const char *disassembly_flavour = att_flavour;
+static int
+x86_64_dwarf_reg_to_regnum (int reg)
+{
+ int regnum = -1;
-/* Push the return address (pointing to the call dummy) onto the stack
- and return the new value for the stack pointer. */
+ if (reg >= 0 || reg < x86_64_dwarf_regmap_len)
+ regnum = x86_64_dwarf_regmap[reg];
-static CORE_ADDR
-x86_64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
-{
- char buf[8];
+ if (regnum == -1)
+ warning ("Unmapped DWARF Register #%d encountered\n", reg);
- store_unsigned_integer (buf, 8, CALL_DUMMY_ADDRESS ());
- write_memory (sp - 8, buf, 8);
- return sp - 8;
+ return regnum;
}
-static void
-x86_64_pop_frame (void)
+/* Return nonzero if a value of type TYPE stored in register REGNUM
+ needs any special handling. */
+
+static int
+x86_64_convert_register_p (int regnum, struct type *type)
{
- generic_pop_current_frame (cfi_pop_frame);
+ return i386_fp_regnum_p (regnum);
}
\f
/* The returning of values is done according to the special algorithm.
- Some types are returned in registers an some (big structures) in memory.
- See ABI for details.
- */
+ Some types are returned in registers an some (big structures) in
+ memory. See the System V psABI for details. */
#define MAX_CLASSES 4
};
/* Return the union class of CLASS1 and CLASS2.
- See the x86-64 ABI for details. */
+ See the System V psABI for details. */
static enum x86_64_reg_class
merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
{
- /* Rule #1: If both classes are equal, this is the resulting class. */
+ /* Rule (a): If both classes are equal, this is the resulting class. */
if (class1 == class2)
return class1;
- /* Rule #2: If one of the classes is NO_CLASS, the resulting class
+ /* Rule (b): If one of the classes is NO_CLASS, the resulting class
is the other class. */
if (class1 == X86_64_NO_CLASS)
return class2;
if (class2 == X86_64_NO_CLASS)
return class1;
- /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
+ /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
return X86_64_MEMORY_CLASS;
- /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
+ /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
|| (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
return X86_64_INTEGERSI_CLASS;
|| class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
return X86_64_INTEGER_CLASS;
- /* Rule #5: If one of the classes is X87 or X87UP class, MEMORY is used. */
+ /* Rule (e): If one of the classes is X87 or X87UP class, MEMORY is
+ used as class. */
if (class1 == X86_64_X87_CLASS || class1 == X86_64_X87UP_CLASS
|| class2 == X86_64_X87_CLASS || class2 == X86_64_X87UP_CLASS)
return X86_64_MEMORY_CLASS;
- /* Rule #6: Otherwise class SSE is used. */
+ /* Rule (f): Otherwise class SSE is used. */
return X86_64_SSE_CLASS;
}
is returned. As a special case for zero sized containers,
classes[0] will be NO_CLASS and 1 is returned.
- See the x86-64 psABI for details. */
+ See the System V psABI for details. */
static int
classify_argument (struct type *type,
return 1;
}
-#define RET_INT_REGS 2
-#define RET_SSE_REGS 2
-
-/* Check if the structure in value_type is returned in registers or in
- memory. If this function returns 1, GDB will call
- STORE_STRUCT_RETURN and EXTRACT_STRUCT_VALUE_ADDRESS else
- STORE_RETURN_VALUE and EXTRACT_RETURN_VALUE will be used. */
-int
-x86_64_use_struct_convention (int gcc_p, struct type *value_type)
-{
- enum x86_64_reg_class class[MAX_CLASSES];
- int n = classify_argument (value_type, class, 0);
- int needed_intregs;
- int needed_sseregs;
-
- return (!n ||
- !examine_argument (class, n, &needed_intregs, &needed_sseregs) ||
- needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS);
-}
-
-/* Extract from an array REGBUF containing the (raw) register state, a
- function return value of TYPE, and copy that, in virtual format,
- into VALBUF. */
-
-void
-x86_64_extract_return_value (struct type *type, struct regcache *regcache,
- void *valbuf)
-{
- enum x86_64_reg_class class[MAX_CLASSES];
- int n = classify_argument (type, class, 0);
- int needed_intregs;
- int needed_sseregs;
- int intreg = 0;
- int ssereg = 0;
- int offset = 0;
- int ret_int_r[RET_INT_REGS] = { RAX_REGNUM, RDX_REGNUM };
- int ret_sse_r[RET_SSE_REGS] = { XMM0_REGNUM, XMM1_REGNUM };
-
- if (!n ||
- !examine_argument (class, n, &needed_intregs, &needed_sseregs) ||
- needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS)
- { /* memory class */
- CORE_ADDR addr;
- regcache_cooked_read (regcache, RAX_REGNUM, &addr);
- read_memory (addr, valbuf, TYPE_LENGTH (type));
- return;
- }
- else
- {
- int i;
- for (i = 0; i < n; i++)
- {
- switch (class[i])
- {
- case X86_64_NO_CLASS:
- break;
- case X86_64_INTEGER_CLASS:
- regcache_cooked_read (regcache, ret_int_r[(intreg + 1) / 2],
- (char *) valbuf + offset);
- offset += 8;
- intreg += 2;
- break;
- case X86_64_INTEGERSI_CLASS:
- regcache_cooked_read_part (regcache, ret_int_r[intreg / 2],
- 0, 4, (char *) valbuf + offset);
- offset += 8;
- intreg++;
- break;
- case X86_64_SSEDF_CLASS:
- case X86_64_SSESF_CLASS:
- case X86_64_SSE_CLASS:
- regcache_cooked_read_part (regcache,
- ret_sse_r[(ssereg + 1) / 2], 0, 8,
- (char *) valbuf + offset);
- offset += 8;
- ssereg += 2;
- break;
- case X86_64_SSEUP_CLASS:
- regcache_cooked_read_part (regcache, ret_sse_r[ssereg / 2],
- 0, 8, (char *) valbuf + offset);
- offset += 8;
- ssereg++;
- break;
- case X86_64_X87_CLASS:
- regcache_cooked_read_part (regcache, FP0_REGNUM,
- 0, 8, (char *) valbuf + offset);
- offset += 8;
- break;
- case X86_64_X87UP_CLASS:
- regcache_cooked_read_part (regcache, FP0_REGNUM,
- 8, 2, (char *) valbuf + offset);
- offset += 8;
- break;
- case X86_64_MEMORY_CLASS:
- default:
- internal_error (__FILE__, __LINE__,
- "Unexpected argument class");
- }
- }
- }
-}
-
-static void
-x86_64_frame_init_saved_regs (struct frame_info *fi)
-{
- /* Do nothing. Everything is handled by the stack unwinding code. */
-}
-
#define INT_REGS 6
-#define SSE_REGS 16
+#define SSE_REGS 8
-CORE_ADDR
-x86_64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
- int struct_return, CORE_ADDR struct_addr)
+static CORE_ADDR
+x86_64_push_arguments (struct regcache *regcache, int nargs,
+ struct value **args, CORE_ADDR sp)
{
int intreg = 0;
int ssereg = 0;
+ /* For varargs functions we have to pass the total number of SSE
+ registers used in %rax. So, let's count this number. */
+ int total_sse_args = 0;
+ /* Once an SSE/int argument is passed on the stack, all subsequent
+ arguments are passed there. */
+ int sse_stack = 0;
+ int int_stack = 0;
+ unsigned total_sp;
int i;
- static int int_parameter_registers[INT_REGS] = {
- 5 /* RDI */ , 4 /* RSI */ ,
- 3 /* RDX */ , 2 /* RCX */ ,
- 8 /* R8 */ , 9 /* R9 */
+ char buf[8];
+ static int int_parameter_registers[INT_REGS] =
+ {
+ X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */
+ X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */
+ 8, 9 /* %r8, %r9 */
};
- /* XMM0 - XMM15 */
- static int sse_parameter_registers[SSE_REGS] = {
- XMM1_REGNUM - 1, XMM1_REGNUM, XMM1_REGNUM + 1, XMM1_REGNUM + 2,
- XMM1_REGNUM + 3, XMM1_REGNUM + 4, XMM1_REGNUM + 5, XMM1_REGNUM + 6,
- XMM1_REGNUM + 7, XMM1_REGNUM + 8, XMM1_REGNUM + 9, XMM1_REGNUM + 10,
- XMM1_REGNUM + 11, XMM1_REGNUM + 12, XMM1_REGNUM + 13, XMM1_REGNUM + 14
+ /* %xmm0 - %xmm7 */
+ static int sse_parameter_registers[SSE_REGS] =
+ {
+ X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
+ X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
+ X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
+ X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
};
int stack_values_count = 0;
int *stack_values;
stack_values = alloca (nargs * sizeof (int));
+
for (i = 0; i < nargs; i++)
{
enum x86_64_reg_class class[MAX_CLASSES];
int needed_sseregs;
if (!n ||
- !examine_argument (class, n, &needed_intregs, &needed_sseregs)
- || intreg / 2 + needed_intregs > INT_REGS
- || ssereg / 2 + needed_sseregs > SSE_REGS)
+ !examine_argument (class, n, &needed_intregs, &needed_sseregs))
{ /* memory class */
stack_values[stack_values_count++] = i;
}
else
{
int j;
+ int offset = 0;
+
+ if (intreg / 2 + needed_intregs > INT_REGS)
+ int_stack = 1;
+ if (ssereg / 2 + needed_sseregs > SSE_REGS)
+ sse_stack = 1;
+ if (!sse_stack)
+ total_sse_args += needed_sseregs;
+
for (j = 0; j < n; j++)
{
- int offset = 0;
switch (class[j])
{
case X86_64_NO_CLASS:
break;
case X86_64_INTEGER_CLASS:
- deprecated_write_register_gen (int_parameter_registers
- [(intreg + 1) / 2],
- VALUE_CONTENTS_ALL (args[i]) + offset);
- offset += 8;
- intreg += 2;
+ if (int_stack)
+ stack_values[stack_values_count++] = i;
+ else
+ {
+ regcache_cooked_write
+ (regcache, int_parameter_registers[(intreg + 1) / 2],
+ VALUE_CONTENTS_ALL (args[i]) + offset);
+ offset += 8;
+ intreg += 2;
+ }
break;
case X86_64_INTEGERSI_CLASS:
- {
- LONGEST num
- = extract_signed_integer (VALUE_CONTENTS_ALL (args[i])
- + offset, 4);
- regcache_raw_write_signed (current_regcache,
- int_parameter_registers[intreg / 2], num);
-
- offset += 8;
- intreg++;
- break;
- }
+ if (int_stack)
+ stack_values[stack_values_count++] = i;
+ else
+ {
+ LONGEST val = extract_signed_integer
+ (VALUE_CONTENTS_ALL (args[i]) + offset, 4);
+ regcache_cooked_write_signed
+ (regcache, int_parameter_registers[intreg / 2], val);
+
+ offset += 8;
+ intreg++;
+ }
+ break;
case X86_64_SSEDF_CLASS:
case X86_64_SSESF_CLASS:
case X86_64_SSE_CLASS:
- deprecated_write_register_gen (sse_parameter_registers
- [(ssereg + 1) / 2],
- VALUE_CONTENTS_ALL (args[i]) + offset);
- offset += 8;
- ssereg += 2;
+ if (sse_stack)
+ stack_values[stack_values_count++] = i;
+ else
+ {
+ regcache_cooked_write
+ (regcache, sse_parameter_registers[(ssereg + 1) / 2],
+ VALUE_CONTENTS_ALL (args[i]) + offset);
+ offset += 8;
+ ssereg += 2;
+ }
break;
case X86_64_SSEUP_CLASS:
- deprecated_write_register_gen (sse_parameter_registers[ssereg / 2],
- VALUE_CONTENTS_ALL (args[i]) + offset);
- offset += 8;
- ssereg++;
+ if (sse_stack)
+ stack_values[stack_values_count++] = i;
+ else
+ {
+ regcache_cooked_write
+ (regcache, sse_parameter_registers[ssereg / 2],
+ VALUE_CONTENTS_ALL (args[i]) + offset);
+ offset += 8;
+ ssereg++;
+ }
break;
case X86_64_X87_CLASS:
case X86_64_MEMORY_CLASS:
}
}
}
+
+ /* We have to make sure that the stack is 16-byte aligned after the
+ setup. Let's calculate size of arguments first, align stack and
+ then fill in the arguments. */
+ total_sp = 0;
+ for (i = 0; i < stack_values_count; i++)
+ {
+ struct value *arg = args[stack_values[i]];
+ int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg));
+ total_sp += (len + 7) & ~7;
+ }
+ /* total_sp is now a multiple of 8, if it is not a multiple of 16,
+ change the stack pointer so that it will be afterwards correctly
+ aligned. */
+ if (total_sp & 15)
+ sp -= 8;
+
+ /* Push any remaining arguments onto the stack. */
while (--stack_values_count >= 0)
{
struct value *arg = args[stack_values[stack_values_count]];
int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg));
- len += 7;
- len -= len % 8;
- sp -= len;
+
+ /* Make sure the stack is 8-byte-aligned. */
+ sp -= (len + 7) & ~7;
write_memory (sp, VALUE_CONTENTS_ALL (arg), len);
}
+
+ /* Write number of SSE type arguments to RAX to take care of varargs
+ functions. */
+ store_unsigned_integer (buf, 8, total_sse_args);
+ regcache_cooked_write (regcache, X86_64_RAX_REGNUM, buf);
+
return sp;
}
-/* Write into the appropriate registers a function return value stored
- in VALBUF of type TYPE, given in virtual format. */
-void
-x86_64_store_return_value (struct type *type, struct regcache *regcache,
- const void *valbuf)
+/* Register classes as defined in the psABI. */
+
+enum amd64_reg_class
+{
+ AMD64_INTEGER,
+ AMD64_SSE,
+ AMD64_SSEUP,
+ AMD64_X87,
+ AMD64_X87UP,
+ AMD64_COMPLEX_X87,
+ AMD64_NO_CLASS,
+ AMD64_MEMORY
+};
+
+/* Return the union class of CLASS1 and CLASS2. See the psABI for
+ details. */
+
+static enum amd64_reg_class
+amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
+{
+ /* Rule (a): If both classes are equal, this is the resulting class. */
+ if (class1 == class2)
+ return class1;
+
+ /* Rule (b): If one of the classes is NO_CLASS, the resulting class
+ is the other class. */
+ if (class1 == AMD64_NO_CLASS)
+ return class2;
+ if (class2 == AMD64_NO_CLASS)
+ return class1;
+
+ /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
+ if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
+ return AMD64_MEMORY;
+
+ /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
+ if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
+ return AMD64_INTEGER;
+
+ /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
+ MEMORY is used as class. */
+ if (class1 == AMD64_X87 || class1 == AMD64_X87UP
+ || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
+ || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
+ return AMD64_MEMORY;
+
+ /* Rule (f): Otherwise class SSE is used. */
+ return AMD64_SSE;
+}
+
+static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
+
+/* Classify TYPE according to the rules for aggregate (structures and
+ arrays) and union types, and store the result in CLASS. */
+
+static void
+amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
{
int len = TYPE_LENGTH (type);
- if (TYPE_CODE_FLT == TYPE_CODE (type))
+ /* 1. If the size of an object is larger than two eightbytes, or in
+ C++, is a non-POD structure or union type, or contains
+ unaligned fields, it has class memory. */
+ if (len > 16)
{
- /* Floating-point return values can be found in %st(0). */
- if (len == TARGET_LONG_DOUBLE_BIT / TARGET_CHAR_BIT
- && TARGET_LONG_DOUBLE_FORMAT == &floatformat_i387_ext)
- {
- /* Copy straight over. */
- regcache_cooked_write (regcache, FP0_REGNUM, valbuf);
- }
- else
+ class[0] = class[1] = AMD64_MEMORY;
+ return;
+ }
+
+ /* 2. Both eightbytes get initialized to class NO_CLASS. */
+ class[0] = class[1] = AMD64_NO_CLASS;
+
+ /* 3. Each field of an object is classified recursively so that
+ always two fields are considered. The resulting class is
+ calculated according to the classes of the fields in the
+ eightbyte: */
+
+ if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
+ {
+ struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
+
+ /* All fields in an array have the same type. */
+ amd64_classify (subtype, class);
+ if (len > 8 && class[1] == AMD64_NO_CLASS)
+ class[1] = class[0];
+ }
+ else
+ {
+ int i;
+
+ /* Structure or union. */
+ gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
+ || TYPE_CODE (type) == TYPE_CODE_UNION);
+
+ for (i = 0; i < TYPE_NFIELDS (type); i++)
{
- char buf[FPU_REG_RAW_SIZE];
- DOUBLEST val;
-
- /* Convert the value found in VALBUF to the extended
- floating point format used by the FPU. This is probably
- not exactly how it would happen on the target itself, but
- it is the best we can do. */
- val = deprecated_extract_floating (valbuf, TYPE_LENGTH (type));
- floatformat_from_doublest (&floatformat_i387_ext, &val, buf);
- regcache_cooked_write_part (regcache, FP0_REGNUM,
- 0, FPU_REG_RAW_SIZE, buf);
+ struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
+ int pos = TYPE_FIELD_BITPOS (type, i) / 64;
+ enum amd64_reg_class subclass[2];
+
+ gdb_assert (pos == 0 || pos == 1);
+
+ amd64_classify (subtype, subclass);
+ class[pos] = amd64_merge_classes (class[pos], subclass[0]);
+ if (pos == 0)
+ class[1] = amd64_merge_classes (class[1], subclass[1]);
}
}
- else
+
+ /* 4. Then a post merger cleanup is done: */
+
+ /* Rule (a): If one of the classes is MEMORY, the whole argument is
+ passed in memory. */
+ if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
+ class[0] = class[1] = AMD64_MEMORY;
+
+ /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
+ SSE. */
+ if (class[0] == AMD64_SSEUP)
+ class[0] = AMD64_SSE;
+ if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
+ class[1] = AMD64_SSE;
+}
+
+/* Classify TYPE, and store the result in CLASS. */
+
+static void
+amd64_classify (struct type *type, enum amd64_reg_class class[2])
+{
+ enum type_code code = TYPE_CODE (type);
+ int len = TYPE_LENGTH (type);
+
+ class[0] = class[1] = AMD64_NO_CLASS;
+
+ /* Arguments of types (signed and unsigned) _Bool, char, short, int,
+ long, long long, and pointers are in the INTEGER class. */
+ if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
+ || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
+ && (len == 1 || len == 2 || len == 4 || len == 8))
+ class[0] = AMD64_INTEGER;
+
+ /* Arguments of types float, double and __m64 are in class SSE. */
+ else if (code == TYPE_CODE_FLT && (len == 4 || len == 8))
+ /* FIXME: __m64 . */
+ class[0] = AMD64_SSE;
+
+ /* Arguments of types __float128 and __m128 are split into two
+ halves. The least significant ones belong to class SSE, the most
+ significant one to class SSEUP. */
+ /* FIXME: __float128, __m128. */
+
+ /* The 64-bit mantissa of arguments of type long double belongs to
+ class X87, the 16-bit exponent plus 6 bytes of padding belongs to
+ class X87UP. */
+ else if (code == TYPE_CODE_FLT && len == 16)
+ /* Class X87 and X87UP. */
+ class[0] = AMD64_X87, class[1] = AMD64_X87UP;
+
+ /* Aggregates. */
+ else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
+ || code == TYPE_CODE_UNION)
+ amd64_classify_aggregate (type, class);
+}
+
+static enum return_value_convention
+amd64_return_value (struct gdbarch *gdbarch, struct type *type,
+ struct regcache *regcache,
+ void *readbuf, const void *writebuf)
+{
+ enum amd64_reg_class class[2];
+ int len = TYPE_LENGTH (type);
+ static int integer_regnum[] = { X86_64_RAX_REGNUM, X86_64_RDX_REGNUM };
+ static int sse_regnum[] = { X86_64_XMM0_REGNUM, X86_64_XMM1_REGNUM };
+ int integer_reg = 0;
+ int sse_reg = 0;
+ int i;
+
+ gdb_assert (!(readbuf && writebuf));
+
+ /* 1. Classify the return type with the classification algorithm. */
+ amd64_classify (type, class);
+
+ /* 2. If the type has class MEMORY, then the caller provides space
+ for the return value and passes the address of this storage in
+ %rdi as if it were the first argument to the function. In
+ effect, this address becomes a hidden first argument. */
+ if (class[0] == AMD64_MEMORY)
+ return RETURN_VALUE_STRUCT_CONVENTION;
+
+ gdb_assert (class[1] != AMD64_MEMORY);
+ gdb_assert (len <= 16);
+
+ for (i = 0; len > 0; i++, len -= 8)
{
- int low_size = REGISTER_RAW_SIZE (0);
- int high_size = REGISTER_RAW_SIZE (1);
+ int regnum = -1;
+ int offset = 0;
- if (len <= low_size)
- regcache_cooked_write_part (regcache, 0, 0, len, valbuf);
- else if (len <= (low_size + high_size))
+ switch (class[i])
{
- regcache_cooked_write_part (regcache, 0, 0, low_size, valbuf);
- regcache_cooked_write_part (regcache, 1, 0,
- len - low_size,
- (const char *) valbuf + low_size);
+ case AMD64_INTEGER:
+ /* 3. If the class is INTEGER, the next available register
+ of the sequence %rax, %rdx is used. */
+ regnum = integer_regnum[integer_reg++];
+ break;
+
+ case AMD64_SSE:
+ /* 4. If the class is SSE, the next available SSE register
+ of the sequence %xmm0, %xmm1 is used. */
+ regnum = sse_regnum[sse_reg++];
+ break;
+
+ case AMD64_SSEUP:
+ /* 5. If the class is SSEUP, the eightbyte is passed in the
+ upper half of the last used SSE register. */
+ gdb_assert (sse_reg > 0);
+ regnum = sse_regnum[sse_reg - 1];
+ offset = 8;
+ break;
+
+ case AMD64_X87:
+ /* 6. If the class is X87, the value is returned on the X87
+ stack in %st0 as 80-bit x87 number. */
+ regnum = X86_64_ST0_REGNUM;
+ if (writebuf)
+ i387_return_value (gdbarch, regcache);
+ break;
+
+ case AMD64_X87UP:
+ /* 7. If the class is X87UP, the value is returned together
+ with the previous X87 value in %st0. */
+ gdb_assert (i > 0 && class[0] == AMD64_X87);
+ regnum = X86_64_ST0_REGNUM;
+ offset = 8;
+ len = 2;
+ break;
+
+ case AMD64_NO_CLASS:
+ continue;
+
+ default:
+ gdb_assert (!"Unexpected register class.");
}
- else
- internal_error (__FILE__, __LINE__,
- "Cannot store return value of %d bytes long.", len);
+
+ gdb_assert (regnum != -1);
+
+ if (readbuf)
+ regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
+ (char *) readbuf + i * 8);
+ if (writebuf)
+ regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
+ (const char *) writebuf + i * 8);
}
+
+ return RETURN_VALUE_REGISTER_CONVENTION;
}
\f
-const char *
-x86_64_register_name (int reg_nr)
+static CORE_ADDR
+x86_64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
+ struct regcache *regcache, CORE_ADDR bp_addr,
+ int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
{
- if (reg_nr < 0 || reg_nr >= X86_64_NUM_REGS)
- return NULL;
- return x86_64_register_info_table[reg_nr].name;
+ char buf[8];
+
+ /* Pass arguments. */
+ sp = x86_64_push_arguments (regcache, nargs, args, sp);
+
+ /* Pass "hidden" argument". */
+ if (struct_return)
+ {
+ store_unsigned_integer (buf, 8, struct_addr);
+ regcache_cooked_write (regcache, X86_64_RDI_REGNUM, buf);
+ }
+
+ /* Store return address. */
+ sp -= 8;
+ store_unsigned_integer (buf, 8, bp_addr);
+ write_memory (sp, buf, 8);
+
+ /* Finally, update the stack pointer... */
+ store_unsigned_integer (buf, 8, sp);
+ regcache_cooked_write (regcache, X86_64_RSP_REGNUM, buf);
+
+ /* ...and fake a frame pointer. */
+ regcache_cooked_write (regcache, X86_64_RBP_REGNUM, buf);
+
+ return sp + 16;
}
+\f
+
+/* The maximum number of saved registers. This should include %rip. */
+#define X86_64_NUM_SAVED_REGS X86_64_NUM_GREGS
-int
-x86_64_register_number (const char *name)
+struct x86_64_frame_cache
{
- int reg_nr;
+ /* Base address. */
+ CORE_ADDR base;
+ CORE_ADDR sp_offset;
+ CORE_ADDR pc;
+
+ /* Saved registers. */
+ CORE_ADDR saved_regs[X86_64_NUM_SAVED_REGS];
+ CORE_ADDR saved_sp;
+
+ /* Do we have a frame? */
+ int frameless_p;
+};
+
+/* Allocate and initialize a frame cache. */
+
+static struct x86_64_frame_cache *
+x86_64_alloc_frame_cache (void)
+{
+ struct x86_64_frame_cache *cache;
+ int i;
+
+ cache = FRAME_OBSTACK_ZALLOC (struct x86_64_frame_cache);
- for (reg_nr = 0; reg_nr < X86_64_NUM_REGS; reg_nr++)
- if (strcmp (name, x86_64_register_info_table[reg_nr].name) == 0)
- return reg_nr;
- return -1;
+ /* Base address. */
+ cache->base = 0;
+ cache->sp_offset = -8;
+ cache->pc = 0;
+
+ /* Saved registers. We initialize these to -1 since zero is a valid
+ offset (that's where %rbp is supposed to be stored). */
+ for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
+ cache->saved_regs[i] = -1;
+ cache->saved_sp = 0;
+
+ /* Frameless until proven otherwise. */
+ cache->frameless_p = 1;
+
+ return cache;
}
-\f
+/* Do a limited analysis of the prologue at PC and update CACHE
+ accordingly. Bail out early if CURRENT_PC is reached. Return the
+ address where the analysis stopped.
-/* We have two flavours of disassembly. The machinery on this page
- deals with switching between those. */
+ We will handle only functions beginning with:
-static int
-gdb_print_insn_x86_64 (bfd_vma memaddr, disassemble_info * info)
+ pushq %rbp 0x55
+ movq %rsp, %rbp 0x48 0x89 0xe5
+
+ Any function that doesn't start with this sequence will be assumed
+ to have no prologue and thus no valid frame pointer in %rbp. */
+
+static CORE_ADDR
+x86_64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
+ struct x86_64_frame_cache *cache)
{
- if (disassembly_flavour == att_flavour)
- return print_insn_i386_att (memaddr, info);
- else if (disassembly_flavour == intel_flavour)
- return print_insn_i386_intel (memaddr, info);
- /* Never reached -- disassembly_flavour is always either att_flavour
- or intel_flavour. */
- internal_error (__FILE__, __LINE__, "failed internal consistency check");
+ static unsigned char proto[3] = { 0x48, 0x89, 0xe5 };
+ unsigned char buf[3];
+ unsigned char op;
+
+ if (current_pc <= pc)
+ return current_pc;
+
+ op = read_memory_unsigned_integer (pc, 1);
+
+ if (op == 0x55) /* pushq %rbp */
+ {
+ /* Take into account that we've executed the `pushq %rbp' that
+ starts this instruction sequence. */
+ cache->saved_regs[X86_64_RBP_REGNUM] = 0;
+ cache->sp_offset += 8;
+
+ /* If that's all, return now. */
+ if (current_pc <= pc + 1)
+ return current_pc;
+
+ /* Check for `movq %rsp, %rbp'. */
+ read_memory (pc + 1, buf, 3);
+ if (memcmp (buf, proto, 3) != 0)
+ return pc + 1;
+
+ /* OK, we actually have a frame. */
+ cache->frameless_p = 0;
+ return pc + 4;
+ }
+
+ return pc;
+}
+
+/* Return PC of first real instruction. */
+
+static CORE_ADDR
+x86_64_skip_prologue (CORE_ADDR start_pc)
+{
+ struct x86_64_frame_cache cache;
+ CORE_ADDR pc;
+
+ pc = x86_64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache);
+ if (cache.frameless_p)
+ return start_pc;
+
+ return pc;
}
\f
-/* Store the address of the place in which to copy the structure the
- subroutine will return. This is called from call_function. */
-void
-x86_64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
+/* Normal frames. */
+
+static struct x86_64_frame_cache *
+x86_64_frame_cache (struct frame_info *next_frame, void **this_cache)
{
- write_register (RDI_REGNUM, addr);
+ struct x86_64_frame_cache *cache;
+ char buf[8];
+ int i;
+
+ if (*this_cache)
+ return *this_cache;
+
+ cache = x86_64_alloc_frame_cache ();
+ *this_cache = cache;
+
+ cache->pc = frame_func_unwind (next_frame);
+ if (cache->pc != 0)
+ x86_64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
+
+ if (cache->frameless_p)
+ {
+ /* We didn't find a valid frame, which means that CACHE->base
+ currently holds the frame pointer for our calling frame. If
+ we're at the start of a function, or somewhere half-way its
+ prologue, the function's frame probably hasn't been fully
+ setup yet. Try to reconstruct the base address for the stack
+ frame by looking at the stack pointer. For truly "frameless"
+ functions this might work too. */
+
+ frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
+ cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
+ }
+ else
+ {
+ frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
+ cache->base = extract_unsigned_integer (buf, 8);
+ }
+
+ /* Now that we have the base address for the stack frame we can
+ calculate the value of %rsp in the calling frame. */
+ cache->saved_sp = cache->base + 16;
+
+ /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
+ frame we find it at the same offset from the reconstructed base
+ address. */
+ cache->saved_regs[X86_64_RIP_REGNUM] = 8;
+
+ /* Adjust all the saved registers such that they contain addresses
+ instead of offsets. */
+ for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
+ if (cache->saved_regs[i] != -1)
+ cache->saved_regs[i] += cache->base;
+
+ return cache;
}
-int
-x86_64_frameless_function_invocation (struct frame_info *frame)
+static void
+x86_64_frame_this_id (struct frame_info *next_frame, void **this_cache,
+ struct frame_id *this_id)
{
- return 0;
+ struct x86_64_frame_cache *cache =
+ x86_64_frame_cache (next_frame, this_cache);
+
+ /* This marks the outermost frame. */
+ if (cache->base == 0)
+ return;
+
+ (*this_id) = frame_id_build (cache->base + 16, cache->pc);
}
-/* We will handle only functions beginning with:
- 55 pushq %rbp
- 48 89 e5 movq %rsp,%rbp
- Any function that doesn't start with this sequence
- will be assumed to have no prologue and thus no valid
- frame pointer in %rbp. */
-#define PROLOG_BUFSIZE 4
-int
-x86_64_function_has_prologue (CORE_ADDR pc)
+static void
+x86_64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
+ int regnum, int *optimizedp,
+ enum lval_type *lvalp, CORE_ADDR *addrp,
+ int *realnump, void *valuep)
{
- int i;
- unsigned char prolog_expect[PROLOG_BUFSIZE] = { 0x55, 0x48, 0x89, 0xe5 },
- prolog_buf[PROLOG_BUFSIZE];
+ struct x86_64_frame_cache *cache =
+ x86_64_frame_cache (next_frame, this_cache);
- read_memory (pc, (char *) prolog_buf, PROLOG_BUFSIZE);
+ gdb_assert (regnum >= 0);
- /* First check, whether pc points to pushq %rbp, movq %rsp,%rbp. */
- for (i = 0; i < PROLOG_BUFSIZE; i++)
- if (prolog_expect[i] != prolog_buf[i])
- return 0; /* ... no, it doesn't. Nothing to skip. */
-
- return 1;
+ if (regnum == SP_REGNUM && cache->saved_sp)
+ {
+ *optimizedp = 0;
+ *lvalp = not_lval;
+ *addrp = 0;
+ *realnump = -1;
+ if (valuep)
+ {
+ /* Store the value. */
+ store_unsigned_integer (valuep, 8, cache->saved_sp);
+ }
+ return;
+ }
+
+ if (regnum < X86_64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
+ {
+ *optimizedp = 0;
+ *lvalp = lval_memory;
+ *addrp = cache->saved_regs[regnum];
+ *realnump = -1;
+ if (valuep)
+ {
+ /* Read the value in from memory. */
+ read_memory (*addrp, valuep,
+ register_size (current_gdbarch, regnum));
+ }
+ return;
+ }
+
+ frame_register_unwind (next_frame, regnum,
+ optimizedp, lvalp, addrp, realnump, valuep);
}
-/* If a function with debugging information and known beginning
- is detected, we will return pc of the next line in the source
- code. With this approach we effectively skip the prolog. */
+static const struct frame_unwind x86_64_frame_unwind =
+{
+ NORMAL_FRAME,
+ x86_64_frame_this_id,
+ x86_64_frame_prev_register
+};
-CORE_ADDR
-x86_64_skip_prologue (CORE_ADDR pc)
+static const struct frame_unwind *
+x86_64_frame_sniffer (struct frame_info *next_frame)
{
- int i;
- struct symtab_and_line v_sal;
- struct symbol *v_function;
- CORE_ADDR endaddr;
+ return &x86_64_frame_unwind;
+}
+\f
- if (! x86_64_function_has_prologue (pc))
- return pc;
+/* Signal trampolines. */
- /* OK, we have found the prologue and want PC of the first
- non-prologue instruction. */
- pc += PROLOG_BUFSIZE;
+/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
+ 64-bit variants. This would require using identical frame caches
+ on both platforms. */
+
+static struct x86_64_frame_cache *
+x86_64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
+{
+ struct x86_64_frame_cache *cache;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ CORE_ADDR addr;
+ char buf[8];
+ int i;
- v_function = find_pc_function (pc);
- v_sal = find_pc_line (pc, 0);
+ if (*this_cache)
+ return *this_cache;
- /* If pc doesn't point to a function with debuginfo, some of the
- following may be NULL. */
- if (!v_function || !v_function->ginfo.value.block || !v_sal.symtab)
- return pc;
+ cache = x86_64_alloc_frame_cache ();
- endaddr = BLOCK_END (SYMBOL_BLOCK_VALUE (v_function));
+ frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
+ cache->base = extract_unsigned_integer (buf, 8) - 8;
- for (i = 0; i < v_sal.symtab->linetable->nitems; i++)
- if (v_sal.symtab->linetable->item[i].pc >= pc
- && v_sal.symtab->linetable->item[i].pc < endaddr)
- {
- pc = v_sal.symtab->linetable->item[i].pc;
- break;
- }
+ addr = tdep->sigcontext_addr (next_frame);
+ gdb_assert (tdep->sc_reg_offset);
+ gdb_assert (tdep->sc_num_regs <= X86_64_NUM_SAVED_REGS);
+ for (i = 0; i < tdep->sc_num_regs; i++)
+ if (tdep->sc_reg_offset[i] != -1)
+ cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
- return pc;
+ *this_cache = cache;
+ return cache;
}
-/* Sequence of bytes for breakpoint instruction. */
-static const unsigned char *
-x86_64_breakpoint_from_pc (CORE_ADDR *pc, int *lenptr)
+static void
+x86_64_sigtramp_frame_this_id (struct frame_info *next_frame,
+ void **this_cache, struct frame_id *this_id)
{
- static unsigned char breakpoint[] = { 0xcc };
- *lenptr = 1;
- return breakpoint;
+ struct x86_64_frame_cache *cache =
+ x86_64_sigtramp_frame_cache (next_frame, this_cache);
+
+ (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
}
static void
-x86_64_save_dummy_frame_tos (CORE_ADDR sp)
+x86_64_sigtramp_frame_prev_register (struct frame_info *next_frame,
+ void **this_cache,
+ int regnum, int *optimizedp,
+ enum lval_type *lvalp, CORE_ADDR *addrp,
+ int *realnump, void *valuep)
+{
+ /* Make sure we've initialized the cache. */
+ x86_64_sigtramp_frame_cache (next_frame, this_cache);
+
+ x86_64_frame_prev_register (next_frame, this_cache, regnum,
+ optimizedp, lvalp, addrp, realnump, valuep);
+}
+
+static const struct frame_unwind x86_64_sigtramp_frame_unwind =
+{
+ SIGTRAMP_FRAME,
+ x86_64_sigtramp_frame_this_id,
+ x86_64_sigtramp_frame_prev_register
+};
+
+static const struct frame_unwind *
+x86_64_sigtramp_frame_sniffer (struct frame_info *next_frame)
+{
+ CORE_ADDR pc = frame_pc_unwind (next_frame);
+ char *name;
+
+ find_pc_partial_function (pc, &name, NULL, NULL);
+ if (PC_IN_SIGTRAMP (pc, name))
+ {
+ gdb_assert (gdbarch_tdep (current_gdbarch)->sigcontext_addr);
+
+ return &x86_64_sigtramp_frame_unwind;
+ }
+
+ return NULL;
+}
+\f
+
+static CORE_ADDR
+x86_64_frame_base_address (struct frame_info *next_frame, void **this_cache)
{
- /* We must add the size of the return address that is already
- put on the stack. */
- generic_save_dummy_frame_tos (sp +
- TYPE_LENGTH (builtin_type_void_func_ptr));
+ struct x86_64_frame_cache *cache =
+ x86_64_frame_cache (next_frame, this_cache);
+
+ return cache->base;
}
+static const struct frame_base x86_64_frame_base =
+{
+ &x86_64_frame_unwind,
+ x86_64_frame_base_address,
+ x86_64_frame_base_address,
+ x86_64_frame_base_address
+};
+
static struct frame_id
-x86_64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *frame)
+x86_64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
- CORE_ADDR base;
- frame_unwind_unsigned_register (frame, SP_REGNUM, &base);
- return frame_id_build (base, frame_pc_unwind (frame));
+ char buf[8];
+ CORE_ADDR fp;
+
+ frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
+ fp = extract_unsigned_integer (buf, 8);
+
+ return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
+}
+
+/* 16 byte align the SP per frame requirements. */
+
+static CORE_ADDR
+x86_64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
+{
+ return sp & -(CORE_ADDR)16;
}
+\f
+
+/* Supply register REGNUM from the floating-point register set REGSET
+ to register cache REGCACHE. If REGNUM is -1, do this for all
+ registers in REGSET. */
+
+static void
+x86_64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *fpregs, size_t len)
+{
+ const struct gdbarch_tdep *tdep = regset->descr;
+
+ gdb_assert (len == tdep->sizeof_fpregset);
+ x86_64_supply_fxsave (regcache, regnum, fpregs);
+}
+
+/* Return the appropriate register set for the core section identified
+ by SECT_NAME and SECT_SIZE. */
+
+static const struct regset *
+x86_64_regset_from_core_section (struct gdbarch *gdbarch,
+ const char *sect_name, size_t sect_size)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
+ {
+ if (tdep->fpregset == NULL)
+ {
+ tdep->fpregset = XMALLOC (struct regset);
+ tdep->fpregset->descr = tdep;
+ tdep->fpregset->supply_regset = x86_64_supply_fpregset;
+ }
+
+ return tdep->fpregset;
+ }
+
+ return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
+}
+\f
void
x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- int i, sum;
- /* The x86-64 has 16 SSE registers. */
+ /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
+ floating-point registers. */
+ tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
+
+ /* AMD64 has an FPU and 16 SSE registers. */
+ tdep->st0_regnum = X86_64_ST0_REGNUM;
tdep->num_xmm_regs = 16;
/* This is what all the fuss is about. */
set_gdbarch_long_double_bit (gdbarch, 128);
set_gdbarch_num_regs (gdbarch, X86_64_NUM_REGS);
+ set_gdbarch_register_name (gdbarch, x86_64_register_name);
+ set_gdbarch_register_type (gdbarch, x86_64_register_type);
/* Register numbers of various important registers. */
- set_gdbarch_sp_regnum (gdbarch, 7); /* %rsp */
- set_gdbarch_fp_regnum (gdbarch, 6); /* %rbp */
- set_gdbarch_pc_regnum (gdbarch, 16); /* %rip */
- set_gdbarch_ps_regnum (gdbarch, 17); /* %eflags */
- set_gdbarch_fp0_regnum (gdbarch, X86_64_NUM_GREGS); /* %st(0) */
+ set_gdbarch_sp_regnum (gdbarch, X86_64_RSP_REGNUM); /* %rsp */
+ set_gdbarch_pc_regnum (gdbarch, X86_64_RIP_REGNUM); /* %rip */
+ set_gdbarch_ps_regnum (gdbarch, X86_64_EFLAGS_REGNUM); /* %eflags */
+ set_gdbarch_fp0_regnum (gdbarch, X86_64_ST0_REGNUM); /* %st(0) */
/* The "default" register numbering scheme for the x86-64 is
- referred to as the "DWARF register number mapping" in the psABI.
- The preferred debugging format for all known x86-64 targets is
- actually DWARF2, and GCC doesn't seem to support DWARF (that is
- DWARF-1), but we provide the same mapping just in case. This
- mapping is also used for stabs, which GCC does support. */
- set_gdbarch_stab_reg_to_regnum (gdbarch, x86_64_dwarf2_reg_to_regnum);
- set_gdbarch_dwarf_reg_to_regnum (gdbarch, x86_64_dwarf2_reg_to_regnum);
- set_gdbarch_dwarf2_reg_to_regnum (gdbarch, x86_64_dwarf2_reg_to_regnum);
-
- /* We don't override SDB_REG_RO_REGNUM, sice COFF doesn't seem to be
- in use on any of the supported x86-64 targets. */
-
- set_gdbarch_register_name (gdbarch, x86_64_register_name);
- set_gdbarch_register_size (gdbarch, 8);
-
- /* Total amount of space needed to store our copies of the machine's
- register (SIZEOF_GREGS + SIZEOF_FPU_REGS + SIZEOF_FPU_CTRL_REGS +
- SIZEOF_SSE_REGS) */
- for (i = 0, sum = 0; i < X86_64_NUM_REGS; i++)
- sum += x86_64_register_info_table[i].size;
- set_gdbarch_register_bytes (gdbarch, sum);
-
- set_gdbarch_register_raw_size (gdbarch, x86_64_register_raw_size);
- set_gdbarch_register_byte (gdbarch, x86_64_register_byte);
- set_gdbarch_register_virtual_type (gdbarch, x86_64_register_virtual_type);
-
- set_gdbarch_register_convertible (gdbarch, x86_64_register_convertible);
- set_gdbarch_register_convert_to_virtual (gdbarch,
- x86_64_register_convert_to_virtual);
- set_gdbarch_register_convert_to_raw (gdbarch,
- x86_64_register_convert_to_raw);
-
- /* Getting saved registers is handled by unwind information. */
- set_gdbarch_deprecated_get_saved_register (gdbarch, cfi_get_saved_register);
-
- /* FIXME: kettenis/20021026: Should we set parm_boundary to 64 here? */
- set_gdbarch_read_fp (gdbarch, cfi_read_fp);
-
- set_gdbarch_extract_return_value (gdbarch, x86_64_extract_return_value);
-
- set_gdbarch_deprecated_push_arguments (gdbarch, x86_64_push_arguments);
- set_gdbarch_deprecated_push_return_address (gdbarch, x86_64_push_return_address);
- set_gdbarch_deprecated_pop_frame (gdbarch, x86_64_pop_frame);
- set_gdbarch_deprecated_store_struct_return (gdbarch, x86_64_store_struct_return);
- set_gdbarch_store_return_value (gdbarch, x86_64_store_return_value);
+ referred to as the "DWARF Register Number Mapping" in the System
+ V psABI. The preferred debugging format for all known x86-64
+ targets is actually DWARF2, and GCC doesn't seem to support DWARF
+ (that is DWARF-1), but we provide the same mapping just in case.
+ This mapping is also used for stabs, which GCC does support. */
+ set_gdbarch_stab_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
+ set_gdbarch_dwarf_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
+
+ /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
+ be in use on any of the supported x86-64 targets. */
+
+ /* Call dummy code. */
+ set_gdbarch_push_dummy_call (gdbarch, x86_64_push_dummy_call);
+ set_gdbarch_frame_align (gdbarch, x86_64_frame_align);
+ set_gdbarch_frame_red_zone_size (gdbarch, 128);
+
+ set_gdbarch_convert_register_p (gdbarch, x86_64_convert_register_p);
+ set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
+ set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
+
+ set_gdbarch_return_value (gdbarch, amd64_return_value);
/* Override, since this is handled by x86_64_extract_return_value. */
set_gdbarch_extract_struct_value_address (gdbarch, NULL);
- set_gdbarch_use_struct_convention (gdbarch, x86_64_use_struct_convention);
- set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, x86_64_frame_init_saved_regs);
set_gdbarch_skip_prologue (gdbarch, x86_64_skip_prologue);
- set_gdbarch_deprecated_frame_chain (gdbarch, x86_64_linux_frame_chain);
- set_gdbarch_frameless_function_invocation (gdbarch,
- x86_64_frameless_function_invocation);
- /* FIXME: kettenis/20021026: These two are GNU/Linux-specific and
- should be moved elsewhere. */
- set_gdbarch_deprecated_frame_saved_pc (gdbarch, x86_64_linux_frame_saved_pc);
- set_gdbarch_deprecated_saved_pc_after_call (gdbarch, x86_64_linux_saved_pc_after_call);
- set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
- /* FIXME: kettenis/20021026: This one is GNU/Linux-specific too. */
- set_gdbarch_pc_in_sigtramp (gdbarch, x86_64_linux_in_sigtramp);
-
+ /* Avoid wiring in the MMX registers for now. */
set_gdbarch_num_pseudo_regs (gdbarch, 0);
+ tdep->mm0_regnum = -1;
- /* Build call frame information (CFI) from DWARF2 frame debug info. */
- set_gdbarch_dwarf2_build_frame_info (gdbarch, dwarf2_build_frame_info);
-
- /* Initialization of per-frame CFI. */
- set_gdbarch_deprecated_init_extra_frame_info (gdbarch, cfi_init_extra_frame_info);
-
- /* Frame PC initialization is handled by using CFI. */
- set_gdbarch_deprecated_init_frame_pc (gdbarch, x86_64_init_frame_pc);
-
- /* Cons up virtual frame pointer for trace. */
- set_gdbarch_virtual_frame_pointer (gdbarch, cfi_virtual_frame_pointer);
+ set_gdbarch_unwind_dummy_id (gdbarch, x86_64_unwind_dummy_id);
/* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
since all supported x86-64 targets are ELF, but that might change
in the future. */
set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section);
-
- /* Dummy frame helper functions. */
- set_gdbarch_save_dummy_frame_tos (gdbarch, x86_64_save_dummy_frame_tos);
- set_gdbarch_unwind_dummy_id (gdbarch, x86_64_unwind_dummy_id);
+
+ frame_unwind_append_sniffer (gdbarch, x86_64_sigtramp_frame_sniffer);
+ frame_unwind_append_sniffer (gdbarch, x86_64_frame_sniffer);
+ frame_base_set_default (gdbarch, &x86_64_frame_base);
+
+ /* If we have a register mapping, enable the generic core file support. */
+ if (tdep->gregset_reg_offset)
+ set_gdbarch_regset_from_core_section (gdbarch,
+ x86_64_regset_from_core_section);
}
+\f
+
+#define I387_ST0_REGNUM X86_64_ST0_REGNUM
+
+/* The 64-bit FXSAVE format differs from the 32-bit format in the
+ sense that the instruction pointer and data pointer are simply
+ 64-bit offsets into the code segment and the data segment instead
+ of a selector offset pair. The functions below store the upper 32
+ bits of these pointers (instead of just the 16-bits of the segment
+ selector). */
+
+/* Fill register REGNUM in REGCACHE with the appropriate
+ floating-point or SSE register value from *FXSAVE. If REGNUM is
+ -1, do this for all registers. This function masks off any of the
+ reserved bits in *FXSAVE. */
void
-_initialize_x86_64_tdep (void)
+x86_64_supply_fxsave (struct regcache *regcache, int regnum,
+ const void *fxsave)
{
- /* Initialize the table saying where each register starts in the
- register file. */
- {
- int i, offset;
+ i387_supply_fxsave (regcache, regnum, fxsave);
- offset = 0;
- for (i = 0; i < X86_64_NUM_REGS; i++)
- {
- x86_64_register_byte_table[i] = offset;
- offset += x86_64_register_info_table[i].size;
- }
- }
+ if (fxsave)
+ {
+ const char *regs = fxsave;
+
+ if (regnum == -1 || regnum == I387_FISEG_REGNUM)
+ regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12);
+ if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
+ regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20);
+ }
+}
+
+/* Fill register REGNUM (if it is a floating-point or SSE register) in
+ *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do
+ this for all registers. This function doesn't touch any of the
+ reserved bits in *FXSAVE. */
+
+void
+x86_64_fill_fxsave (char *fxsave, int regnum)
+{
+ i387_fill_fxsave (fxsave, regnum);
+
+ if (regnum == -1 || regnum == I387_FISEG_REGNUM)
+ regcache_collect (I387_FISEG_REGNUM, fxsave + 12);
+ if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
+ regcache_collect (I387_FOSEG_REGNUM, fxsave + 20);
}
projects / deliverable / binutils-gdb.git / blobdiff