CORE_ADDR start_addr;
xtensa_isa isa;
xtensa_insnbuf ins, slot;
- char ibuf[XTENSA_ISA_BSZ];
+ gdb_byte ibuf[XTENSA_ISA_BSZ];
CORE_ADDR ia, bt, ba;
xtensa_format ifmt;
int ilen, islots, is;
#define RETURN_RET goto done
xtensa_isa isa;
xtensa_insnbuf ins, slot;
- char ibuf[XTENSA_ISA_BSZ];
+ gdb_byte ibuf[XTENSA_ISA_BSZ];
CORE_ADDR ia, bt, ba;
xtensa_format ifmt;
int ilen, islots, is;
CORE_ADDR ia; /* Current insn address in prologue. */
CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
- char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
+ gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
xtensa_isa isa; /* libisa ISA handle. */
xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
xtensa_format ifmt; /* libisa instruction format. */
{
xtensa_isa isa;
xtensa_insnbuf ins, slot;
- char ibuf[XTENSA_ISA_BSZ];
+ gdb_byte ibuf[XTENSA_ISA_BSZ];
CORE_ADDR ia, bt, ba;
xtensa_format ifmt;
int ilen, islots, is;