+2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
+ instruction classes.
+
+2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
+ hwcaps2.
+
+2016-11-22 Alan Modra <amodra@gmail.com>
+
+ PR 20744
+ * opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
+
+2016-11-03 David Tolnay <dtolnay@gmail.com>
+ Mark Wielaard <mark@klomp.org>
+
+ * demangle.h (DMGL_RUST): New macro.
+ (DMGL_STYLE_MASK): Add DMGL_RUST.
+ (demangling_styles): Add dlang_rust.
+ (RUST_DEMANGLING_STYLE_STRING): New macro.
+ (RUST_DEMANGLING): New macro.
+ (rust_demangle): New prototype.
+ (rust_is_mangled): Likewise.
+ (rust_demangle_sym): Likewise.
+
+2016-11-07 Jason Merrill <jason@redhat.com>
+
+ * demangle.h (enum demangle_component_type): Add
+ DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
+ AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
+ (enum aarch64_op): Add OP_FCMLA_ELEM.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
+ (enum aarch64_insn_class): Add ldst_imm10.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
+ (AARCH64_ARCH_V8_3): Define.
+ (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
+
+2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
+ (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
+ (ARM_ARCH_V8M_MAIN_DSP): Likewise.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
+
+2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
+ fields.
+ (struct arc_long_opcode): Delete.
+ (struct arc_operand): Change types for insert and extract
+ handlers.
+
+2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h: Make macros 64-bit safe.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * opcode/arc.h (arc_opcode_len): Declare.
+ (ARC_SHORT): Delete.
+
+2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
+ Andrew Waterman <andrew@sifive.com>
+
+ Add support for RISC-V architecture.
+ * dis-asm.h: Add prototypes for print_insn_riscv and
+ print_riscv_disassembler_options.
+ * elf/riscv.h: New file.
+ * opcode/riscv-opc.h: New file.
+ * opcode/riscv.h: New file.
+
+2016-10-17 Nick Clifton <nickc@redhat.com>
+
+ * elf/common.h (DT_SYMTAB_SHNDX): Define.
+ (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
+ (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
+ (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
+ (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
+ (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
+ (ELFOSABI_OPENVOS): Define.
+ (GRP_MASKOS, GRP_MASKPROC): Define.
+
+2016-10-14 Pedro Alves <palves@redhat.com>
+
+ * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
+ OVERRIDE): Define as empty.
+ [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
+ __final.
+ [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
+ empty.
+
+2016-10-14 Pedro Alves <palves@redhat.com>
+
+ * ansidecl.h (GCC_FINAL): Delete.
+ (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
+
+2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
+
+2016-09-29 Alan Modra <amodra@gmail.com>
+
+ * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
+
+2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * opcode/arc.h (insn_class_t): Add two new classes.
+
+2016-09-26 Alan Modra <amodra@gmail.com>
+
+ * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
+ (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
+ (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
+ (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
+ (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
+ (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
+ aarch64_insn_classes.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
+ (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
+ (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
+ (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
+ (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
+ (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
+ (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
+ (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
+ (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
+ (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
+ (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
+ (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
+ (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
+ (AARCH64_OPND_SVE_UIMM8_53): Likewise.
+ (aarch64_sve_dupm_mov_immediate_p): Declare.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
+ (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
+ (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
+ (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
+ (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
+ (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
+ (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
+ (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
+ (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
+ (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
+ (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
+ (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
+ (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
+ (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
+ (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
+ (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
+ (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
+ (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
+ (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
+ (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
+ Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
+ aarch64_opnd.
+ (AARCH64_MOD_MUL): New aarch64_modifier_kind.
+ (aarch64_opnd_info): Make shifter.amount an int64_t and
+ rearrange the fields.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
+ (AARCH64_OPND_SVE_PRFOP): Likewise.
+ (aarch64_sve_pattern_array): Declare.
+ (aarch64_sve_prfop_array): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
+ (AARCH64_OPND_QLF_P_M): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
+ aarch64_operand_class.
+ (AARCH64_OPND_CLASS_PRED_REG): Likewise.
+ (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
+ (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
+ (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
+ (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
+ (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
+ (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
+ (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
+ (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (F_STRICT): New flag.
+
+2016-09-07 Richard Earnshaw <rearnsha@arm.com>
+
+ * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
+
+2016-08-26 Cupertino Miranda <cmiranda@synopsys.com>
+ * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
+ SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
+ * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
+ relocation.
+
+2016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
+ (ARM_SET_SYM_CMSE_SPCL): Likewise.
+
+2016-08-01 Andrew Jenner <andrew@codesourcery.com>
+
+ * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
+
+2016-07-29 Aldy Hernandez <aldyh@redhat.com>
+
+ * libiberty.h (MAX_ALLOCA_SIZE): New macro.
+
+2016-07-27 Graham Markall <graham.markall@embecosm.com>
+
+ * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
+ ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
+ ARC_NUM_ADDRTYPES.
+ * opcode/arc.h: Add BMU to insn_class_t enum.
+ * opcode/arc.h: Add PMU to insn_class_t enum.
+
+2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * dis-asm.h: Declare print_arc_disassembler_options.
+
+2016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
+ out_implib_bfd fields.
+
+2016-07-14 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
+
+2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
+
+ * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
+ (SHF_ARM_PURECODE): ... this.
+
+2016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
+ (AARCH64_CPU_HAS_ANY_FEATURES): New.
+ (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
+ (AARCH64_OPCODE_HAS_FEATURE): Remove.
+
+2016-06-30 Matthew Wahab <matthew.wahab@arm.com>
+
+ * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
+ of enabled FPU features.
+
+2016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * opcode/sparc.h (enum sparc_opcode_arch_val): Move
+ SPARC_OPCODE_ARCH_MAX into the enum.
+
+2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
+
+2016-06-28 Maciej W. Rozycki <macro@imgtec.com>
+
+ * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
+
+2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * elf/xtensa.h (xtensa_make_property_section): New prototype.
+
+2016-06-24 John Baldwin <jhb@FreeBSD.org>
+
+ * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
+ (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
+ (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
+ (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
+
+2016-06-23 Graham Markall <graham.markall@embecosm.com>
+
+ * opcode/arc.h: Make insn_class_t alphabetical again.
+
+2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * elf/dlx.h: Wrap in extern C.
+ * elf/xtensa.h: Likewise.
+ * opcode/arc.h: Likewise.
+
+2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
+ tilegx_pipeline.
+
2016-06-21 Graham Markall <graham.markall@embecosm.com>
* opcode/arc.h: Add nps400 extension and instruction
projects / deliverable / binutils-gdb.git / blobdiff