AArch64: Mark sve instructions that require MOVPRFX constraints

[deliverable/binutils-gdb.git] / include / ChangeLog

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@@ -1,3 +1,28 @@
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+       * opcode/aarch64.h (struct aarch64_opcode): Add constraints,
+       extend flags field size.
+       (F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
+
+2018-10-03  John Darrington <john@darrington.wattle.id.au>
+
+       * dis-asm.h (print_insn_s12z): New declaration.
+
+2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
+
+       * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
+       (MASK_FENCE_TSO): Likewise.
+
+2018-10-01  Cupertino Miranda <cmiranda@synopsys.com>
+
+       * arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula.
+
+2018-09-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR binutils/23694
+       * include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't
+       include zero size sections at start of PT_NOTE segment.
+
 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 
        * elf/nds32.h: Remove the unused target features.