AArch64: Mark sve instructions that require MOVPRFX constraints
[deliverable/binutils-gdb.git] / include / ChangeLog
index aec4b63589c9e1be2ff19f8eae48fc2e30cf5138..8608a111eead6ffc88c28d19474c4ad1a524f835 100644 (file)
@@ -1,3 +1,103 @@
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+       * opcode/aarch64.h (struct aarch64_opcode): Add constraints,
+       extend flags field size.
+       (F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
+
+2018-10-03  John Darrington <john@darrington.wattle.id.au>
+
+       * dis-asm.h (print_insn_s12z): New declaration.
+
+2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
+
+       * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
+       (MASK_FENCE_TSO): Likewise.
+
+2018-10-01  Cupertino Miranda <cmiranda@synopsys.com>
+
+       * arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula.
+
+2018-09-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR binutils/23694
+       * include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't
+       include zero size sections at start of PT_NOTE segment.
+
+2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
+
+       * elf/nds32.h: Remove the unused target features.
+       * dis-asm.h (disassemble_init_nds32): Declared.
+       * elf/nds32.h (E_NDS32_NULL): Removed.
+       (E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
+       * opcode/nds32.h: Ident.
+       (N32_SUB6, INSN_LW): New macros.
+       (enum n32_opcodes): Updated.
+       * elf/nds32.h: Doc fixes.
+       * elf/nds32.h: Add R_NDS32_LSI.
+       * elf/nds32.h: Add new relocations for TLS.
+
+2018-09-20  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+       * elf/common.h (AT_SUN_HWCAP): Rename to ...
+       (AT_SUN_CAP_HW1): ... this.  Retain old name for backward
+       compatibility.
+       (AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1)
+       (AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2): Define.
+
+2018-09-05  Simon Marchi  <simon.marchi@ericsson.com>
+
+       * diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.
+
+2018-08-31  Alan Modra  <amodra@gmail.com>
+
+       * elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
+       (R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
+       (R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
+       (R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
+
+2018-08-30  Kito Cheng  <kito@andestech.com>
+
+       * opcode/riscv.h (MAX_SUBSET_NUM): New.
+       (riscv_opcode): Add xlen_requirement field and change type of
+       subset.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+       * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
+       * opcode/mips.h (CPU_XXX): New CPU_GS264E.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+       * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
+       * opcode/mips.h (CPU_XXX): New CPU_GS464E.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+       * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
+       E_MIPS_MACH_GS464.
+       (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
+       * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
+       (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
+       * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+       * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
+       (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
+       * opcode/mips.h (ASE_LOONGSON_EXT2): New macro.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+        * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
+        (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
+        * opcode/mips.h (ASE_LOONGSON_EXT): New macro.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+       * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
+       (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
+       * opcode/mips.h (ASE_LOONGSON_CAM): New macro.
+
 2018-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 
        * elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
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