+2018-10-26 John Baldwin <jhb@FreeBSD.org>
+
+ * elf/common.h (AT_FREEBSD_HWCAP2): Define.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
+ (AARCH64_FEATURE_ID_PFR2): New.
+ (AARCH64_ARCH_V8_5): Add both by default.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
+ (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
+ (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
+ define HINT #imm values.
+ (HINT_OPD_JC, HINT_OPD_NULL): Likewise.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
+ (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
+ (aarch64_sys_regs_sr): Declare new table.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_SB): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
+ (AARCH64_FEATURE_FRINTTS): New.
+ (AARCH64_ARCH_V8_5): Add both by default.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
+ (AARCH64_ARCH_V8_5): New.
+
+2018-10-08 Alan Modra <amodra@gmail.com>
+
+ * bfdlink.h (struct bfd_link_info): Add load_phdrs field.
+
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/arm.h (ARM_EXT2_PREDRES): New.
+ (ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.
+
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/arm.h (ARM_EXT2_SB): New.
+ (ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
+
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/arm.h (ARM_EXT2_V8_5A): New.
+ (ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.
+
+2018-10-05 Richard Henderson <rth@twiddle.net>
+
+ * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
+ R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
+ R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
+ R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
+ R_OR1K_SLO13, R_OR1K_PLTA26.
+
+2018-10-05 Richard Henderson <rth@twiddle.net>
+
+ * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
+ R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
+ R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (aarch64_inst): Remove.
+ (enum err_type): Add ERR_VFI.
+ (aarch64_is_destructive_by_operands): New.
+ (init_insn_sequence): New.
+ (aarch64_decode_insn): Remove param name.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
+ more arguments.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (enum err_type): New.
+ (aarch64_decode_insn): Use it.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (struct aarch64_instr_sequence): New.
+ (aarch64_opcode_encode): Use it.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (struct aarch64_opcode): Add constraints,
+ extend flags field size.
+ (F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
+
+2018-10-03 John Darrington <john@darrington.wattle.id.au>
+
+ * dis-asm.h (print_insn_s12z): New declaration.
+
+2018-10-02 Palmer Dabbelt <palmer@sifive.com>
+
+ * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
+ (MASK_FENCE_TSO): Likewise.
+
+2018-10-01 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula.
+
+2018-09-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/23694
+ * include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't
+ include zero size sections at start of PT_NOTE segment.
+
+2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
+
+ * elf/nds32.h: Remove the unused target features.
+ * dis-asm.h (disassemble_init_nds32): Declared.
+ * elf/nds32.h (E_NDS32_NULL): Removed.
+ (E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
+ * opcode/nds32.h: Ident.
+ (N32_SUB6, INSN_LW): New macros.
+ (enum n32_opcodes): Updated.
+ * elf/nds32.h: Doc fixes.
+ * elf/nds32.h: Add R_NDS32_LSI.
+ * elf/nds32.h: Add new relocations for TLS.
+
+2018-09-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ * elf/common.h (AT_SUN_HWCAP): Rename to ...
+ (AT_SUN_CAP_HW1): ... this. Retain old name for backward
+ compatibility.
+ (AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1)
+ (AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2): Define.
+
+2018-09-05 Simon Marchi <simon.marchi@ericsson.com>
+
+ * diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.
+
+2018-08-31 Alan Modra <amodra@gmail.com>
+
+ * elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
+ (R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
+ (R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
+ (R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
+
+2018-08-30 Kito Cheng <kito@andestech.com>
+
+ * opcode/riscv.h (MAX_SUBSET_NUM): New.
+ (riscv_opcode): Add xlen_requirement field and change type of
+ subset.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
+ * opcode/mips.h (CPU_XXX): New CPU_GS264E.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
+ * opcode/mips.h (CPU_XXX): New CPU_GS464E.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
+ E_MIPS_MACH_GS464.
+ (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
+ * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
+ (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
+ * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
+ * opcode/mips.h (ASE_LOONGSON_EXT2): New macro.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
+ * opcode/mips.h (ASE_LOONGSON_EXT): New macro.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
+ * opcode/mips.h (ASE_LOONGSON_CAM): New macro.
+
2018-08-24 H.J. Lu <hongjiu.lu@intel.com>
* elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
projects / deliverable / binutils-gdb.git / blobdiff