+2009-08-29 Martin Thuresson <martin@mtme.org>
+
+ * tic30.h (template): Rename type template to
+ insn_template. Updated code to use new name.
+ * tic54x.h (template): Rename type template to
+ insn_template.
+
+2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
+
+ * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
+
+2009-06-11 Anthony Green <green@moxielogic.com>
+
+ * moxie.h (MOXIE_F3_PCREL): Define.
+ (moxie_form3_opc_info): Grow.
+
+2009-06-06 Anthony Green <green@moxielogic.com>
+
+ * moxie.h (MOXIE_F1_M): Define.
+
+2009-04-15 Anthony Green <green@moxielogic.com>
+
+ * moxie.h: Created.
+
+2009-04-06 DJ Delorie <dj@redhat.com>
+
+ * h8300.h: Add relaxation attributes to MOVA opcodes.
+
+2009-03-10 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc.h (ppc_parse_cpu): Declare.
+
+2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
+
+ * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
+ and _IMM11 for mbitclr and mbitset.
+ * score-datadep.h: Update dependency information.
+
+2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (PPC_OPCODE_POWER7): New.
+
+2009-02-06 Doug Evans <dje@google.com>
+
+ * i386.h: Add comment regarding sse* insns and prefixes.
+
+2009-02-03 Sandip Matte <sandip@rmicorp.com>
+
+ * mips.h (INSN_XLR): Define.
+ (INSN_CHIP_MASK): Update.
+ (CPU_XLR): Define.
+ (OPCODE_IS_MEMBER): Update.
+ (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
+
+2009-01-28 Doug Evans <dje@google.com>
+
+ * opcode/i386.h: Add multiple inclusion protection.
+ (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
+ (EDI_REG_NUM): New macros.
+ (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
+ (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
+ (REX_PREFIX_P): New macro.
+
+2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (struct powerpc_opcode): New field "deprecated".
+ (PPC_OPCODE_NOPOWER4): Delete.
+
+2008-11-28 Joshua Kinard <kumba@gentoo.org>
+
+ * mips.h: Define CPU_R14000, CPU_R16000.
+ (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
+
+2008-11-18 Catherine Moore <clm@codesourcery.com>
+
+ * arm.h (FPU_NEON_FP16): New.
+ (FPU_ARCH_NEON_FP16): New.
+
+2008-11-06 Chao-ying Fu <fu@mips.com>
+
+ * mips.h: Doucument '1' for 5-bit sync type.
+
+2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
+ IA64_RS_CR.
+
+2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
+
+2008-07-30 Michael J. Eager <eager@eagercon.com>
+
+ * ppc.h (PPC_OPCODE_405): Define.
+ (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
+
+2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (ppc_cpu_t): New typedef.
+ (struct powerpc_opcode <flags>): Use it.
+ (struct powerpc_operand <insert, extract>): Likewise.
+ (struct powerpc_macro <flags>): Likewise.
+
+2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
+ Update comment before MIPS16 field descriptors to mention MIPS16.
+ (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
+ BBIT.
+ (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
+ New bit masks and shift counts for cins and exts.
+
+ * mips.h: Document new field descriptors +Q.
+ (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
+
+2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
+ (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
+
+2008-04-14 Edmar Wienskoski <edmar@freescale.com>
+
+ * ppc.h: (PPC_OPCODE_E500MC): New.
+
+2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (MAX_OPERANDS): Set to 5.
+ (MAX_MNEM_SIZE): Changed to 20.
+
+2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
+
+2008-03-09 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
+
+2008-03-04 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
+ (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
+ (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
+
+2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
+ Nick Clifton <nickc@redhat.com>
+
+ PR 3134
+ * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
+ with a 32-bit displacement but without the top bit of the 4th byte
+ set.
+
+2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * cr16.h (cr16_num_optab): Declared.
+
+2008-02-14 Hakan Ardo <hakan@debian.org>
+
+ PR gas/2626
+ * avr.h (AVR_ISA_2xxe): Define.
+
+2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips.h: Update copyright.
+ (INSN_CHIP_MASK): New macro.
+ (INSN_OCTEON): New macro.
+ (CPU_OCTEON): New macro.
+ (OPCODE_IS_MEMBER): Handle Octeon instructions.
+
+2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
+
+2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * avr.h (AVR_ISA_USB162): Add new opcode set.
+ (AVR_ISA_AVR3): Likewise.
+
+2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
+
+ * mips.h (INSN_LOONGSON_2E): New.
+ (INSN_LOONGSON_2F): New.
+ (CPU_LOONGSON_2E): New.
+ (CPU_LOONGSON_2F): New.
+ (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
+
+2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
+
+ * mips.h (INSN_ISA*): Redefine certain values as an
+ enumeration. Update comments.
+ (mips_isa_table): New.
+ (ISA_MIPS*): Redefine to match enumeration.
+ (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
+ values.
+
+2007-08-08 Ben Elliston <bje@au.ibm.com>
+
+ * ppc.h (PPC_OPCODE_PPCPS): New.
+
+2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
+
+ * m68k.h: Document j K & E.
+
+2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * cr16.h: New file for CR16 target.
+
+2007-05-02 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc.h (PPC_OPERAND_PLUS1): Update comment.
+
+2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
+
+ * m68k.h (mcfisa_c): New.
+ (mcfusp, mcf_mask): Adjust.
+
+2007-04-20 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
+ (num_powerpc_operands): Declare.
+ (PPC_OPERAND_SIGNED et al): Redefine as hex.
+ (PPC_OPERAND_PLUS1): Define.
+
+2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (REX_MODE64): Renamed to ...
+ (REX_W): This.
+ (REX_EXTX): Renamed to ...
+ (REX_R): This.
+ (REX_EXTY): Renamed to ...
+ (REX_X): This.
+ (REX_EXTZ): Renamed to ...
+ (REX_B): This.
+
+2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h: Add entries from config/tc-i386.h and move tables
+ to opcodes/i386-opc.h.
+
+2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (FloatDR): Removed.
+ (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
+
+2007-03-01 Alan Modra <amodra@bigpond.net.au>
+
+ * spu-insns.h: Add soma double-float insns.
+
+2007-02-20 Thiemo Seufer <ths@mips.com>
+ Chao-Ying Fu <fu@mips.com>
+
+ * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
+ (INSN_DSPR2): Add flag for DSP R2 instructions.
+ (M_BALIGN): New macro.
+
+2007-02-14 Alan Modra <amodra@bigpond.net.au>
+
+ * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
+ and Seg3ShortFrom with Shortform.
+
+2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/4027
+ * i386.h (i386_optab): Put the real "test" before the pseudo
+ one.
+
+2007-01-08 Kazu Hirata <kazu@codesourcery.com>
+
+ * m68k.h (m68010up): OR fido_a.
+
+2006-12-25 Kazu Hirata <kazu@codesourcery.com>
+
+ * m68k.h (fido_a): New.
+
+2006-12-24 Kazu Hirata <kazu@codesourcery.com>
+
+ * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
+ mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
+ values.
+
+2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
+
+2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * score-inst.h (enum score_insn_type): Add Insn_internal.
+
+2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
+ Yukishige Shibata <shibata@rd.scei.sony.co.jp>
+ Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
+ Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
+ Alan Modra <amodra@bigpond.net.au>
+
+ * spu-insns.h: New file.
+ * spu.h: New file.
+
+2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
+
+ * ppc.h (PPC_OPCODE_CELL): Define.
+
+2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+
+ * i386.h : Modify opcode to support for the change in POPCNT opcode
+ in amdfam10 architecture.
+
+2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h: Replace CpuMNI with CpuSSSE3.
+
+2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
+ Joseph Myers <joseph@codesourcery.com>
+ Ian Lance Taylor <ian@wasabisystems.com>
+ Ben Elliston <bje@wasabisystems.com>
+
+ * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
+
+2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * score-datadep.h: New file.
+ * score-inst.h: New file.
+
+2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
+ movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
+ movdq2q and movq2dq.
+
+2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+ Michael Meissner <michael.meissner@amd.com>
+
+ * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
+
+2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Add "nop" with memory reference.
+
+2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Update comment for 64bit NOP.
+
2006-06-06 Ben Elliston <bje@au.ibm.com>
Anton Blanchard <anton@samba.org>
before corresponding pa11 opcodes. Add strict pa10 register-immediate
entries for "fdc".
+2005-09-30 Catherine Moore <clm@cm00re.com>
+
+ * bfin.h: New file.
+
2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
projects / deliverable / binutils-gdb.git / blobdiff