AArch64: Mark sve instructions that require MOVPRFX constraints

[deliverable/binutils-gdb.git] / include / opcode / aarch64.h

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index dc16fe4a02a6de5721f84ee1f556bd488ac8517b..c7d9008c857ba5e6d79a3d6acddb52729c77e213 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -178,6 +178,8 @@ enum aarch64_opnd
   AARCH64_OPND_Ed,     /* AdvSIMD Vector Element Vd.  */
   AARCH64_OPND_En,     /* AdvSIMD Vector Element Vn.  */
   AARCH64_OPND_Em,     /* AdvSIMD Vector Element Vm.  */
+  AARCH64_OPND_Em16,   /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
+                          qualifier is S_H.  */
   AARCH64_OPND_LVn,    /* AdvSIMD Vector register list used in e.g. TBL.  */
   AARCH64_OPND_LVt,    /* AdvSIMD Vector register list used in ld/st.  */
   AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
@@ -698,7 +700,10 @@ struct aarch64_opcode
   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 
   /* Flags providing information about this instruction */
-  uint32_t flags;
+  uint64_t flags;
+
+  /* Extra constraints on the instruction that the verifier checks.  */
+  uint32_t constraints;
 
   /* If nonzero, this operand and operand 0 are both registers and
      are required to have the same register number.  */
@@ -769,7 +774,18 @@ extern aarch64_opcode aarch64_opcode_table[];
 #define F_SYS_READ (1ULL << 29)
 /* This system instruction is used to write system registers.  */
 #define F_SYS_WRITE (1ULL << 30)
-/* Next bit is 31.  */
+/* This instruction has an extra constraint on it that imposes a requirement on
+   subsequent instructions.  */
+#define F_SCAN (1ULL << 31)
+/* Next bit is 32.  */
+
+/* Instruction constraints.  */
+/* This instruction has a predication constraint on the instruction at PC+4.  */
+#define C_SCAN_MOVPRFX (1U << 0)
+/* This instruction's operation width is determined by the operand with the
+   largest element size.  */
+#define C_MAX_ELEM (1U << 1)
+/* Next bit is 2.  */
 
 static inline bfd_boolean
 alias_opcode_p (const aarch64_opcode *opcode)