/* mips.h. Mips opcode list for GDB, the GNU debugger.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005, 2008, 2009, 2010, 2013
- Free Software Foundation, Inc.
+ Copyright (C) 1993-2018 Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
#include "bfd.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/* These are bit masks and shift counts to use to access the various
fields of an instruction. To retrieve the X field of an
instruction, use the expression
/* Described by mips_reg_operand. */
OP_REG,
+ /* Like OP_REG, but can be omitted if the register is the same as the
+ previous operand. */
+ OP_OPTIONAL_REG,
+
/* Described by mips_reg_pair_operand. */
OP_REG_PAIR,
OP_REPEAT_PREV_REG,
/* $pc, which has no encoding in the architectural instruction. */
- OP_PC
+ OP_PC,
+
+ /* $28, which has no encoding in the MIPS16e architectural instruction. */
+ OP_REG28,
+
+ /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
+ which. */
+ OP_VU0_SUFFIX,
+
+ /* Like OP_VU0_SUFFIX, but used when the operand's value has already
+ been set. Any suffix used here must match the previous value. */
+ OP_VU0_MATCH_SUFFIX,
+
+ /* An index selected by an integer, e.g. [1]. */
+ OP_IMM_INDEX,
+
+ /* An index selected by a register, e.g. [$2]. */
+ OP_REG_INDEX,
+
+ /* The operand spans two 5-bit register fields, both of which must be set to
+ the source register. */
+ OP_SAME_RS_RT,
+
+ /* Described by mips_prev_operand. */
+ OP_CHECK_PREV,
+
+ /* A register operand that must not be zero. */
+ OP_NON_ZERO_REG
};
/* Enumerates the types of MIPS register. */
/* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
also be used in some contexts. */
- OP_REG_HW
+ OP_REG_HW,
+
+ /* Floating-point registers $vf0-$vf31. */
+ OP_REG_VF,
+
+ /* Integer registers $vi0-$vi31. */
+ OP_REG_VI,
+
+ /* R5900 VU0 registers $I, $Q, $R and $ACC. */
+ OP_REG_R5900_I,
+ OP_REG_R5900_Q,
+ OP_REG_R5900_R,
+ OP_REG_R5900_ACC,
+
+ /* MSA registers $w0-$w31. */
+ OP_REG_MSA,
+
+ /* MSA control registers $0-$31. */
+ OP_REG_MSA_CTRL
};
/* Base class for all operands. */
const unsigned char *reg_map;
};
+/* Describes an operand that which must match a condition based on the
+ previous operand. */
+struct mips_check_prev_operand
+{
+ struct mips_operand root;
+
+ bfd_boolean greater_than_ok;
+ bfd_boolean less_than_ok;
+ bfd_boolean equal_ok;
+ bfd_boolean zero_ok;
+};
+
/* Describes an operand that encodes a pair of registers. */
struct mips_reg_pair_operand
{
but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
struct mips_pcrel_operand
{
- struct mips_operand root;
+ /* Encodes the offset. */
+ struct mips_int_operand root;
- /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC'. */
+ /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',
+ which is then added to the offset encoded by ROOT. */
unsigned int align_log2 : 8;
- /* The operand is shifted left SHIFT places and added to PC'.
- The operand is signed if IS_SIGNED. */
- unsigned int shift : 8;
- unsigned int is_signed : 1;
-
/* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
reinstated. This is true for jumps and branches and false for
PC-relative data instructions. */
unsigned int flip_isa_bit : 1;
};
+/* Return true if the assembly syntax allows OPERAND to be omitted. */
+
+static inline bfd_boolean
+mips_optional_operand_p (const struct mips_operand *operand)
+{
+ return (operand->type == OP_OPTIONAL_REG
+ || operand->type == OP_REPEAT_PREV_REG);
+}
+
/* Return a version of INSN in which the field specified by OPERAND
has value UVAL. */
return uval;
}
+/* Return the maximum value that can be encoded by OPERAND. */
+
+static inline int
+mips_int_operand_max (const struct mips_int_operand *operand)
+{
+ return (operand->max_val + operand->bias) << operand->shift;
+}
+
+/* Return the minimum value that can be encoded by OPERAND. */
+
+static inline int
+mips_int_operand_min (const struct mips_int_operand *operand)
+{
+ unsigned int mask;
+
+ mask = (1 << operand->root.size) - 1;
+ return mips_int_operand_max (operand) - (mask << operand->shift);
+}
+
/* Return the register that OPERAND encodes as UVAL. */
static inline int
bfd_vma addr;
addr = base_pc & -(1 << operand->align_log2);
- if (operand->is_signed)
- addr += mips_signed_operand (&operand->root, uval) * (1 << operand->shift);
- else
- addr += uval << operand->shift;
+ addr += mips_decode_int_operand (&operand->root, uval);
if (operand->include_isa_bit)
addr |= base_pc & 1;
if (operand->flip_isa_bit)
unsigned long exclusions;
};
+/* Return true if MO is an instruction that requires 32-bit encoding. */
+
+static inline bfd_boolean
+mips_opcode_32bit_p (const struct mips_opcode *mo)
+{
+ return mo->mask >> 16 != 0;
+}
+
/* These are the characters which may appear in the args field of an
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
Macro instructions:
"A" General 32 bit expression
"I" 32 bit immediate (value placed in imm_expr).
- "+I" 32 bit immediate (value placed in imm2_expr).
"F" 64 bit floating point constant in .rdata
"L" 64 bit floating point constant in .lit8
"f" 32 bit floating point constant
"Y" source register (OP_*_FS)
"Z" source register (OP_*_FT)
+ R5900 VU0 Macromode instructions:
+ "+5" 5 bit floating point register (FD)
+ "+6" 5 bit floating point register (FS)
+ "+7" 5 bit floating point register (FT)
+ "+8" 5 bit integer register (FD)
+ "+9" 5 bit integer register (FS)
+ "+0" 5 bit integer register (FT)
+ "+K" match an existing 4-bit channel mask starting at bit 21
+ "+L" 2-bit channel index starting at bit 21
+ "+M" 2-bit channel index starting at bit 23
+ "+N" match an existing 2-bit channel index starting at bit 0
+ "+f" 15 bit immediate for VCALLMS
+ "+g" 5 bit signed immediate for VIADDI
+ "+m" $ACC register (syntax only)
+ "+q" $Q register (syntax only)
+ "+r" $R register (syntax only)
+ "+y" $I register (syntax only)
+ "#+" "++" decorator in ($reg++) sequence
+ "#-" "--" decorator in (--$reg) sequence
+
DSP ASE usage:
"2" 2 bit unsigned immediate for byte align (OP_*_BP)
"3" 3 bit unsigned immediate (OP_*_SA3)
"+z" 5-bit rz register (OP_*_RZ)
"+Z" 5-bit fz register (OP_*_FZ)
+ interAptiv MR2:
+ "-m" register list for SAVE/RESTORE instruction
+
Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+ MSA Extension:
+ "+d" 5-bit MSA register (FD)
+ "+e" 5-bit MSA register (FS)
+ "+h" 5-bit MSA register (FT)
+ "+k" 5-bit GPR at bit 6
+ "+l" 5-bit MSA control register at bit 6
+ "+n" 5-bit MSA control register at bit 11
+ "+o" 4-bit vector element index at bit 16
+ "+u" 3-bit vector element index at bit 16
+ "+v" 2-bit vector element index at bit 16
+ "+w" 1-bit vector element index at bit 16
+ "+T" (-512 .. 511) << 0 at bit 16
+ "+U" (-512 .. 511) << 1 at bit 16
+ "+V" (-512 .. 511) << 2 at bit 16
+ "+W" (-512 .. 511) << 3 at bit 16
+ "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+ "+!" 3 bit unsigned bit position at bit 16
+ "+@" 4 bit unsigned bit position at bit 16
+ "+#" 6 bit unsigned bit position at bit 16
+ "+$" 5 bit unsigned immediate at bit 16
+ "+%" 5 bit signed immediate at bit 16
+ "+^" 10 bit signed immediate at bit 11
+ "+&" 0 vector element index
+ "+*" 5-bit register vector element index at bit 16
+ "+|" 8-bit mask at bit 16
+
+ MIPS R6:
+ "+:" 11-bit mask at bit 0
+ "+'" 26 bit PC relative branch target address
+ "+"" 21 bit PC relative branch target address
+ "+;" 5 bit same register in both OP_*_RS and OP_*_RT
+ "+I" 2bit unsigned bit position at bit 6
+ "+O" 3bit unsigned bit position at bit 6
+ "+R" must be program counter
+ "-a" (-262144 .. 262143) << 2 at bit 0
+ "-b" (-131072 .. 131071) << 3 at bit 0
+ "-d" Same as destination register GP
+ "-s" 5 bit source register specifier (OP_*_RS) not $0
+ "-t" 5 bit source register specifier (OP_*_RT) not $0
+ "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS
+ "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS
+ "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS
+ "-x" 5 bit source register specifier (OP_*_RT) greater than or
+ equal to OP_*_RS
+ "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS
+ "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
+ "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
+
+ GINV ASE usage:
+ "+\" 2 bit Global TLB invalidate type at bit 8
+
Other:
"()" parens surrounding optional value
"," separates operands
Characters used so far, for quick reference when adding more:
"1234567890"
- "%[]<>(),+:'@!$*&\~"
+ "%[]<>(),+-:'@!#$*&\~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefghijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
- "1234"
- "ABCEFGHIJPQSXZ"
- "abcijpstxz"
+ "1234567890"
+ "~!@#$%^&*|:'";\"
+ "ABCEFGHIJKLMNOPQRSTUVWXZ"
+ "abcdefghijklmnopqrstuvwxyz"
+
+ Extension character sequences used so far ("-" followed by the
+ following), for quick reference when adding more:
+ "AB"
+ "abdmstuvwxy"
*/
/* These are the bits which may be set in the pinfo field of an
#define INSN_TLB 0x00000200
/* Reads coprocessor register other than floating point register. */
#define INSN_COP 0x00000400
-/* Instruction loads value from memory, requiring delay. */
-#define INSN_LOAD_MEMORY_DELAY 0x00000800
-/* Instruction loads value from coprocessor, requiring delay. */
-#define INSN_LOAD_COPROC_DELAY 0x00001000
+/* Instruction loads value from memory. */
+#define INSN_LOAD_MEMORY 0x00000800
+/* Instruction loads value from coprocessor, (may require delay). */
+#define INSN_LOAD_COPROC 0x00001000
/* Instruction has unconditional branch delay slot. */
#define INSN_UNCOND_BRANCH_DELAY 0x00002000
/* Instruction has conditional branch delay slot. */
#define INSN_COND_BRANCH_DELAY 0x00004000
/* Conditional branch likely: if branch not taken, insn nullified. */
#define INSN_COND_BRANCH_LIKELY 0x00008000
-/* Moves to coprocessor register, requiring delay. */
-#define INSN_COPROC_MOVE_DELAY 0x00010000
+/* Moves to coprocessor register, (may require delay). */
+#define INSN_COPROC_MOVE 0x00010000
/* Loads coprocessor register from memory, requiring delay. */
#define INSN_COPROC_MEMORY_DELAY 0x00020000
/* Reads the HI register. */
#define INSN2_COND_BRANCH 0x00001000
/* Reads from $16. This is true of the MIPS16 0x6500 nop. */
#define INSN2_READ_GPR_16 0x00002000
+/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */
+#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
+/* Instruction has a forbidden slot. */
+#define INSN2_FORBIDDEN_SLOT 0x00008000
+/* Opcode table entry is for a short MIPS16 form only. An extended
+ encoding may still exist, but with a separate opcode table entry
+ required. In disassembly the presence of this flag in an otherwise
+ successful match against an extended instruction encoding inhibits
+ matching against any subsequent short table entry even if it does
+ not have this flag set. A table entry matching the full extended
+ encoding is needed or otherwise the final EXTEND entry will apply,
+ for the disassembly of the prefix only. */
+#define INSN2_SHORT_ONLY 0x00010000
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
word constructed using these macros is a bitmask of the remaining
INSN_* values below. */
-#define INSN_ISA_MASK 0x0000000ful
+#define INSN_ISA_MASK 0x0000001ful
/* We cannot start at zero due to ISA_UNKNOWN below. */
#define INSN_ISA1 1
#define INSN_ISA5 5
#define INSN_ISA32 6
#define INSN_ISA32R2 7
-#define INSN_ISA64 8
-#define INSN_ISA64R2 9
+#define INSN_ISA32R3 8
+#define INSN_ISA32R5 9
+#define INSN_ISA32R6 10
+#define INSN_ISA64 11
+#define INSN_ISA64R2 12
+#define INSN_ISA64R3 13
+#define INSN_ISA64R5 14
+#define INSN_ISA64R6 15
/* Below this point the INSN_* values correspond to combinations of ISAs.
They are only for use in the opcodes table to indicate membership of
a combination of ISAs that cannot be expressed using the usual inclusion
ordering on the above INSN_* values. */
-#define INSN_ISA3_32 10
-#define INSN_ISA3_32R2 11
-#define INSN_ISA4_32 12
-#define INSN_ISA4_32R2 13
-#define INSN_ISA5_32R2 14
-
-/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
- INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
- this table describes whether at least one of the ISAs described by X
- is/are implemented by ISA Y. (Think of Y as the ISA level supported by
- a particular core and X as the ISA level(s) at which a certain instruction
- is defined.) The ISA(s) described by X is/are implemented by Y iff
- (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
- is non-zero. */
-static const unsigned int mips_isa_table[] =
- { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+#define INSN_ISA3_32 16
+#define INSN_ISA3_32R2 17
+#define INSN_ISA4_32 18
+#define INSN_ISA4_32R2 19
+#define INSN_ISA5_32R2 20
+
+/* The R6 definitions shown below state that they support all previous ISAs.
+ This is not actually true as some instructions are removed in R6.
+ The problem is that the removed instructions in R6 come from different
+ ISAs. One approach to solve this would be to describe in the membership
+ field of the opcode table the different ISAs an instruction belongs to.
+ This would require us to create a large amount of different ISA
+ combinations which is hard to manage. A cleaner approach (which is
+ implemented here) is to say that R6 is an extension of R5 and then to
+ deal with the removed instructions by adding instruction exclusions
+ for R6 in the opcode table. */
+
+/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */
+
+#define ISAF(X) (1 << (INSN_ISA##X - 1))
+#define INSN_UPTO1 ISAF(1)
+#define INSN_UPTO2 INSN_UPTO1 | ISAF(2)
+#define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2)
+#define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2)
+#define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2)
+#define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32)
+#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \
+ | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)
+#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3)
+#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5)
+#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6)
+#define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32)
+#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)
+#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3)
+#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5)
+#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6)
+
+/* The same information in table form: bit INSN_ISA<X> - 1 of index
+ INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */
+static const unsigned int mips_isa_table[] = {
+ INSN_UPTO1,
+ INSN_UPTO2,
+ INSN_UPTO3,
+ INSN_UPTO4,
+ INSN_UPTO5,
+ INSN_UPTO32,
+ INSN_UPTO32R2,
+ INSN_UPTO32R3,
+ INSN_UPTO32R5,
+ INSN_UPTO32R6,
+ INSN_UPTO64,
+ INSN_UPTO64R2,
+ INSN_UPTO64R3,
+ INSN_UPTO64R5,
+ INSN_UPTO64R6
+};
+#undef ISAF
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0f20
+#define INSN_CHIP_MASK 0xc7ff4f60
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
#define INSN_OCTEONP 0x00000200
#define INSN_OCTEON2 0x00000100
+#define INSN_OCTEON3 0x00000040
/* MIPS R5900 instruction */
#define INSN_5900 0x00004000
#define INSN_LOONGSON_3A 0x00000400
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
+/* Imagination interAptiv MR2. */
+#define INSN_INTERAPTIV_MR2 0x04000000
/* DSP ASE */
#define ASE_DSP 0x00000001
/* Virtualization ASE */
#define ASE_VIRT 0x00000200
#define ASE_VIRT64 0x00000400
+/* MSA Extension */
+#define ASE_MSA 0x00000800
+#define ASE_MSA64 0x00001000
+/* eXtended Physical Address (XPA) Extension. */
+#define ASE_XPA 0x00002000
+/* DSP R3 Module. */
+#define ASE_DSPR3 0x00004000
+/* MIPS16e2 ASE. */
+#define ASE_MIPS16E2 0x00008000
+/* MIPS16e2 MT ASE instructions. */
+#define ASE_MIPS16E2_MT 0x00010000
+/* The Virtualization ASE has eXtended Physical Addressing (XPA)
+ instructions which are only valid when both ASEs are enabled. */
+#define ASE_XPA_VIRT 0x00020000
+/* Cyclic redundancy check (CRC) ASE. */
+#define ASE_CRC 0x00040000
+#define ASE_CRC64 0x00080000
+/* Global INValidate Extension. */
+#define ASE_GINV 0x00100000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
#define ISA_MIPS64 INSN_ISA64
#define ISA_MIPS32R2 INSN_ISA32R2
+#define ISA_MIPS32R3 INSN_ISA32R3
+#define ISA_MIPS32R5 INSN_ISA32R5
#define ISA_MIPS64R2 INSN_ISA64R2
+#define ISA_MIPS64R3 INSN_ISA64R3
+#define ISA_MIPS64R5 INSN_ISA64R5
+#define ISA_MIPS32R6 INSN_ISA32R6
+#define ISA_MIPS64R6 INSN_ISA64R6
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
#define CPU_MIPS16 16
#define CPU_MIPS32 32
#define CPU_MIPS32R2 33
+#define CPU_MIPS32R3 34
+#define CPU_MIPS32R5 36
+#define CPU_MIPS32R6 37
#define CPU_MIPS5 5
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
+#define CPU_MIPS64R3 66
+#define CPU_MIPS64R5 68
+#define CPU_MIPS64R6 69
#define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
#define CPU_OCTEON 6501
#define CPU_OCTEONP 6601
#define CPU_OCTEON2 6502
+#define CPU_OCTEON3 6503
#define CPU_XLR 887682 /* decimal 'XLR' */
+#define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */
/* Return true if the given CPU is included in INSN_* mask MASK. */
case CPU_OCTEON2:
return (mask & INSN_OCTEON2) != 0;
+ case CPU_OCTEON3:
+ return (mask & INSN_OCTEON3) != 0;
+
case CPU_XLR:
return (mask & INSN_XLR) != 0;
+ case CPU_INTERAPTIV_MR2:
+ return (mask & INSN_INTERAPTIV_MR2) != 0;
+
+ case CPU_MIPS32R6:
+ return (mask & INSN_ISA_MASK) == INSN_ISA32R6;
+
+ case CPU_MIPS64R6:
+ return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
+ || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
+
default:
return FALSE;
}
M_DDIV_3I,
M_DDIVU_3,
M_DDIVU_3I,
- M_DEXT,
- M_DINS,
M_DIV_3,
M_DIV_3I,
M_DIVU_3,
Many instructions are short hand for other instructions (i.e., The
jal <register> instruction is short for jalr <register>). */
+extern const struct mips_operand mips_vu0_channel_mask;
extern const struct mips_operand *decode_mips_operand (const char *);
extern const struct mips_opcode mips_builtin_opcodes[];
extern const int bfd_mips_num_builtin_opcodes;
"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
- "0" zero register ($0)
+ "." zero register ($0)
"S" stack pointer ($sp or $29)
"P" program counter
"R" return address register ($ra or $31)
"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
+ "0" 5-bit ASMACRO p0 immediate
+ "1" 3-bit ASMACRO p1 immediate
+ "2" 3-bit ASMACRO p2 immediate
+ "3" 5-bit ASMACRO p3 immediate
+ "4" 3-bit ASMACRO p4 immediate
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
"a" 26 bit jump address
"i" likewise, but flips bit 0
"e" 11 bit extension value
"l" register list for entry instruction
"L" register list for exit instruction
+ ">" 5-bit SYNC code
+ "9" 9-bit signed immediate
+ "G" global pointer ($gp or $28)
+ "N" 5-bit coprocessor register
+ "O" 3-bit sel field for MFC0/MTC0
+ "Q" 5-bit hardware register
+ "T" 5-bit CACHE opcode or PREF hint
+ "b" 5-bit INS/EXT position, which becomes LSB
+ Enforces: 0 <= pos < 32.
+ "c" 5-bit INS size, which becomes MSB
+ Requires that "b" occurs first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ "d" 5-bit EXT size, which becomes MSBD
+ Requires that "b" occurs first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ "n" 2-bit immediate (1 .. 4)
+ "o" 5-bit unsigned immediate * 16
+ "r" 3-bit register
+ "s" 3-bit ASMACRO select immediate
+ "u" 16-bit unsigned immediate
"I" an immediate value used for macros
The remaining codes may be extended. Except as otherwise noted,
the full extended operand is a 16 bit signed value.
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
- ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
- "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
+ "F" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
- "m" 7 bit register list for save instruction (18 bit extended)
- "M" 7 bit register list for restore instruction (18 bit extended)
+ "m" 7 bit register list for SAVE/RESTORE instruction (18 bit extended)
+
+ Characters used so far, for quick reference when adding more:
+ "0123456 89"
+ ".[]<>"
+ "ABCDEFGHI KL NOPQRSTUVWXYZ"
+ "abcde ijklmnopqrs uvwxyz"
*/
/* Save/restore encoding for the args field when all 4 registers are
either saved as arguments or saved/restored as statics. */
-#define MIPS16_ALL_ARGS 0xe
-#define MIPS16_ALL_STATICS 0xb
+#define MIPS_SVRS_ALL_ARGS 0xe
+#define MIPS_SVRS_ALL_STATICS 0xb
/* The following flags have the same value for the mips16 opcode
table:
"y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
"z" must be zero register
"C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
- "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
"K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
"+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
"+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
+ "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code
+ (MICROMIPSOP_*_CODE10)
PC-relative addition (ADDIUPC) instruction:
"mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
Macro instructions:
"A" general 32 bit expression
"I" 32-bit immediate (value placed in imm_expr).
- "+I" 32-bit immediate (value placed in imm2_expr).
"F" 64-bit floating point constant in .rdata
"L" 64-bit floating point constant in .lit8
"f" 32-bit floating point constant
microMIPS Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+ MSA Extension:
+ "+d" 5-bit MSA register (FD)
+ "+e" 5-bit MSA register (FS)
+ "+h" 5-bit MSA register (FT)
+ "+k" 5-bit GPR at bit 6
+ "+l" 5-bit MSA control register at bit 6
+ "+n" 5-bit MSA control register at bit 11
+ "+o" 4-bit vector element index at bit 16
+ "+u" 3-bit vector element index at bit 16
+ "+v" 2-bit vector element index at bit 16
+ "+w" 1-bit vector element index at bit 16
+ "+x" 5-bit shift amount at bit 16
+ "+T" (-512 .. 511) << 0 at bit 16
+ "+U" (-512 .. 511) << 1 at bit 16
+ "+V" (-512 .. 511) << 2 at bit 16
+ "+W" (-512 .. 511) << 3 at bit 16
+ "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+ "+!" 3 bit unsigned bit position at bit 16
+ "+@" 4 bit unsigned bit position at bit 16
+ "+#" 6 bit unsigned bit position at bit 16
+ "+$" 5 bit unsigned immediate at bit 16
+ "+%" 5 bit signed immediate at bit 16
+ "+^" 10 bit signed immediate at bit 11
+ "+&" 0 vector element index
+ "+*" 5-bit register vector element index at bit 16
+ "+|" 8-bit mask at bit 16
+
Other:
"()" parens surrounding optional value
"," separates operands
Characters used so far, for quick reference when adding more:
"12345678 0"
- "<>(),+.@\^|~"
+ "<>(),+-.@\^|~"
"ABCDEFGHI KLMN RST V "
"abcd f hijklmnopqrstuvw yz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
""
- ""
- "ABCEFGHI"
- "ij"
+ "~!@#$%^&*|"
+ "ABCEFGHJTUVW"
+ "dehijklnouvwx"
Extension character sequences used so far ("m" followed by the
following), for quick reference when adding more:
""
" BCDEFGHIJ LMNOPQ U WXYZ"
" bcdefghij lmn pq st xyz"
+
+ Extension character sequences used so far ("-" followed by the
+ following), for quick reference when adding more:
+ ""
+ ""
+ <none so far>
*/
extern const struct mips_operand *decode_micromips_operand (const char *);
Used to implement -mfix-loongson2f. */
#define LOONGSON2F_NOP_INSN 0x00200825
+#ifdef __cplusplus
+}
+#endif
+
#endif /* _MIPS_H_ */
projects / deliverable / binutils-gdb.git / blobdiff