gas/

[deliverable/binutils-gdb.git] / include / opcode / mips.h

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index f5f648bd34d54a84f099278f39cbf069d2d36797..476c8e3112cf189bd58a55ad938c4bb3a6cfb25c 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1,5 +1,5 @@
 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
@@ -142,6 +142,10 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define OP_SH_VECBYTE          22
 #define OP_MASK_VECALIGN       0x7     /* Vector byte-align (alni.ob) op.  */
 #define OP_SH_VECALIGN         21
+#define OP_MASK_INSMSB         0x1f    /* "ins" MSB.  */
+#define OP_SH_INSMSB           11
+#define OP_MASK_EXTMSBD                0x1f    /* "ext" MSBD.  */
+#define OP_SH_EXTMSBD          11
 
 #define        OP_OP_COP0              0x10
 #define        OP_OP_COP1              0x11
@@ -193,7 +197,7 @@ struct mips_opcode
   unsigned long membership;
 };
 
-/* These are the characters which may appears in the args field of an
+/* These are the characters which may appear in the args field of an
    instruction.  They appear in the order in which the fields appear
    when the instruction is used.  Commas and parentheses in the args
    string are ignored when assembling, and written into the output
@@ -228,6 +232,15 @@ struct mips_opcode
    "J" 19 bit wait function code (OP_*_CODE19)
    "x" accept and ignore register name
    "z" must be zero register
+   "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
+   "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
+       Enforces: 0 <= pos < 32.
+   "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
+       Requires that "+A" occur first to set position.
+       Enforces: 0 < (pos+size) <= 32.
+   "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
+       Requires that "+A" occur first to set position.
+       Enforces: 0 < (pos+size) <= 32.
 
    Floating point instructions:
    "D" 5 bit destination register (OP_*_FD)
@@ -247,6 +260,8 @@ struct mips_opcode
    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
    see also "k" above
+   "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
+       for pretty-printing in disassembly only.
 
    Macro instructions:
    "A" General 32 bit expression
@@ -268,11 +283,16 @@ struct mips_opcode
    "()" parens surrounding optional value
    ","  separates operands
    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
+   "+"  Start of extension sequence.
 
    Characters used so far, for quick reference when adding more:
-   "%[]<>(),"
-   "ABCDEFGHIJLMNOPQRSTUVWXYZ"
+   "%[]<>(),+"
+   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefhijklopqrstuvwxz"
+
+   Extension character sequences used so far ("+" followed by the
+   following), for quick reference when adding more:
+   "ABCD"
 */
 
 /* These are the bits which may be set in the pinfo field of an
@@ -353,17 +373,18 @@ struct mips_opcode
 
 /* Masks used to mark instructions to indicate which MIPS ISA level
    they were introduced in.  ISAs, as defined below, are logical
-   ORs of these bits, indicatingthat they support the instructions
+   ORs of these bits, indicating that they support the instructions
    defined at the given level.  */
 
 #define INSN_ISA_MASK            0x00000fff
-#define INSN_ISA1                 0x00000010
-#define INSN_ISA2                 0x00000020
-#define INSN_ISA3                 0x00000040
-#define INSN_ISA4                 0x00000080
-#define INSN_ISA5                 0x00000100
-#define INSN_ISA32                0x00000200
-#define INSN_ISA64                0x00000400
+#define INSN_ISA1                 0x00000001
+#define INSN_ISA2                 0x00000002
+#define INSN_ISA3                 0x00000004
+#define INSN_ISA4                 0x00000008
+#define INSN_ISA5                 0x00000010
+#define INSN_ISA32                0x00000020
+#define INSN_ISA64                0x00000040
+#define INSN_ISA32R2              0x00000080
 
 /* Masks used for MIPS-defined ASEs.  */
 #define INSN_ASE_MASK            0x0000f000
@@ -406,9 +427,12 @@ struct mips_opcode
 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
+
 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 
+#define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
+
 /* CPU defines, use instead of hardcoding processor number. Keep this
    in sync with bfd/archures.c in order for machine selection to work.  */
 #define CPU_UNKNOWN    0               /* Gas internal use.  */
@@ -432,6 +456,7 @@ struct mips_opcode
 #define CPU_R12000     12000
 #define CPU_MIPS16     16
 #define CPU_MIPS32     32
+#define CPU_MIPS32R2   33
 #define CPU_MIPS5       5
 #define CPU_MIPS64      64
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */