bfd:

[deliverable/binutils-gdb.git] / include / opcode / mips.h

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index e7cfdb97908c4b593df1e1a36668904875c504f3..a4017a1eee7e15aefe6d0072540707883e8d1f4a 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -543,7 +543,7 @@ static const unsigned int mips_isa_table[] =
   { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 
 /* Masks used for Chip specific instructions.  */
-#define INSN_CHIP_MASK           0xc3ff0800
+#define INSN_CHIP_MASK           0xc3ff0820
 
 /* Cavium Networks Octeon instructions.  */
 #define INSN_OCTEON              0x00000800
@@ -592,6 +592,8 @@ static const unsigned int mips_isa_table[] =
 #define INSN_LOONGSON_2E          0x40000000
 /* ST Microelectronics Loongson 2F.  */
 #define INSN_LOONGSON_2F          0x80000000
+/* RMI Xlr instruction */
+#define INSN_XLR                 0x00000020
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -644,6 +646,7 @@ static const unsigned int mips_isa_table[] =
 #define CPU_LOONGSON_2E 3001
 #define CPU_LOONGSON_2F 3002
 #define CPU_OCTEON     6501
+#define CPU_XLR        887682          /* decimal 'XLR'   */
 
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified
@@ -677,6 +680,7 @@ static const unsigned int mips_isa_table[] =
          && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
      || (cpu == CPU_OCTEON                                             \
         && ((insn)->membership & INSN_OCTEON) != 0)                    \
+     || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \
      || 0)     /* Please keep this term for easier source merging.  */
 
 /* This is a list of macro expanded instructions.
@@ -809,6 +813,11 @@ enum
   M_LWR_A,
   M_LWR_AB,
   M_LWU_AB,
+  M_MSGSND,
+  M_MSGLD,
+  M_MSGLD_T,
+  M_MSGWAIT,
+  M_MSGWAIT_T,
   M_MOVE,
   M_MUL,
   M_MUL_I,