MIPS16e2: Add MIPS16e2 ASE support

[deliverable/binutils-gdb.git] / include / opcode / mips.h

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 0d043d9520d7b85eba55c4dd9cde798c517fc196..c71a33a1a3519f01521bb169df5ceaf20dafd7c0 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -409,6 +409,9 @@ enum mips_operand_type {
   /* $pc, which has no encoding in the architectural instruction.  */
   OP_PC,
 
+  /* $28, which has no encoding in the MIPS16e architectural instruction.  */
+  OP_REG28,
+
   /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
      which.  */
   OP_VU0_SUFFIX,
@@ -1116,7 +1119,12 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
 #define INSN2_FORBIDDEN_SLOT        0x00008000
 /* Opcode table entry is for a short MIPS16 form only.  An extended
    encoding may still exist, but with a separate opcode table entry
-   required.  */
+   required.  In disassembly the presence of this flag in an otherwise
+   successful match against an extended instruction encoding inhibits
+   matching against any subsequent short table entry even if it does
+   not have this flag set.  A table entry matching the full extended
+   encoding is needed or otherwise the final EXTEND entry will apply,
+   for the disassembly of the prefix only.  */
 #define INSN2_SHORT_ONLY           0x00010000
 
 /* Masks used to mark instructions to indicate which MIPS ISA level
@@ -1274,6 +1282,10 @@ static const unsigned int mips_isa_table[] = {
 #define ASE_XPA                        0x00002000
 /* DSP R3 Module.  */
 #define ASE_DSPR3              0x00004000
+/* MIPS16e2 ASE.  */
+#define ASE_MIPS16E2           0x00008000
+/* MIPS16e2 MT ASE instructions.  */
+#define ASE_MIPS16E2_MT                0x00010000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -1820,7 +1832,24 @@ extern int bfd_mips_num_opcodes;
    "e" 11 bit extension value
    "l" register list for entry instruction
    "L" register list for exit instruction
+   ">" 5-bit SYNC code
+   "9" 9-bit signed immediate
+   "G" global pointer ($gp or $28)
+   "N" 5-bit coprocessor register
+   "O" 3-bit sel field for MFC0/MTC0
+   "Q" 5-bit hardware register
+   "T" 5-bit CACHE opcode or PREF hint
+   "b" 5-bit INS/EXT position, which becomes LSB
+       Enforces: 0 <= pos < 32.
+   "c" 5-bit INS size, which becomes MSB
+       Requires that "b" occurs first to set position.
+       Enforces: 0 < (pos+size) <= 32.
+   "d" 5-bit EXT size, which becomes MSBD
+       Requires that "b" occurs first to set position.
+       Enforces: 0 < (pos+size) <= 32.
+   "r" 3-bit register
    "s" 3-bit ASMACRO select immediate
+   "u" 16-bit unsigned immediate
 
    "I" an immediate value used for macros
 
@@ -1850,10 +1879,10 @@ extern int bfd_mips_num_opcodes;
    "M" 7 bit register list for restore instruction (18 bit extended)
 
    Characters used so far, for quick reference when adding more:
-   "0123456 8 "
-   ".[]<"
-   "ABCDEF HI KLM  P RS UVWXYZ"
-   "a   e   ijklm  pq s  vwxyz"
+   "0123456 89"
+   ".[]<>"
+   "ABCDEFGHI KLMNOPQRSTUVWXYZ"
+   "abcde   ijklm  pqrs uvwxyz"
   */
 
 /* Save/restore encoding for the args field when all 4 registers are