/* Opcode table for the TI MSP430 microcontrollers
- Copyright 2002, 2004 Free Software Foundation, Inc.
+ Copyright (C) 2002-2019 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef __MSP430_H_
#define __MSP430_H_
int ol; /* Operand length words. */
int am; /* Addr mode. */
int reg; /* Register. */
- int mode; /* Pperand mode. */
+ int mode; /* Operand mode. */
+ int vshift; /* Number of bytes to shift operand down. */
#define OP_REG 0
#define OP_EXP 1
#ifndef DASM_SECTION
#endif
};
-#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */
+/* Byte operation flag for all instructions. Also used as the
+ A/L bit in the extension word to indicate a 20-bit operation. */
+#define BYTE_OPERATION (1 << 6)
+/* Z/C bit in the extension word. If set the carry bit is ignored
+ for the duration of the operation, although it may be changed as
+ a result of the operation. */
+#define IGNORE_CARRY_BIT (1 << 8)
struct msp430_opcode_s
{
- char *name;
+ const char *name;
int fmt;
int insn_opnumb;
int bin_opcode;
int bin_mask;
};
-#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask }
+#define MSP_INSN(name, fmt, numb, bin, mask) { #name, fmt, numb, bin, mask }
static struct msp430_opcode_s msp430_opcodes[] =
{
MSP_INSN (bleu, 5, 2, 0, 0xffff),
MSP_INSN (ble, 5, 3, 0, 0xffff),
+ /* MSP430X instructions - these ones use an extension word.
+ A negative format indicates an MSP430X instruction. */
+ MSP_INSN (addcx, -2, 2, 0x6000, 0xf000),
+ MSP_INSN (addx, -2, 2, 0x5000, 0xf000),
+ MSP_INSN (andx, -2, 2, 0xf000, 0xf000),
+ MSP_INSN (bicx, -2, 2, 0xc000, 0xf000),
+ MSP_INSN (bisx, -2, 2, 0xd000, 0xf000),
+ MSP_INSN (bitx, -2, 2, 0xb000, 0xf000),
+ MSP_INSN (cmpx, -2, 2, 0x9000, 0xf000),
+ MSP_INSN (daddx, -2, 2, 0xa000, 0xf000),
+ MSP_INSN (movx, -2, 2, 0x4000, 0xf000),
+ MSP_INSN (subcx, -2, 2, 0x7000, 0xf000),
+ MSP_INSN (subx, -2, 2, 0x8000, 0xf000),
+ MSP_INSN (xorx, -2, 2, 0xe000, 0xf000),
+
+ /* MSP430X Synthetic instructions. */
+ MSP_INSN (adcx, -1, 1, 0x6300, 0xff30),
+ MSP_INSN (clra, -1, 1, 0x4300, 0xff30),
+ MSP_INSN (clrx, -1, 1, 0x4300, 0xff30),
+ MSP_INSN (dadcx, -1, 1, 0xa300, 0xff30),
+ MSP_INSN (decx, -1, 1, 0x8310, 0xff30),
+ MSP_INSN (decda, -1, 1, 0x8320, 0xff30),
+ MSP_INSN (decdx, -1, 1, 0x8320, 0xff30),
+ MSP_INSN (incx, -1, 1, 0x5310, 0xff30),
+ MSP_INSN (incda, -1, 1, 0x5320, 0xff30),
+ MSP_INSN (incdx, -1, 1, 0x5320, 0xff30),
+ MSP_INSN (invx, -1, 1, 0xe330, 0xfff0),
+ MSP_INSN (popx, -1, 1, 0x4130, 0xff30),
+ MSP_INSN (rlax, -1, 2, 0x5000, 0xf000),
+ MSP_INSN (rlcx, -1, 2, 0x6000, 0xf000),
+ MSP_INSN (sbcx, -1, 1, 0x7300, 0xff30),
+ MSP_INSN (tsta, -1, 1, 0x9300, 0xff30),
+ MSP_INSN (tstx, -1, 1, 0x9300, 0xff30),
+
+ MSP_INSN (pushx, -3, 1, 0x1200, 0xff80),
+ MSP_INSN (rrax, -3, 1, 0x1100, 0xff80),
+ MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit clear. */
+ MSP_INSN (rrux, -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit set. */
+ MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0),
+ MSP_INSN (sxtx, -3, 1, 0x1180, 0xffc0),
+
+ /* MSP430X Address instructions - no extension word needed.
+ The insn_opnumb field is used to encode the nature of the
+ instruction for assembly and disassembly purposes. */
+ MSP_INSN (calla, -1, 4, 0x1300, 0xff00),
+
+ MSP_INSN (popm, -1, 5, 0x1600, 0xfe00),
+ MSP_INSN (pushm, -1, 5, 0x1400, 0xfe00),
+
+ MSP_INSN (rrcm, -1, 6, 0x0040, 0xf3e0),
+ MSP_INSN (rram, -1, 6, 0x0140, 0xf3e0),
+ MSP_INSN (rlam, -1, 6, 0x0240, 0xf3e0),
+ MSP_INSN (rrum, -1, 6, 0x0340, 0xf3e0),
+
+ MSP_INSN (adda, -1, 8, 0x00a0, 0xf0b0),
+ MSP_INSN (cmpa, -1, 8, 0x0090, 0xf0b0),
+ MSP_INSN (suba, -1, 8, 0x00b0, 0xf0b0),
+
+ MSP_INSN (reta, -1, 9, 0x0110, 0xffff),
+ MSP_INSN (bra, -1, 9, 0x0000, 0xf0cf),
+ MSP_INSN (mova, -1, 9, 0x0000, 0xf080),
+ MSP_INSN (mova, -1, 9, 0x0080, 0xf0b0),
+ MSP_INSN (mova, -1, 9, 0x00c0, 0xf0f0),
+
+ /* Pseudo instruction to set the repeat field in the extension word. */
+ MSP_INSN (rpt, -1, 10, 0x0000, 0x0000),
+
/* End of instruction set. */
{ NULL, 0, 0, 0, 0 }
};
-/* GCC uses the some condition codes which we'll
- implement as new polymorph instructions.
-
- COND EXPL SHORT JUMP LONG JUMP
- ===============================================
- eq == jeq jne +4; br lab
- ne != jne jeq +4; br lab
-
- ltn honours no-overflow flag
- ltn < jn jn +2; jmp +4; br lab
-
- lt < jl jge +4; br lab
- ltu < jlo lhs +4; br lab
- le <= see below
- leu <= see below
-
- gt > see below
- gtu > see below
- ge >= jge jl +4; br lab
- geu >= jhs jlo +4; br lab
- ===============================================
-
- Therefore, new opcodes are (BranchEQ -> beq; and so on...)
- beq,bne,blt,bltn,bltu,bge,bgeu
- 'u' means unsigned compares
-
- Also, we add 'jump' instruction:
- jump UNCOND -> jmp br lab
-
- They will have fmt == 4, and insn_opnumb == number of instruction. */
-
-struct rcodes_s
-{
- char * name;
- int index; /* Corresponding insn_opnumb. */
- int sop; /* Opcode if jump length is short. */
- long lpos; /* Label position. */
- long lop0; /* Opcode 1 _word_ (16 bits). */
- long lop1; /* Opcode second word. */
- long lop2; /* Opcode third word. */
-};
-
-#define MSP430_RLC(n,i,sop,o1) \
- {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
-
-static struct rcodes_s msp430_rcodes[] =
-{
- MSP430_RLC (beq, 0, 0x2400, 0x2000),
- MSP430_RLC (bne, 1, 0x2000, 0x2400),
- MSP430_RLC (blt, 2, 0x3800, 0x3400),
- MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
- MSP430_RLC (bge, 4, 0x3400, 0x3800),
- MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
- {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
- {"jump", 7, 0x3c00, 1, 0x4010, 0, 0},
- {0,0,0,0,0,0,0}
-};
-#undef MSP430_RLC
-
-
-/* More difficult than above and they have format 5.
-
- COND EXPL SHORT LONG
- =================================================================
- gt > jeq +2; jge label jeq +6; jl +4; br label
- gtu > jeq +2; jhs label jeq +6; jlo +4; br label
- leu <= jeq label; jlo label jeq +2; jhs +4; br label
- le <= jeq label; jl label jeq +2; jge +4; br label
- ================================================================= */
-
-struct hcodes_s
-{
- char * name;
- int index; /* Corresponding insn_opnumb. */
- int tlab; /* Number of labels in short mode. */
- int op0; /* Opcode for first word of short jump. */
- int op1; /* Opcode for second word of short jump. */
- int lop0; /* Opcodes for long jump mode. */
- int lop1;
- int lop2;
-};
-
-static struct hcodes_s msp430_hcodes[] =
-{
- {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
- {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
- {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
- {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
- {0,0,0,0,0,0,0,0}
-};
-
#endif
projects / deliverable / binutils-gdb.git / blobdiff