[binutils][aarch64] New iclass sve_size_hsd2.

[deliverable/binutils-gdb.git] / include / opcode / rx.h

diff --git a/include/opcode/rx.h b/include/opcode/rx.h
index a1e6c45c77e7c1e941c16d0a87ef5d6c819e7338..8b27fe5a661f3a3a385acb5da18503b7f4251f21 100644 (file)
--- a/include/opcode/rx.h
+++ b/include/opcode/rx.h
@@ -1,13 +1,12 @@
 /* Opcode decoder for the Renesas RX
-   Copyright 2008, 2009
-   Free Software Foundation, Inc.
+   Copyright (C) 2008-2019 Free Software Foundation, Inc.
    Written by DJ Delorie <dj@redhat.com>
 
    This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License, or
+   the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
@@ -24,6 +23,10 @@
    analyzer, and the disassembler.  Given an opcode data source,
    it decodes the next opcode into the following structures.  */
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 typedef enum
 {
   RX_AnySize = 0,
@@ -35,6 +38,9 @@ typedef enum
   RX_SWord,
   RX_3Byte,
   RX_Long,
+  RX_Double,
+  RX_Bad_Size,
+  RX_MAX_SIZE
 } RX_Size;
 
 typedef enum
@@ -43,10 +49,17 @@ typedef enum
   RX_Operand_Immediate,        /* #addend */
   RX_Operand_Register, /* Rn */
   RX_Operand_Indirect, /* [Rn + addend] */
+  RX_Operand_Zero_Indirect,/* [Rn] */
   RX_Operand_Postinc,  /* [Rn+] */
   RX_Operand_Predec,   /* [-Rn] */
   RX_Operand_Condition,        /* eq, gtu, etc */
   RX_Operand_Flag,     /* [UIOSZC] */
+  RX_Operand_TwoReg,   /* [Rn + scale*R2] */
+  RX_Operand_DoubleReg,        /* DRn */
+  RX_Operand_DoubleRegH,/* DRHn */
+  RX_Operand_DoubleRegL,/* DRLn */
+  RX_Operand_DoubleCReg,/* DCRxx */
+  RX_Operand_DoubleCond,/* UN/EQ/LE/LT */
 } RX_Operand_Type;
 
 typedef enum
@@ -57,7 +70,6 @@ typedef enum
   RXO_movbir,  /* [s,s2] = d (signed) */
   RXO_pushm,   /* s..s2 */
   RXO_popm,    /* s..s2 */
-  RXO_pusha,   /* &s */
   RXO_xchg,    /* s <-> d */
   RXO_stcc,    /* d = s if cond(s2) */
   RXO_rtsd,    /* rtsd, 1=imm, 2-0 = reg if reg type */
@@ -83,8 +95,6 @@ typedef enum
   RXO_min,     /* d = min(d,s) */
   RXO_emul,    /* d:64 = d:32 * s */
   RXO_emulu,   /* d:64 = d:32 * s (unsigned) */
-  RXO_ediv,    /* d:64 / s; d = quot, d+1 = rem */
-  RXO_edivu,   /* d:64 / s; d = quot, d+1 = rem */
 
   RXO_rolc,    /* d <<= 1 through carry */
   RXO_rorc,    /* d >>= 1 through carry*/
@@ -98,6 +108,12 @@ typedef enum
   RXO_jsrrel,  /* pc += d */
   RXO_rts,
   RXO_nop,
+  RXO_nop2,
+  RXO_nop3,
+  RXO_nop4,
+  RXO_nop5,
+  RXO_nop6,
+  RXO_nop7,
 
   RXO_scmpu,
   RXO_smovu,
@@ -151,6 +167,51 @@ typedef enum
   RXO_wait,
 
   RXO_sccnd,   /* d = cond(s) ? 1 : 0 */
+
+  RXO_fsqrt,
+  RXO_ftou,
+  RXO_utof,
+  RXO_movco,
+  RXO_movli,
+  RXO_emaca,
+  RXO_emsba,
+  RXO_emula,
+  RXO_maclh,
+  RXO_msbhi,
+  RXO_msblh,
+  RXO_msblo,
+  RXO_mullh,
+  RXO_mvfacgu,
+  RXO_mvtacgu,
+  RXO_racl,
+  RXO_rdacl,
+  RXO_rdacw,
+
+  RXO_bfmov,
+  RXO_bfmovz,
+  RXO_rstr,
+  RXO_save,
+  RXO_dmov,
+  RXO_dpopm,
+  RXO_dpushm,
+  RXO_mvfdc,
+  RXO_mvfdr,
+  RXO_mvtdc,
+  RXO_dabs,
+  RXO_dadd,
+  RXO_dcmp,
+  RXO_ddiv,
+  RXO_dmul,
+  RXO_dneg,
+  RXO_dround,
+  RXO_dsqrt,
+  RXO_dsub,
+  RXO_dtoi,
+  RXO_dtof,
+  RXO_dtou,
+  RXO_ftod,
+  RXO_itod,
+  RXO_utod
 } RX_Opcode_ID;
 
 /* Condition bitpatterns, as registers.  */
@@ -213,3 +274,7 @@ typedef struct
    registers.  32..47 are condition codes.  */
 
 int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *);
+
+#ifdef __cplusplus
+}
+#endif