Automatic date update in version.in

[deliverable/binutils-gdb.git] / include / opcode / sparc.h

diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 6e8d6d7bc065604bfe3cf85891334e0f2400440c..bebed45620f6eb45c9ba4ad35d134a45b25f1296 100644 (file)
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -1,5 +1,5 @@
 /* Definitions for opcode table for the sparc.
-   Copyright (C) 1989-2017 Free Software Foundation, Inc.
+   Copyright (C) 1989-2019 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
    the GNU Binutils.
@@ -58,7 +58,8 @@ enum sparc_opcode_arch_val
   SPARC_OPCODE_ARCH_V9V, /* V9 with OSA2011 and T4 additions, integer
                             multiply and Fujitsu fp multiply-add.  */
   SPARC_OPCODE_ARCH_V9M, /* V9 with OSA2015 and M7 additions.  */
-  SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_V9M,
+  SPARC_OPCODE_ARCH_M8,  /* V9 with OSA2017 and M8 additions.  */
+  SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_M8,
   SPARC_OPCODE_ARCH_BAD  /* Error return from sparc_opcode_lookup_arch.  */
 };
 
@@ -184,6 +185,15 @@ typedef struct
 #define HWCAP2_FJDES     0x00002000 /* Fujitsu DES instrs */
 #define HWCAP2_FJAES     0x00010000 /* Fujitsu AES instrs */
 
+#define HWCAP2_SPARC6    0x00020000 /* OSA2017 new instructions */
+#define HWCAP2_ONADDSUB  0x00040000 /* Oracle Number add/subtract */
+#define HWCAP2_ONMUL     0x00080000 /* Oracle Number multiply */
+#define HWCAP2_ONDIV     0x00100000 /* Oracle Number divide */
+#define HWCAP2_DICTUNP   0x00200000 /* Dictionary unpack instruction */
+#define HWCAP2_FPCMPSHL  0x00400000 /* Partition compare with shifted result */
+#define HWCAP2_RLE       0x00800000 /* Run-length encoded burst and length */
+#define HWCAP2_SHA3      0x01000000 /* SHA3 instruction */
+
 
 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
    macro), which is 64 bits. It is handled as a special case.
@@ -202,15 +212,19 @@ typedef struct
        e       frs1 floating point register.
        v       frs1 floating point register (double/even).
        V       frs1 floating point register (quad/multiple of 4).
+       ;       frs1 floating piont register (multiple of 8).
        f       frs2 floating point register.
        B       frs2 floating point register (double/even).
        R       frs2 floating point register (quad/multiple of 4).
+       :       frs2 floating point register (multiple of 8).
+       '       rs2m floating point register (double/even) in FPCMPSHL. (m8)
        4       frs3 floating point register.
        5       frs3 floating point register (doube/even).
        g       frsd floating point register.
        H       frsd floating point register (double/even).
        J       frsd floating point register (quad/multiple of 4).
        }       frsd floating point register (double/even) that is == frs2
+       ^       frsd floating piont register in ON instructions.
        b       crs1 coprocessor register
        c       crs2 coprocessor register
        D       crsd coprocessor register
@@ -253,6 +267,7 @@ typedef struct
        P       %pc.  (v9)
        W       %tick.  (v9)
        {       %mcdper. (v9b)
+       &       %entropy.  (m8)
        o       %asi. (v9)
        6       %fcc0. (v9)
        7       %fcc1. (v9)
@@ -269,7 +284,8 @@ typedef struct
        /       Ancillary state register in rs1 (v9a)
        (       entire floating point state register (%efsr)
        )       5 bit immediate placed in RS3 field
-       =       2+8 bit PC relative immediate. (v9)  */
+       =       2+8 bit PC relative immediate. (v9)
+       |       FPCMPSHL 2 bit immediate. (m8)  */
 
 #define OP2(x)         (((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */
 #define OP3(x)         (((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */
@@ -277,6 +293,10 @@ typedef struct
 #define OPF(x)         (((x) & 0x1ff) << 5) /* Opf field of float insns.  */
 #define OPF_LOW5(x)    OPF ((x) & 0x1f)     /* V9.  */
 #define OPF_LOW4(x)    OPF ((x) & 0xf)      /* V9.  */
+#define OPM(x)         (((x) & 0x7) << 10)  /* opm field of misaligned load/store insns.  */
+#define OPMI(x)        (((x) & 0x1) << 9)   /* opm i field of misaligned load/store insns.  */
+#define ONFCN(x)       (((x) & 0x3) << 26)  /* fcn field of Oracle Number insns.  */
+#define REVFCN(x)      (((x) & 0x3) << 0)   /* fcn field of REV* insns.  */
 #define F3F(x, y, z)   (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
 #define F3F4(x, y, z)  (OP (x) | OP3 (y) | OPF_LOW4 (z))
 #define F3I(x)         (((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
@@ -287,6 +307,7 @@ typedef struct
 #define ASI(x)         (((x) & 0xff) << 5)  /* Asi field of format3 insns.  */
 #define RS2(x)         ((x) & 0x1f)         /* Rs2 field.  */
 #define SIMM13(x)      ((x) & 0x1fff)       /* Simm13 field.  */
+#define SIMM10(x)      ((x) & 0x3ff)        /* Simm10 field.  */
 #define RD(x)          (((x) & 0x1f) << 25) /* Destination register field.  */
 #define RS1(x)         (((x) & 0x1f) << 14) /* Rs1 field.  */
 #define RS3(x)         (((x) & 0x1f) << 9)  /* Rs3 field.  */