Add support for RISC-V architecture.

[deliverable/binutils-gdb.git] / ld / Makefile.am

diff --git a/ld/Makefile.am b/ld/Makefile.am
index 1a7fc3fe670bf73fd97324df6799736f92b3daf1..9b3de728731c1fbd62b0078eb2ab08529eabad15 100644 (file)
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -278,6 +278,7 @@ ALL_EMULATION_SOURCES = \
        eelf32ppcsim.c \
        eelf32ppcvxworks.c \
        eelf32ppcwindiss.c \
+       eelf32lriscv.c \
        eelf32rl78.c \
        eelf32rx.c \
        eelf32tilegx.c \
@@ -494,6 +495,7 @@ ALL_64_EMULATION_SOURCES = \
        eelf64btsmip_fbsd.c \
        eelf64hppa.c \
        eelf64lppc.c \
+       eelf64lriscv.c \
        eelf64ltsmip.c \
        eelf64ltsmip_fbsd.c \
        eelf64mmix.c \
@@ -1165,6 +1167,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \
   $(srcdir)/emultempl/ppc32elf.em ldemul-list.h \
   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 
+eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \
+  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
+  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
+  ${GEN_DEPENDS}
+
 eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \
   $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \
   $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
@@ -1959,6 +1966,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \
   ldemul-list.h \
   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 
+eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \
+  $(srcdir)/emulparams/elf64lriscv-defs.sh \
+  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
+  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
+  ${GEN_DEPENDS}
+
 eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \
   $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \
   $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \