[binutils][Arm] Fix Branch Future relocation handling and testisms

[deliverable/binutils-gdb.git] / ld / testsuite / ld-arm / tls-app.d

diff --git a/ld/testsuite/ld-arm/tls-app.d b/ld/testsuite/ld-arm/tls-app.d
index de0cbab9616888e7477cbdcbc6acd8cdeaf196b6..454adcd066cd0696ea38db52a00968d6c9e6f3a1 100644 (file)
--- a/ld/testsuite/ld-arm/tls-app.d
+++ b/ld/testsuite/ld-arm/tls-app.d
@@ -2,17 +2,17 @@
 .*:     file format elf32-.*arm.*
 architecture: arm.*, flags 0x00000112:
 EXEC_P, HAS_SYMS, D_PAGED
-start address 0x000081c8
+start address 0x00008[0-9a-f]+
 
 Disassembly of section .text:
 
-000081c8 <foo>:
-    81c8:      e1a00000        nop                     ; \(mov r0, r0\)
-    81cc:      e1a00000        nop                     ; \(mov r0, r0\)
-    81d0:      e1a0f00e        mov     pc, lr
-    81d4:      000080bc        .word   0x000080bc
-    81d8:      000080b4        .word   0x000080b4
-    81dc:      000080ac        .word   0x000080ac
-    81e0:      00000004        .word   0x00000004
-    81e4:      000080c4        .word   0x000080c4
-    81e8:      00000014        .word   0x00000014
+00008[0-9a-f]+ <foo>:
+    8[0-9a-f]+:        e1a00000        nop                     ; \(mov r0, r0\)
+    8[0-9a-f]+:        e1a00000        nop                     ; \(mov r0, r0\)
+    8[0-9a-f]+:        e1a0f00e        mov     pc, lr
+    8[0-9a-f]+:        000080bc        .word   0x000080bc
+    8[0-9a-f]+:        000080b4        .word   0x000080b4
+    8[0-9a-f]+:        000080ac        .word   0x000080ac
+    8[0-9a-f]+:        00000004        .word   0x00000004
+    8[0-9a-f]+:        000080c4        .word   0x000080c4
+    8[0-9a-f]+:        00000014        .word   0x00000014