Add support for .extCondCode, .extCoreRegister and .extAuxRegister.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
index 0a78719cb2e3a885a36aef4a58289d5714c94878..04b497612c65d5711cfebf54e5b05768431efef0 100644 (file)
@@ -1,3 +1,189 @@
+2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-dis.c (find_format): Check for extension flags.
+       (print_flags): New function.
+       (print_insn_arc): Update for .extCondCode, .extCoreRegister and
+       .extAuxRegister.
+       * arc-ext.c (arcExtMap_coreRegName): Use
+       LAST_EXTENSION_CORE_REGISTER.
+       (arcExtMap_coreReadWrite): Likewise.
+       (dump_ARC_extmap): Update printing.
+       * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
+       (arc_aux_regs): Add cpu field.
+       * arc-regs.h: Add cpu field, lower case name aux registers.
+
+2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-tbl.h: Add rtsc, sleep with no arguments.
+
+2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
+       Initialize.
+       (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
+       (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
+       (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
+       (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
+       (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
+       (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
+       (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
+       (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
+       (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
+       (arc_opcode arc_opcodes): Null terminate the array.
+       (arc_num_opcodes): Remove.
+       * arc-ext.h (INSERT_XOP): Define.
+       (extInstruction_t): Likewise.
+       (arcExtMap_instName): Delete.
+       (arcExtMap_insn): New function.
+       (arcExtMap_genOpcode): Likewise.
+       * arc-ext.c (ExtInstruction): Remove.
+       (create_map): Zero initialize instruction fields.
+       (arcExtMap_instName): Remove.
+       (arcExtMap_insn): New function.
+       (dump_ARC_extmap): More info while debuging.
+       (arcExtMap_genOpcode): New function.
+       * arc-dis.c (find_format): New function.
+       (print_insn_arc): Use find_format.
+       (arc_get_disassembler): Enable dump_ARC_extmap only when
+       debugging.
+
+2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (print_mips16_insn_arg): Mask unused extended
+       instruction bits out.
+
+2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
+       * arc-opc.c (arc_flag_operands): Add new flags.
+       (arc_flag_classes): Add new classes.
+
+2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
+
+2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
+       encode1, rflt, crc16, and crc32 instructions.
+       * arc-opc.c (arc_flag_operands): Add F_NPS_R.
+       (arc_flag_classes): Add C_NPS_R.
+       (insert_nps_bitop_size_2b): New function.
+       (extract_nps_bitop_size_2b): Likewise.
+       (insert_nps_bitop_uimm8): Likewise.
+       (extract_nps_bitop_uimm8): Likewise.
+       (arc_operands): Add new operand entries.
+
+2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-regs.h: Add a new subclass field.  Add double assist
+       accumulator register values.
+       * arc-tbl.h: Use DPA subclass to mark the double assist
+       instructions.  Use DPX/SPX subclas to mark the FPX instructions.
+       * arc-opc.c (RSP): Define instead of SP.
+       (arc_aux_regs): Add the subclass field.
+
+2016-04-05  Jiong Wang  <jiong.wang@arm.com>
+
+       * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
+
+2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
+       NPS_R_SRC1.
+
+2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
+       issues.  No functional changes.
+
+2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
+       (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
+       (RTT): Remove duplicate.
+       (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
+       (PCT_CONFIG*): Remove.
+       (D1L, D1H, D2H, D2L): Define.
+
+2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
+
+2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-tbl.h (invld07): Remove.
+       * arc-ext-tbl.h: New file.
+       * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
+       * arc-opc.c (arc_opcodes): Add ext-tbl include.
+
+2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+       Fix -Wstack-usage warnings.
+       * aarch64-dis.c (print_operands): Substitute size.
+       * aarch64-opc.c (print_register_offset_address): Substitute tblen.
+
+2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
+       to get a proper diagnostic when an invalid ASR register is used.
+
+2016-03-22  Nick Clifton  <nickc@redhat.com>
+
+       * configure: Regenerate.
+
+2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-nps400-tbl.h: New file.
+       * arc-opc.c: Add top level comment.
+       (insert_nps_3bit_dst): New function.
+       (extract_nps_3bit_dst): New function.
+       (insert_nps_3bit_src2): New function.
+       (extract_nps_3bit_src2): New function.
+       (insert_nps_bitop_size): New function.
+       (extract_nps_bitop_size): New function.
+       (arc_flag_operands): Add nps400 entries.
+       (arc_flag_classes): Add nps400 entries.
+       (arc_operands): Add nps400 entries.
+       (arc_opcodes): Add nps400 include.
+
+2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-opc.c (arc_flag_classes): Convert all flag classes to use
+       the new class enum values.
+
+2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-dis.c (print_insn_arc): Handle nps400.
+
+2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-opc.c (BASE): Delete.
+
+2016-03-18  Nick Clifton  <nickc@redhat.com>
+
+       PR target/19721
+       * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
+       of MOV insn that aliases an ORR insn.
+
+2016-03-16  Jiong Wang  <jiong.wang@arm.com>
+
+       * arm-dis.c (neon_opcodes): Support new FP16 instructions.
+
+2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
+
+       * mcore-opc.h: Add const qualifiers.
+       * microblaze-opc.h (struct op_code_struct): Likewise.
+       * sh-opc.h: Likewise.
+       * tic4x-dis.c (tic4x_print_indirect): Likewise.
+       (tic4x_print_op): Likewise.
+
+2016-03-02  Alan Modra  <amodra@gmail.com>
+
+       * or1k-desc.h: Regenerate.
+       * fr30-ibld.c: Regenerate.
+       * rl78-decode.c: Regenerate.
+
 2016-03-01  Nick Clifton  <nickc@redhat.com>
 
        PR target/19747
 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
            Janek van Oirschot  <jvanoirs@synopsys.com>
 
-        * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
-        variable.
+       * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
+       variable.
 
 2016-02-04  Nick Clifton  <nickc@redhat.com>
 
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