+2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
+
+ * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
+ * configure.ac: Remove AC_PREREQ.
+ * Makefile.in: Re-generate.
+ * aclocal.m4: Re-generate.
+ * configure: Re-generate.
+
+2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
+
+ * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
+ mips64r6 descriptors.
+ (parse_mips_ase_option): Handle -Mginv option.
+ (print_mips_disassembler_options): Document -Mginv.
+ * mips-opc.c (decode_mips_operand) <+\>: New operand format.
+ (GINV): New macro.
+ (mips_opcodes): Define ginvi and ginvt.
+
+2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
+ Faraz Shahbazker <Faraz.Shahbazker@mips.com>
+
+ * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
+ * mips-opc.c (CRC, CRC64): New macros.
+ (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
+ crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
+ crc32cd for CRC64.
+
+2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
+
+ PR 20319
+ * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
+ (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
+
+2018-06-06 Alan Modra <amodra@gmail.com>
+
+ * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
+ setjmp. Move init for some other vars later too.
+
+2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
+
+ * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
+ (dis_private): Add new fields for property section tracking.
+ (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
+ (xtensa_instruction_fits): New functions.
+ (fetch_data): Bump minimal fetch size to 4.
+ (print_insn_xtensa): Make struct dis_private static.
+ Load and prepare property table on section change.
+ Don't disassemble literals. Don't disassemble instructions that
+ cross property table boundaries.
+
+2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+
+2018-06-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
+ * i386-tbl.h: Re-generate.
+
+2018-06-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (sldt, str): Add NoRex64.
+ * i386-tbl.h: Re-generate.
+
+2018-06-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (invpcid): Add Oword.
+ * i386-tbl.h: Re-generate.
+
+2018-06-01 Alan Modra <amodra@gmail.com>
+
+ * sysdep.h (_bfd_error_handler): Don't declare.
+ * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
+ * rl78-decode.opc: Likewise.
+ * msp430-decode.c: Regenerate.
+ * rl78-decode.c: Regenerate.
+
+2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
+
+ * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
+ * i386-init.h : Regenerated.
+
+2018-05-25 Alan Modra <amodra@gmail.com>
+
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
+
+ * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
+ insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
+ (insert_bab, extract_bab, insert_btab, extract_btab,
+ insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
+ (BAT, BBA VBA RBS XB6S): Delete macros.
+ (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
+ (BB, BD, RBX, XC6): Update for new macros.
+ (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
+ crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
+ e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
+ * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
+
+2018-05-18 John Darrington <john@darrington.wattle.id.au>
+
+ * Makefile.am: Add support for s12z architecture.
+ * configure.ac: Likewise.
+ * disassemble.c: Likewise.
+ * disassemble.h: Likewise.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * s12z-dis.c: New file.
+ * s12z.h: New file.
+
+2018-05-18 Alan Modra <amodra@gmail.com>
+
+ * nfp-dis.c: Don't #include libbfd.h.
+ (init_nfp3200_priv): Use bfd_get_section_contents.
+ (nit_nfp6000_mecsr_sec): Likewise.
+
+2018-05-17 Nick Clifton <nickc@redhat.com>
+
+ * po/zh_CN.po: Updated simplified Chinese translation.
+
+2018-05-16 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/23109
+ * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
+ * aarch64-dis-2.c: Regenerate.
+
+2018-05-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/21446
+ * aarch64-asm.c (opintl.h): Include.
+ (aarch64_ins_sysreg): Enforce read/write constraints.
+ * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
+ * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
+ (F_REG_READ, F_REG_WRITE): New.
+ * aarch64-opc.c (aarch64_print_operand): Generate notes for
+ AARCH64_OPND_SYSREG.
+ (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
+ (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
+ mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
+ id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
+ id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
+ id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
+ mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
+ id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
+ id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
+ id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
+ csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
+ rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
+ mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
+ mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
+ pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
+ * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
+ msr (F_SYS_WRITE), mrs (F_SYS_READ).
+
+2018-05-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/21446
+ * aarch64-dis.c (no_notes: New.
+ (parse_aarch64_dis_option): Support notes.
+ (aarch64_decode_insn, print_operands): Likewise.
+ (print_aarch64_disassembler_options): Document notes.
+ * aarch64-opc.c (aarch64_print_operand): Support notes.
+
+2018-05-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/21446
+ * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
+ and take error struct.
+ * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
+ aarch64_ins_reglist, aarch64_ins_ldst_reglist,
+ aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
+ aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
+ aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
+ aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
+ aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
+ aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
+ aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
+ aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
+ aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
+ aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
+ aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
+ aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
+ aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
+ aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
+ aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
+ aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
+ aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
+ aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
+ aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
+ aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
+ aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
+ aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
+ aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
+ * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
+ * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
+ aarch64_ext_reglist, aarch64_ext_ldst_reglist,
+ aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
+ aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
+ aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
+ aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
+ aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
+ aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
+ aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
+ aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
+ aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
+ aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
+ aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
+ aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
+ aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
+ aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
+ aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
+ aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
+ aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
+ aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
+ aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
+ aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
+ aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
+ aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
+ aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
+ (determine_disassembling_preference, aarch64_decode_insn,
+ print_insn_aarch64_word, print_insn_data): Take errors struct.
+ (print_insn_aarch64): Use errors.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-gen.c (print_operand_inserter): Use errors and change type to
+ boolean in aarch64_insert_operan.
+ (print_operand_extractor): Likewise.
+ * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
+
+2018-05-15 Francois H. Theron <francois.theron@netronome.com>
+
+ * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
+
+2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
+
+2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
+
+ * cr16-opc.c (cr16_instruction): Comment typo fix.
+ * hppa-dis.c (print_insn_hppa): Likewise.
+
+2018-05-08 Jim Wilson <jimw@sifive.com>
+
+ * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
+ (match_c_slli64, match_srxi_as_c_srxi): New.
+ (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
+ <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
+ <c.slli, c.srli, c.srai>: Use match_s_slli.
+ <c.slli64, c.srli64, c.srai64>: New.
+
+2018-05-08 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
+ (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
+ partition opcode space for index lookup.
+
+2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
+
+ * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
+ <insn_length>: ...with this. Update usage.
+ Remove duplicate call to *info->memory_error_func.
+
+2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+ H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (Gva): New.
+ (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
+ MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
+ (prefix_table): New instructions (see prefix above).
+ (mod_table): New instructions (see prefix above).
+ (OP_G): Handle va_mode.
+ * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
+ CPU_MOVDIR64B_FLAGS.
+ (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
+ * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
+ (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
+ * i386-opc.tbl: Add movidir{i,64b}.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
projects / deliverable / binutils-gdb.git / blobdiff