+2019-11-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_instances): Add RegB entry.
+ * i386-opc.h (enum operand_instance): Add RegB.
+ * i386-opc.tbl (RegC, RegD, RegB): Define.
+ (Acc, ShiftCount, InOutPortReg): Adjust definitions.
+ (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
+ monitorx, mwaitx): Drop ImmExt and convert encodings
+ accordingly.
+ * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
+ (edx, rdx): Add Instance=RegD.
+ (ebx, rbx): Add Instance=RegB.
+ * i386-tbl.h: Re-generate.
+
+2019-11-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Adjust
+ OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
+ OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
+ OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
+ (operand_instances): New.
+ (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
+ (output_operand_type): New parameter "instance". Process it.
+ (process_i386_operand_type): New local variable "instance".
+ (main): Adjust static assertions.
+ * i386-opc.h (INSTANCE_WIDTH): Define.
+ (enum operand_instance): New.
+ (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
+ (union i386_operand_type): Replace acc, inoutportreg, and
+ shiftcount by instance.
+ * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
+ * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
+ Add Instance=.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-11 Jan Beulich <jbeulich@suse.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
+ smaxp/sminp entries' "tied_operand" field to 2.
+
+2019-11-11 Jan Beulich <jbeulich@suse.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Replace
+ "index" local variable by that of the already existing "num".
+
+2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25167
+ * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
+ * i386-tbl.h: Regenerated.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
+ OPERAND_TYPE_REGBND entry.
+ (operand_classes): Add RegMask and RegBND entries.
+ (operand_types): Drop RegMask and RegBND entry.
+ * i386-opc.h (enum operand_class): Add RegMask and RegBND.
+ (RegMask, RegBND): Delete.
+ (union i386_operand_type): Remove regmask and regbnd fields.
+ * i386-opc.tbl (RegMask, RegBND): Define.
+ * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
+ Class=RegBND.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
+ OPERAND_TYPE_REGZMM entries.
+ (operand_classes): Add RegMMX and RegSIMD entries.
+ (operand_types): Drop RegMMX and RegSIMD entries.
+ * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
+ (RegMMX, RegSIMD): Delete.
+ (union i386_operand_type): Remove regmmx and regsimd fields.
+ * i386-opc.tbl (RegMMX): Define.
+ (RegXMM, RegYMM, RegZMM): Add Class=.
+ * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
+ Class=RegSIMD.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
+ entries.
+ (operand_classes): Add RegCR, RegDR, and RegTR entries.
+ (operand_types): Drop Control, Debug, and Test entries.
+ * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
+ (Control, Debug, Test): Delete.
+ (union i386_operand_type): Remove control, debug, and test
+ fields.
+ * i386-opc.tbl (Control, Debug, Test): Define.
+ * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
+ Class=RegDR, and Test by Class=RegTR.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
2019-11-08 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class= to