GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 666238d906d20d8590bb4f3660fe62da57503c3f..149737e1ed62d5a86c731ab54e9297929414f0f0 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,92 @@
+2018-07-02  Maciej W. Rozycki  <macro@mips.com>
+
+       PR tdep/8282
+       * mips-dis.c (mips_option_arg_t): New enumeration.
+       (mips_options): New variable.
+       (disassembler_options_mips): New function.
+       (print_mips_disassembler_options): Reimplement in terms of
+       `disassembler_options_mips'.
+       * arm-dis.c (disassembler_options_arm): Adapt to using the
+       `disasm_options_and_args_t' structure.
+       * ppc-dis.c (disassembler_options_powerpc): Likewise.
+       * s390-dis.c (disassembler_options_s390): Likewise.
+
+2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
+       expected result.
+       * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
+       * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
+       * testsuite/ld-arm/tls-longplt.d: Likewise.
+
+2018-06-29  Tamar Christina  <tamar.christina@arm.com>
+
+       PR binutils/23192
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Likewise.
+       * aarch64-opc-2.c: Likewise.
+       * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
+       * aarch64-opc.c (operand_general_constraint_met_p,
+       aarch64_print_operand): Likewise.
+       * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
+       smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
+       fmlal2, fmlsl2.
+       (AARCH64_OPERANDS): Add Em2.
+
+2018-06-26  Nick Clifton  <nickc@redhat.com>
+
+       * po/uk.po: Updated Ukranian translation.
+       * po/de.po: Updated German translation.
+       * po/pt_BR.po: Updated Brazilian Portuguese translation.
+
+2018-06-26  Nick Clifton  <nickc@redhat.com>
+
+       * nfp-dis.c: Fix spelling mistake.
+
+2018-06-24  Nick Clifton  <nickc@redhat.com>
+
+       * configure: Regenerate.
+       * po/opcodes.pot: Regenerate.
+
+2018-06-24  Nick Clifton  <nickc@redhat.com>
+
+       2.31 branch created.
+
+2018-06-19  Tamar Christina  <tamar.christina@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Likewise.
+
+2018-06-21  Maciej W. Rozycki  <macro@mips.com>
+
+       * mips-dis.c (print_mips_disassembler_options): Fix a typo in
+       `-M ginv' option description.
+
+2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
+
+       PR gas/23305
+       * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
+       la and lla.
+
+2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
+
+       * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
+       * configure.ac: Remove AC_PREREQ.
+       * Makefile.in: Re-generate.
+       * aclocal.m4: Re-generate.
+       * configure: Re-generate.
+
+2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
+
+       * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
+       mips64r6 descriptors.
+       (parse_mips_ase_option): Handle -Mginv option.
+       (print_mips_disassembler_options): Document -Mginv.
+       * mips-opc.c (decode_mips_operand) <+\>: New operand format.
+       (GINV): New macro.
+       (mips_opcodes): Define ginvi and ginvt.
+
 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>