+2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-opc.c (UIMM6_20R): Define.
+ (SIMM12_20): Use above.
+ (SIMM12_20R): Define.
+ (SIMM3_5_S): Use above.
+ (UIMM7_A32_11R_S): Define.
+ (UIMM7_9_S): Use above.
+ (UIMM3_13R_S): Define.
+ (SIMM11_A32_7_S): Use above.
+ (SIMM9_8R): Define.
+ (UIMM10_A32_8_S): Use above.
+ (UIMM8_8R_S): Define.
+ (W6): Use above.
+ (arc_relax_opcodes): Use all above defines.
+
+2017-02-15 Vineet Gupta <vgupta@synopsys.com>
+
+ * arc-regs.h: Distinguish some of the registers different on
+ ARC700 and HS38 cpus.
+
+2017-02-14 Alan Modra <amodra@gmail.com>
+
+ PR 21118
+ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
+ with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
+
+2017-02-11 Stafford Horne <shorne@gmail.com>
+ Alan Modra <amodra@gmail.com>
+
+ * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
+ Use insn_bytes_value and insn_int_value directly instead. Don't
+ free allocated memory until function exit.
+
+2017-02-10 Nicholas Piggin <npiggin@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
+
+2017-02-03 Nick Clifton <nickc@redhat.com>
+
+ PR 21096
+ * aarch64-opc.c (print_register_list): Ensure that the register
+ list index will fir into the tb buffer.
+ (print_register_offset_address): Likewise.
+ * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
+
+2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
+
+ PR 21056
+ * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
+ instructions when the previous fetch packet ends with a 32-bit
+ instruction.
+
2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
* pru-opc.c: Remove vague reference to a future GDB port.