+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
+ (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
+ * aarch64-dis.c (insn_sequence): New.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
+ _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
+ _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
+ V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
+ constraints.
+ (_SVE_INSNC): New.
+ (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
+ constraints.
+ (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
+ F_SCAN flags.
+ (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
+ sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
+ sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
+ sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
+ uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
+ uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
+ C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
+
+2018-10-02 Palmer Dabbelt <palmer@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
+
+2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
+
+ * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
+ are used when extracting signed fields and converting them to
+ potentially 64-bit types.
+
+2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
+
+ * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
+ * Makefile.in: Re-generate.
+ * aclocal.m4: Re-generate.
+ * configure: Re-generate.
+ * configure.ac: Remove check for -Wno-missing-field-initializers.
+ * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
+ (csky_v2_opcodes): Likewise.
+
+2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
+
+ * arc-nps400-tbl.h: Append `ull' to large constants throughout.
+
+2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
+
+ * nds32-asm.c (operand_fields): Remove the unused fields.
+ (nds32_opcodes): Remove the unused instructions.
+ * nds32-dis.c (nds32_ex9_info): Removed.
+ (nds32_parse_opcode): Updated.
+ (print_insn_nds32): Likewise.
+ * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
+ (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
+ (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
+ build_opcode_hash_table): New functions.
+ (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
+ nds32_opcode_table): New.
+ (hw_ktabs): Declare it to a pointer rather than an array.
+ (build_hash_table): Removed.
+ * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
+ SYN_ROPT and upadte HW_GPR and HW_INT.
+ * nds32-dis.c (keywords): Remove const.
+ (match_field): New function.
+ (nds32_parse_opcode): Updated.
+ * disassemble.c (disassemble_init_for_target):
+ Add disassemble_init_nds32.
+ * nds32-dis.c (eum map_type): New.
+ (nds32_private_data): Likewise.
+ (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
+ nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
+ (print_insn_nds32): Updated.
+ * nds32-asm.c (parse_aext_reg): Add new parameter.
+ (parse_re, parse_re2, parse_aext_reg): Only reduced registers
+ are allowed to use.
+ All callers changed.
+ * nds32-asm.c (keyword_usr, keyword_sr): Updated.
+ (operand_fields): Add new fields.
+ (nds32_opcodes): Add new instructions.
+ (keyword_aridxi_mx): New keyword.
+ * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
+ and NASM_ATTR_ZOL.
+ (ALU2_1, ALU2_2, ALU2_3): New macros.
+ * nds32-dis.c (nds32_filter_unknown_insn): Updated.
+
+2018-09-17 Kito Cheng <kito@andestech.com>
+
+ * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
+
+2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/23670
+ * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
+ EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
+ (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
+ (EVEX_LEN_0F7E_P_1): Likewise.
+ (EVEX_LEN_0F7E_P_2): Likewise.
+ (EVEX_LEN_0FD6_P_2): Likewise.
+ * i386-dis.c (USE_EVEX_LEN_TABLE): New.
+ (EVEX_LEN_TABLE): Likewise.
+ (EVEX_LEN_0F6E_P_2): New enum.
+ (EVEX_LEN_0F7E_P_1): Likewise.
+ (EVEX_LEN_0F7E_P_2): Likewise.
+ (EVEX_LEN_0FD6_P_2): Likewise.
+ (evex_len_table): New.
+ (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
+ * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
+ * i386-tbl.h: Regenerated.
+
2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
PR gas/23665
projects / deliverable / binutils-gdb.git / blobdiff