+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-opc.c (init_insn_block): New.
+ (verify_constraints, aarch64_is_destructive_by_operands): New.
+ * aarch64-opc.h (verify_constraints): New.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
+ * aarch64-opc.c (verify_ldpsw): Update arguments.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
+ (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
+ * aarch64-dis.c (insn_sequence): New.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
+ _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
+ _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
+ V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
+ constraints.
+ (_SVE_INSNC): New.
+ (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
+ constraints.
+ (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
+ F_SCAN flags.
+ (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
+ sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
+ sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
+ sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
+ uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
+ uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
+ C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
+
+2018-10-02 Palmer Dabbelt <palmer@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
+
+2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
+
+ * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
+ are used when extracting signed fields and converting them to
+ potentially 64-bit types.
+
+2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
+
+ * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
+ * Makefile.in: Re-generate.
+ * aclocal.m4: Re-generate.
+ * configure: Re-generate.
+ * configure.ac: Remove check for -Wno-missing-field-initializers.
+ * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
+ (csky_v2_opcodes): Likewise.
+
+2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
+
+ * arc-nps400-tbl.h: Append `ull' to large constants throughout.
+
+2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
+
+ * nds32-asm.c (operand_fields): Remove the unused fields.
+ (nds32_opcodes): Remove the unused instructions.
+ * nds32-dis.c (nds32_ex9_info): Removed.
+ (nds32_parse_opcode): Updated.
+ (print_insn_nds32): Likewise.
+ * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
+ (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
+ (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
+ build_opcode_hash_table): New functions.
+ (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
+ nds32_opcode_table): New.
+ (hw_ktabs): Declare it to a pointer rather than an array.
+ (build_hash_table): Removed.
+ * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
+ SYN_ROPT and upadte HW_GPR and HW_INT.
+ * nds32-dis.c (keywords): Remove const.
+ (match_field): New function.
+ (nds32_parse_opcode): Updated.
+ * disassemble.c (disassemble_init_for_target):
+ Add disassemble_init_nds32.
+ * nds32-dis.c (eum map_type): New.
+ (nds32_private_data): Likewise.
+ (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
+ nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
+ (print_insn_nds32): Updated.
+ * nds32-asm.c (parse_aext_reg): Add new parameter.
+ (parse_re, parse_re2, parse_aext_reg): Only reduced registers
+ are allowed to use.
+ All callers changed.
+ * nds32-asm.c (keyword_usr, keyword_sr): Updated.
+ (operand_fields): Add new fields.
+ (nds32_opcodes): Add new instructions.
+ (keyword_aridxi_mx): New keyword.
+ * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
+ and NASM_ATTR_ZOL.
+ (ALU2_1, ALU2_2, ALU2_3): New macros.
+ * nds32-dis.c (nds32_filter_unknown_insn): Updated.
+
+2018-09-17 Kito Cheng <kito@andestech.com>
+
+ * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
+
+2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/23670
+ * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
+ EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
+ (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
+ (EVEX_LEN_0F7E_P_1): Likewise.
+ (EVEX_LEN_0F7E_P_2): Likewise.
+ (EVEX_LEN_0FD6_P_2): Likewise.
+ * i386-dis.c (USE_EVEX_LEN_TABLE): New.
+ (EVEX_LEN_TABLE): Likewise.
+ (EVEX_LEN_0F6E_P_2): New enum.
+ (EVEX_LEN_0F7E_P_1): Likewise.
+ (EVEX_LEN_0F7E_P_2): Likewise.
+ (EVEX_LEN_0FD6_P_2): Likewise.
+ (evex_len_table): New.
+ (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
+ * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
+ * i386-tbl.h: Regenerated.
+
+2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/23665
+ * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
+ VEX_LEN_0F7E_P_2 entries.
+ * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
+ * i386-tbl.h: Regenerated.
+
+2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (VZERO_Fixup): Removed.
+ (VZERO): Likewise.
+ (VEX_LEN_0F10_P_1): Likewise.
+ (VEX_LEN_0F10_P_3): Likewise.
+ (VEX_LEN_0F11_P_1): Likewise.
+ (VEX_LEN_0F11_P_3): Likewise.
+ (VEX_LEN_0F2E_P_0): Likewise.
+ (VEX_LEN_0F2E_P_2): Likewise.
+ (VEX_LEN_0F2F_P_0): Likewise.
+ (VEX_LEN_0F2F_P_2): Likewise.
+ (VEX_LEN_0F51_P_1): Likewise.
+ (VEX_LEN_0F51_P_3): Likewise.
+ (VEX_LEN_0F52_P_1): Likewise.
+ (VEX_LEN_0F53_P_1): Likewise.
+ (VEX_LEN_0F58_P_1): Likewise.
+ (VEX_LEN_0F58_P_3): Likewise.
+ (VEX_LEN_0F59_P_1): Likewise.
+ (VEX_LEN_0F59_P_3): Likewise.
+ (VEX_LEN_0F5A_P_1): Likewise.
+ (VEX_LEN_0F5A_P_3): Likewise.
+ (VEX_LEN_0F5C_P_1): Likewise.
+ (VEX_LEN_0F5C_P_3): Likewise.
+ (VEX_LEN_0F5D_P_1): Likewise.
+ (VEX_LEN_0F5D_P_3): Likewise.
+ (VEX_LEN_0F5E_P_1): Likewise.
+ (VEX_LEN_0F5E_P_3): Likewise.
+ (VEX_LEN_0F5F_P_1): Likewise.
+ (VEX_LEN_0F5F_P_3): Likewise.
+ (VEX_LEN_0FC2_P_1): Likewise.
+ (VEX_LEN_0FC2_P_3): Likewise.
+ (VEX_LEN_0F3A0A_P_2): Likewise.
+ (VEX_LEN_0F3A0B_P_2): Likewise.
+ (VEX_W_0F10_P_0): Likewise.
+ (VEX_W_0F10_P_1): Likewise.
+ (VEX_W_0F10_P_2): Likewise.
+ (VEX_W_0F10_P_3): Likewise.
+ (VEX_W_0F11_P_0): Likewise.
+ (VEX_W_0F11_P_1): Likewise.
+ (VEX_W_0F11_P_2): Likewise.
+ (VEX_W_0F11_P_3): Likewise.
+ (VEX_W_0F12_P_0_M_0): Likewise.
+ (VEX_W_0F12_P_0_M_1): Likewise.
+ (VEX_W_0F12_P_1): Likewise.
+ (VEX_W_0F12_P_2): Likewise.
+ (VEX_W_0F12_P_3): Likewise.
+ (VEX_W_0F13_M_0): Likewise.
+ (VEX_W_0F14): Likewise.
+ (VEX_W_0F15): Likewise.
+ (VEX_W_0F16_P_0_M_0): Likewise.
+ (VEX_W_0F16_P_0_M_1): Likewise.
+ (VEX_W_0F16_P_1): Likewise.
+ (VEX_W_0F16_P_2): Likewise.
+ (VEX_W_0F17_M_0): Likewise.
+ (VEX_W_0F28): Likewise.
+ (VEX_W_0F29): Likewise.
+ (VEX_W_0F2B_M_0): Likewise.
+ (VEX_W_0F2E_P_0): Likewise.
+ (VEX_W_0F2E_P_2): Likewise.
+ (VEX_W_0F2F_P_0): Likewise.
+ (VEX_W_0F2F_P_2): Likewise.
+ (VEX_W_0F50_M_0): Likewise.
+ (VEX_W_0F51_P_0): Likewise.
+ (VEX_W_0F51_P_1): Likewise.
+ (VEX_W_0F51_P_2): Likewise.
+ (VEX_W_0F51_P_3): Likewise.
+ (VEX_W_0F52_P_0): Likewise.
+ (VEX_W_0F52_P_1): Likewise.
+ (VEX_W_0F53_P_0): Likewise.
+ (VEX_W_0F53_P_1): Likewise.
+ (VEX_W_0F58_P_0): Likewise.
+ (VEX_W_0F58_P_1): Likewise.
+ (VEX_W_0F58_P_2): Likewise.
+ (VEX_W_0F58_P_3): Likewise.
+ (VEX_W_0F59_P_0): Likewise.
+ (VEX_W_0F59_P_1): Likewise.
+ (VEX_W_0F59_P_2): Likewise.
+ (VEX_W_0F59_P_3): Likewise.
+ (VEX_W_0F5A_P_0): Likewise.
+ (VEX_W_0F5A_P_1): Likewise.
+ (VEX_W_0F5A_P_3): Likewise.
+ (VEX_W_0F5B_P_0): Likewise.
+ (VEX_W_0F5B_P_1): Likewise.
+ (VEX_W_0F5B_P_2): Likewise.
+ (VEX_W_0F5C_P_0): Likewise.
+ (VEX_W_0F5C_P_1): Likewise.
+ (VEX_W_0F5C_P_2): Likewise.
+ (VEX_W_0F5C_P_3): Likewise.
+ (VEX_W_0F5D_P_0): Likewise.
+ (VEX_W_0F5D_P_1): Likewise.
+ (VEX_W_0F5D_P_2): Likewise.
+ (VEX_W_0F5D_P_3): Likewise.
+ (VEX_W_0F5E_P_0): Likewise.
+ (VEX_W_0F5E_P_1): Likewise.
+ (VEX_W_0F5E_P_2): Likewise.
+ (VEX_W_0F5E_P_3): Likewise.
+ (VEX_W_0F5F_P_0): Likewise.
+ (VEX_W_0F5F_P_1): Likewise.
+ (VEX_W_0F5F_P_2): Likewise.
+ (VEX_W_0F5F_P_3): Likewise.
+ (VEX_W_0F60_P_2): Likewise.
+ (VEX_W_0F61_P_2): Likewise.
+ (VEX_W_0F62_P_2): Likewise.
+ (VEX_W_0F63_P_2): Likewise.
+ (VEX_W_0F64_P_2): Likewise.
+ (VEX_W_0F65_P_2): Likewise.
+ (VEX_W_0F66_P_2): Likewise.
+ (VEX_W_0F67_P_2): Likewise.
+ (VEX_W_0F68_P_2): Likewise.
+ (VEX_W_0F69_P_2): Likewise.
+ (VEX_W_0F6A_P_2): Likewise.
+ (VEX_W_0F6B_P_2): Likewise.
+ (VEX_W_0F6C_P_2): Likewise.
+ (VEX_W_0F6D_P_2): Likewise.
+ (VEX_W_0F6F_P_1): Likewise.
+ (VEX_W_0F6F_P_2): Likewise.
+ (VEX_W_0F70_P_1): Likewise.
+ (VEX_W_0F70_P_2): Likewise.
+ (VEX_W_0F70_P_3): Likewise.
+ (VEX_W_0F71_R_2_P_2): Likewise.
+ (VEX_W_0F71_R_4_P_2): Likewise.
+ (VEX_W_0F71_R_6_P_2): Likewise.
+ (VEX_W_0F72_R_2_P_2): Likewise.
+ (VEX_W_0F72_R_4_P_2): Likewise.
+ (VEX_W_0F72_R_6_P_2): Likewise.
+ (VEX_W_0F73_R_2_P_2): Likewise.
+ (VEX_W_0F73_R_3_P_2): Likewise.
+ (VEX_W_0F73_R_6_P_2): Likewise.
+ (VEX_W_0F73_R_7_P_2): Likewise.
+ (VEX_W_0F74_P_2): Likewise.
+ (VEX_W_0F75_P_2): Likewise.
+ (VEX_W_0F76_P_2): Likewise.
+ (VEX_W_0F77_P_0): Likewise.
+ (VEX_W_0F7C_P_2): Likewise.
+ (VEX_W_0F7C_P_3): Likewise.
+ (VEX_W_0F7D_P_2): Likewise.
+ (VEX_W_0F7D_P_3): Likewise.
+ (VEX_W_0F7E_P_1): Likewise.
+ (VEX_W_0F7F_P_1): Likewise.
+ (VEX_W_0F7F_P_2): Likewise.
+ (VEX_W_0FAE_R_2_M_0): Likewise.
+ (VEX_W_0FAE_R_3_M_0): Likewise.
+ (VEX_W_0FC2_P_0): Likewise.
+ (VEX_W_0FC2_P_1): Likewise.
+ (VEX_W_0FC2_P_2): Likewise.
+ (VEX_W_0FC2_P_3): Likewise.
+ (VEX_W_0FD0_P_2): Likewise.
+ (VEX_W_0FD0_P_3): Likewise.
+ (VEX_W_0FD1_P_2): Likewise.
+ (VEX_W_0FD2_P_2): Likewise.
+ (VEX_W_0FD3_P_2): Likewise.
+ (VEX_W_0FD4_P_2): Likewise.
+ (VEX_W_0FD5_P_2): Likewise.
+ (VEX_W_0FD6_P_2): Likewise.
+ (VEX_W_0FD7_P_2_M_1): Likewise.
+ (VEX_W_0FD8_P_2): Likewise.
+ (VEX_W_0FD9_P_2): Likewise.
+ (VEX_W_0FDA_P_2): Likewise.
+ (VEX_W_0FDB_P_2): Likewise.
+ (VEX_W_0FDC_P_2): Likewise.
+ (VEX_W_0FDD_P_2): Likewise.
+ (VEX_W_0FDE_P_2): Likewise.
+ (VEX_W_0FDF_P_2): Likewise.
+ (VEX_W_0FE0_P_2): Likewise.
+ (VEX_W_0FE1_P_2): Likewise.
+ (VEX_W_0FE2_P_2): Likewise.
+ (VEX_W_0FE3_P_2): Likewise.
+ (VEX_W_0FE4_P_2): Likewise.
+ (VEX_W_0FE5_P_2): Likewise.
+ (VEX_W_0FE6_P_1): Likewise.
+ (VEX_W_0FE6_P_2): Likewise.
+ (VEX_W_0FE6_P_3): Likewise.
+ (VEX_W_0FE7_P_2_M_0): Likewise.
+ (VEX_W_0FE8_P_2): Likewise.
+ (VEX_W_0FE9_P_2): Likewise.
+ (VEX_W_0FEA_P_2): Likewise.
+ (VEX_W_0FEB_P_2): Likewise.
+ (VEX_W_0FEC_P_2): Likewise.
+ (VEX_W_0FED_P_2): Likewise.
+ (VEX_W_0FEE_P_2): Likewise.
+ (VEX_W_0FEF_P_2): Likewise.
+ (VEX_W_0FF0_P_3_M_0): Likewise.
+ (VEX_W_0FF1_P_2): Likewise.
+ (VEX_W_0FF2_P_2): Likewise.
+ (VEX_W_0FF3_P_2): Likewise.
+ (VEX_W_0FF4_P_2): Likewise.
+ (VEX_W_0FF5_P_2): Likewise.
+ (VEX_W_0FF6_P_2): Likewise.
+ (VEX_W_0FF7_P_2): Likewise.
+ (VEX_W_0FF8_P_2): Likewise.
+ (VEX_W_0FF9_P_2): Likewise.
+ (VEX_W_0FFA_P_2): Likewise.
+ (VEX_W_0FFB_P_2): Likewise.
+ (VEX_W_0FFC_P_2): Likewise.
+ (VEX_W_0FFD_P_2): Likewise.
+ (VEX_W_0FFE_P_2): Likewise.
+ (VEX_W_0F3800_P_2): Likewise.
+ (VEX_W_0F3801_P_2): Likewise.
+ (VEX_W_0F3802_P_2): Likewise.
+ (VEX_W_0F3803_P_2): Likewise.
+ (VEX_W_0F3804_P_2): Likewise.
+ (VEX_W_0F3805_P_2): Likewise.
+ (VEX_W_0F3806_P_2): Likewise.
+ (VEX_W_0F3807_P_2): Likewise.
+ (VEX_W_0F3808_P_2): Likewise.
+ (VEX_W_0F3809_P_2): Likewise.
+ (VEX_W_0F380A_P_2): Likewise.
+ (VEX_W_0F380B_P_2): Likewise.
+ (VEX_W_0F3817_P_2): Likewise.
+ (VEX_W_0F381C_P_2): Likewise.
+ (VEX_W_0F381D_P_2): Likewise.
+ (VEX_W_0F381E_P_2): Likewise.
+ (VEX_W_0F3820_P_2): Likewise.
+ (VEX_W_0F3821_P_2): Likewise.
+ (VEX_W_0F3822_P_2): Likewise.
+ (VEX_W_0F3823_P_2): Likewise.
+ (VEX_W_0F3824_P_2): Likewise.
+ (VEX_W_0F3825_P_2): Likewise.
+ (VEX_W_0F3828_P_2): Likewise.
+ (VEX_W_0F3829_P_2): Likewise.
+ (VEX_W_0F382A_P_2_M_0): Likewise.
+ (VEX_W_0F382B_P_2): Likewise.
+ (VEX_W_0F3830_P_2): Likewise.
+ (VEX_W_0F3831_P_2): Likewise.
+ (VEX_W_0F3832_P_2): Likewise.
+ (VEX_W_0F3833_P_2): Likewise.
+ (VEX_W_0F3834_P_2): Likewise.
+ (VEX_W_0F3835_P_2): Likewise.
+ (VEX_W_0F3837_P_2): Likewise.
+ (VEX_W_0F3838_P_2): Likewise.
+ (VEX_W_0F3839_P_2): Likewise.
+ (VEX_W_0F383A_P_2): Likewise.
+ (VEX_W_0F383B_P_2): Likewise.
+ (VEX_W_0F383C_P_2): Likewise.
+ (VEX_W_0F383D_P_2): Likewise.
+ (VEX_W_0F383E_P_2): Likewise.
+ (VEX_W_0F383F_P_2): Likewise.
+ (VEX_W_0F3840_P_2): Likewise.
+ (VEX_W_0F3841_P_2): Likewise.
+ (VEX_W_0F38DB_P_2): Likewise.
+ (VEX_W_0F3A08_P_2): Likewise.
+ (VEX_W_0F3A09_P_2): Likewise.
+ (VEX_W_0F3A0A_P_2): Likewise.
+ (VEX_W_0F3A0B_P_2): Likewise.
+ (VEX_W_0F3A0C_P_2): Likewise.
+ (VEX_W_0F3A0D_P_2): Likewise.
+ (VEX_W_0F3A0E_P_2): Likewise.
+ (VEX_W_0F3A0F_P_2): Likewise.
+ (VEX_W_0F3A21_P_2): Likewise.
+ (VEX_W_0F3A40_P_2): Likewise.
+ (VEX_W_0F3A41_P_2): Likewise.
+ (VEX_W_0F3A42_P_2): Likewise.
+ (VEX_W_0F3A62_P_2): Likewise.
+ (VEX_W_0F3A63_P_2): Likewise.
+ (VEX_W_0F3ADF_P_2): Likewise.
+ (VEX_LEN_0F77_P_0): New.
+ (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
+ PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
+ PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
+ PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
+ PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
+ PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
+ PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
+ PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
+ PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
+ PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
+ PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
+ PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
+ PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
+ PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
+ PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
+ PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
+ PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
+ PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
+ PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
+ PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
+ PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
+ PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
+ PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
+ PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
+ PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
+ PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
+ PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
+ PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
+ PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
+ PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
+ PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
+ PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
+ PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
+ PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
+ PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
+ PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
+ PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
+ PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
+ PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
+ PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
+ PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
+ PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
+ PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
+ PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
+ PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
+ PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
+ PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
+ PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
+ PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
+ (vex_table): Update VEX 0F28 and 0F29 entries.
+ (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
+ VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
+ VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
+ VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
+ VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
+ VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
+ VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
+ VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
+ VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
+ VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
+ VEX_LEN_0F3A0B_P_2 entries.
+ (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
+ VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
+ VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
+ VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
+ VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
+ VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
+ VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
+ VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
+ VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
+ VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
+ VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
+ VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
+ VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
+ VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
+ VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
+ VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
+ VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
+ VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
+ VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
+ VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
+ VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
+ VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
+ VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
+ VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
+ VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
+ VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
+ VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
+ VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
+ VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
+ VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
+ VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
+ VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
+ VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
+ VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
+ VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
+ VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
+ VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
+ VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
+ VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
+ VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
+ VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
+ VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
+ VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
+ VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
+ VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
+ VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
+ VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
+ VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
+ VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
+ VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
+ VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
+ VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
+ VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
+ VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
+ VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
+ VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
+ VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
+ VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
+ VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
+ VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
+ VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
+ VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
+ VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
+ VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
+ VEX_W_0F3ADF_P_2 entries.
+ (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
+ MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
+ MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
+
+2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl (VexWIG): New.
+ Replace VexW=3 with VexWIG.
+
+2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
+ * i386-tbl.h: Regenerated.
+
+2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/23665
+ * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
+ VEX_LEN_0FD6_P_2 entries.
+ * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
+ * i386-tbl.h: Regenerated.
+
+2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/23642
+ * i386-opc.h (VEXWIG): New.
+ * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
+ * i386-tbl.h: Regenerated.
+
+2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/23655
+ * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
+ vcvtsi2sd%LQ and vcvtusi2sd%LQ.
+ * i386-dis.c (EXxEVexR64): New.
+ (evex_rounding_64_mode): Likewise.
+ (OP_Rounding): Handle evex_rounding_64_mode.
+
+2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/23655
+ * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
+ vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
+ * i386-dis.c (Edqa): New.
+ (dqa_mode): Likewise.
+ (intel_operand_size): Handle dqa_mode as m_mode.
+ (OP_E_register): Handle dqa_mode as dq_mode.
+ (OP_E_memory): Set shift for dqa_mode based on address_mode.
+
+2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (OP_E_memory): Reformat.
+
+2018-09-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (crc32): Fold byte and word forms.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
+ pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
+ Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
+ vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
+ * i386-tbl.h: Regenerated.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
+ meaningless.
+ (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
+ xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
+ rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
+ AVX512_4VNNIW insns.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from SHA insns.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from AVX insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
+ (vpbroadcastw, rdpid): Drop NoRex64.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
+ store templates, adding D.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
+ movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
+ movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
+ vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
+ vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
+ Fold load and store templates where possible, adding D. Drop
+ IgnoreSize where it was pointlessly present. Drop redundant
+ *word.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
+ (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
+ (intel_operand_size): Handle v_bndmk_mode.
+ (OP_E_memory): Likewise. Produce (bad) when also riprel.
+
+2018-09-08 John Darrington <john@darrington.wattle.id.au>
+
+ * disassemble.c (ARCH_s12z): Define if ARCH_all.
+
+2018-08-31 Kito Cheng <kito@andestech.com>
+
+ * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
+ compressed floating point instructions.
+
+2018-08-30 Kito Cheng <kito@andestech.com>
+
+ * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
+ riscv_opcode.xlen_requirement.
+ * riscv-opc.c (riscv_opcodes): Update for struct change.
+
+2018-08-29 Martin Aberg <maberg@gaisler.com>
+
+ * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
+ psr (PWRPSR) instruction.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
+ loongson3a as an alias of gs464 for compatibility.
+ * mips-opc.c (mips_opcodes): Change Comments.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
+ option.
+ (print_mips_disassembler_options): Document -M loongson-ext.
+ * mips-opc.c (LEXT2): New macro.
+ (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
+ descriptors.
+ (parse_mips_ase_option): Handle -M loongson-ext option.
+ (print_mips_disassembler_options): Document -M loongson-ext.
+ * mips-opc.c (IL3A): Delete.
+ * mips-opc.c (LEXT): New macro.
+ (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
+ instructions.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
+ descriptors.
+ (parse_mips_ase_option): Handle -M loongson-cam option.
+ (print_mips_disassembler_options): Document -M loongson-cam.
+ * mips-opc.c (LCAM): New macro.
+ (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
+ instructions.
+
+2018-08-21 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (operand_value_powerpc): Init "invalid".
+ (skip_optional_operands): Count optional operands, and update
+ ppc_optional_operand_value call.
+ * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
+ (extract_vlensi): Likewise.
+ (extract_fxm): Return default value for missing optional operand.
+ (extract_ls, extract_raq, extract_tbr): Likewise.
+ (insert_sxl, extract_sxl): New functions.
+ (insert_esync, extract_esync): Remove Power9 handling and simplify.
+ (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
+ flag and extra entry.
+ (powerpc_operands <SXL>): Likewise, and use insert_sxl and
+ extract_sxl.
+
+2018-08-20 Alan Modra <amodra@gmail.com>
+
+ * sh-opc.h (MASK): Simplify.
+
+2018-08-18 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-dis.c (bm_decode): Deal with cases where the mode is
+ BM_RESERVED0 or BM_RESERVED1
+ (bm_rel_decode, bm_n_bytes): Ditto.
+
+2018-08-18 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z.h: Delete.
+
+2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
+ address with the addr32 prefix and without base nor index
+ registers.
+
2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
projects / deliverable / binutils-gdb.git / blobdiff