+2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
+ information.
+ (print_insn_arc): Set insn_type information.
+ * arc-opc.c (C_CC): Add F_CLASS_COND.
+ * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
+ (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
+ (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
+ (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
+ (brne, brne_s, jeq_s, jne_s): Likewise.
+
+2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h (neg): New instruction variant.
+
+2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * arc-dis.c (find_format, find_format, get_auxreg)
+ (print_insn_arc): Changed.
+ * arc-ext.h (INSERT_XOP): Likewise.
+
+2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * tic54x-dis.c (sprint_mmr): Adjust.
+ * tic54x-opc.c: Likewise.
+
+2016-05-19 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
+
+2016-05-19 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c: Formatting.
+ (NSISIGNOPT): Define.
+ (powerpc_opcodes <subis>): Use NSISIGNOPT.
+
+2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
+ replacing references to `micromips_ase' throughout.
+ (_print_insn_mips): Don't use file-level microMIPS annotation to
+ determine the disassembly mode with the symbol table.
+
+2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
+
+2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
+ mips64r6.
+ * mips-opc.c (D34): New macro.
+ (mips_builtin_opcodes): Define bposge32c for DSPr3.
+
+2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
+
+ * i386-dis.c (prefix_table): Add RDPID instruction.
+ * i386-gen.c (cpu_flag_init): Add RDPID flag.
+ (cpu_flags): Add RDPID bitfield.
+ * i386-opc.h (enum): Add RDPID element.
+ (i386_cpu_flags): Add RDPID field.
+ * i386-opc.tbl: Add RDPID instruction.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Regenerate.
+
+2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
+ branch type of a symbol.
+ (print_insn): Likewise.
+
+2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
+ Mainline Security Extensions instructions.
+ (thumb_opcodes): Add entries for narrow ARMv8-M Security
+ Extensions instructions.
+ (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
+ instructions.
+ (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
+ special registers.
+
+2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
+
+2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
+ (arcExtMap_genOpcode): Likewise.
+ * arc-opc.c (arg_32bit_rc): Define new variable.
+ (arg_32bit_u6): Likewise.
+ (arg_32bit_limm): Likewise.
+
+2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-gen.c (VERIFIER): Define.
+ * aarch64-opc.c (VERIFIER): Define.
+ (verify_ldpsw): Use static linkage.
+ * aarch64-opc.h (verify_ldpsw): Remove.
+ * aarch64-tbl.h: Use VERIFIER for verifiers.
+
+2016-04-28 Nick Clifton <nickc@redhat.com>
+
+ PR target/19722
+ * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
+ * aarch64-opc.c (verify_ldpsw): New function.
+ * aarch64-opc.h (verify_ldpsw): New prototype.
+ * aarch64-tbl.h: Add initialiser for verifier field.
+ (LDPSW): Set verifier to verify_ldpsw.
+
+2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/19983
+ PR binutils/19984
+ * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
+ smaller than address size.
+
+2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * alpha-dis.c: Regenerate.
+ * crx-dis.c: Likewise.
+ * disassemble.c: Likewise.
+ * epiphany-opc.c: Likewise.
+ * fr30-opc.c: Likewise.
+ * frv-opc.c: Likewise.
+ * ip2k-opc.c: Likewise.
+ * iq2000-opc.c: Likewise.
+ * lm32-opc.c: Likewise.
+ * lm32-opinst.c: Likewise.
+ * m32c-opc.c: Likewise.
+ * m32r-opc.c: Likewise.
+ * m32r-opinst.c: Likewise.
+ * mep-opc.c: Likewise.
+ * mt-opc.c: Likewise.
+ * or1k-opc.c: Likewise.
+ * or1k-opinst.c: Likewise.
+ * tic80-opc.c: Likewise.
+ * xc16x-opc.c: Likewise.
+ * xstormy16-opc.c: Likewise.
+
+2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
+ fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
+ calcsd, and calcxd instructions.
+ * arc-opc.c (insert_nps_bitop_size): Delete.
+ (extract_nps_bitop_size): Delete.
+ (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
+ (extract_nps_qcmp_m3): Define.
+ (extract_nps_qcmp_m2): Define.
+ (extract_nps_qcmp_m1): Define.
+ (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
+ (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
+ (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
+ NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
+ NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
+ NPS_QCMP_M3.
+
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.