Replace "if (x) free (x)" with "free (x)", opcodes

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4336066d2e26d952e1452f50f86a308e91c8f0fc..3e66569d4e128a34fef55adc2e24b9b1d4ddf2de 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,121 @@
+2020-05-21  Alan Modra  <amodra@gmail.com>
+
+       * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
+       * sparc-dis.c: Likewise.
+       * tic4x-dis.c: Likewise.
+       * xtensa-dis.c: Likewise.
+       * bpf-desc.c: Regenerate.
+       * epiphany-desc.c: Regenerate.
+       * fr30-desc.c: Regenerate.
+       * frv-desc.c: Regenerate.
+       * ip2k-desc.c: Regenerate.
+       * iq2000-desc.c: Regenerate.
+       * lm32-desc.c: Regenerate.
+       * m32c-desc.c: Regenerate.
+       * m32r-desc.c: Regenerate.
+       * mep-asm.c: Regenerate.
+       * mep-desc.c: Regenerate.
+       * mt-desc.c: Regenerate.
+       * or1k-desc.c: Regenerate.
+       * xc16x-desc.c: Regenerate.
+       * xstormy16-desc.c: Regenerate.
+
+2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
+
+       * riscv-opc.c (riscv_ext_version_table): The table used to store
+       all information about the supported spec and the corresponding ISA
+       versions.  Currently, only Zicsr is supported to verify the
+       correctness of Z sub extension settings.  Others will be supported
+       in the future patches.
+       (struct isa_spec_t, isa_specs): List for all supported ISA spec
+       classes and the corresponding strings.
+       (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
+       spec class by giving a ISA spec string.
+       * riscv-opc.c (struct priv_spec_t): New structure.
+       (struct priv_spec_t priv_specs): List for all supported privilege spec
+       classes and the corresponding strings.
+       (riscv_get_priv_spec_class): New function.  Get the corresponding
+       privilege spec class by giving a spec string.
+       (riscv_get_priv_spec_name): New function.  Get the corresponding
+       privilege spec string by giving a CSR version class.
+       * riscv-dis.c: Updated since DECLARE_CSR is changed.
+       * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
+       according to the chosen version.  Build a hash table riscv_csr_hash to
+       store the valid CSR for the chosen pirv verison.  Dump the direct
+       CSR address rather than it's name if it is invalid.
+       (parse_riscv_dis_option_without_args): New function.  Parse the options
+       without arguments.
+       (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
+       parse the options without arguments first, and then handle the options
+       with arguments.  Add the new option -Mpriv-spec, which has argument.
+       * riscv-dis.c (print_riscv_disassembler_options): Add description
+       about the new OBJDUMP option.
+
+2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
+
+       * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
+       WC values on POWER10 sync, dcbf  and wait instructions.
+       (insert_pl, extract_pl): New functions.
+       (L2OPT, LS, WC): Use insert_ls and extract_ls.
+       (LS3): New , 3-bit L for sync.
+       (LS3, L3OPT): New, 3-bit L for sync and dcbf.
+       (SC2, PL): New, 2-bit SC and PL for sync and wait.
+       (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
+       (XOPL3, XWCPL, XSYNCLS): New opcode macros.
+       (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
+       plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
+       <wait>: Enable PL operand on POWER10.
+       <dcbf>: Enable L3OPT operand on POWER10.
+       <sync>: Enable SC2 operand on POWER10.
+
+2020-05-19  Stafford Horne  <shorne@gmail.com>
+
+       PR 25184
+       * or1k-asm.c: Regenerate.
+       * or1k-desc.c: Regenerate.
+       * or1k-desc.h: Regenerate.
+       * or1k-dis.c: Regenerate.
+       * or1k-ibld.c: Regenerate.
+       * or1k-opc.c: Regenerate.
+       * or1k-opc.h: Regenerate.
+       * or1k-opinst.c: Regenerate.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
+       xsmaxcqp, xsmincqp.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
+       stxvrbx, stxvrhx, stxvrwx, stxvrdx.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
+       vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
+
+2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
+
+       * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
+       mnemonics.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
+       (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
+       vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
+       (prefix_opcodes): Add xxeval.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
+       xxgenpcvwm, xxgenpcvdm.
+
 2020-05-11  Alan Modra  <amodra@gmail.com>
 
        * ppc-opc.c (MP, VXVAM_MASK): Define.