+2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25641
+ * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
+
+2020-03-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (X86_64_0D): Rename to ...
+ (X86_64_0E): ... this.
+
+2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
+ * Makefile.in: Regenerated.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
+ 3-operand pseudos.
+ * i386-tbl.h: Re-generate.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
+ vprot*, vpsha*, and vpshl*.
+ * i386-tbl.h: Re-generate.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
+ vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
+ * i386-tbl.h: Re-generate.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (set_bitfield): Ignore zero-length field names.
+ * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
+ cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
+ * i386-tbl.h: Re-generate.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (struct template_arg, struct template_instance,
+ struct template_param, struct template, templates,
+ parse_template, expand_templates): New.
+ (process_i386_opcodes): Various local variables moved to
+ expand_templates. Call parse_template and expand_templates.
+ * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
+ vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
+ register and memory source templates. Replace VexW= by VexW*
+ where applicable.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
+ VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
+ (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
+ pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
+ VexW0 on SSE2AVX variants.
+ (vmovq): Drop NoRex64 from XMM/XMM variants.
+ (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
+ vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
+ applicable use VexW0.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Remove Rex64 field.
+ * i386-opc.h (Rex64): Delete.
+ (struct i386_opcode_modifier): Remove rex64 field.
+ * i386-opc.tbl (crc32): Drop Rex64.
+ Replace Rex64 with Size64 everywhere else.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_E_memory): Exclude recording of used address
+ prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
+ addressed memory operands for MPX insns.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
+ invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
+ adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
+ (ptwrite): Split into non-64-bit and 64-bit forms.
+ * i386-tbl.h: Re-generate.
+
2020-03-06 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand