+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
+ (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
+ pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
+ VexW0 on SSE2AVX variants.
+ (vmovq): Drop NoRex64 from XMM/XMM variants.
+ (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
+ vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
+ applicable use VexW0.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Remove Rex64 field.
+ * i386-opc.h (Rex64): Delete.
+ (struct i386_opcode_modifier): Remove rex64 field.
+ * i386-opc.tbl (crc32): Drop Rex64.
+ Replace Rex64 with Size64 everywhere else.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_E_memory): Exclude recording of used address
+ prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
+ addressed memory operands for MPX insns.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
+ invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
+ adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
+ (ptwrite): Split into non-64-bit and 64-bit forms.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
+ template.
+ * i386-tbl.h: Re-generate.
+
+2020-03-04 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
+ (prefix_table): Move vmmcall here. Add vmgexit.
+ (rm_table): Replace vmmcall entry by prefix_table[] escape.
+ * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
+ (cpu_flags): Add CpuSEV_ES entry.
+ * i386-opc.h (CpuSEV_ES): New.
+ (union i386_cpu_flags): Add cpusev_es field.
+ * i386-opc.tbl (vmgexit): New.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
+ with MnemonicSize.
+ * i386-opc.h (IGNORESIZE): New.
+ (DEFAULTSIZE): Likewise.
+ (IgnoreSize): Removed.
+ (DefaultSize): Likewise.
+ (MnemonicSize): New.
+ (i386_opcode_modifier): Replace ignoresize/defaultsize with
+ mnemonicsize.
+ * i386-opc.tbl (IgnoreSize): New.
+ (DefaultSize): Likewise.
+ * i386-tbl.h: Regenerated.
+
+2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25627
+ * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
+ instructions.
+
+2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25622
+ * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
+ vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
+ * i386-tbl.h: Regenerated.
+
+2020-02-26 Alan Modra <amodra@gmail.com>
+
+ * aarch64-asm.c: Indent labels correctly.
+ * aarch64-dis.c: Likewise.
+ * aarch64-gen.c: Likewise.
+ * aarch64-opc.c: Likewise.
+ * alpha-dis.c: Likewise.
+ * i386-dis.c: Likewise.
+ * nds32-asm.c: Likewise.
+ * nfp-dis.c: Likewise.
+ * visium-dis.c: Likewise.
+
+2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
+
+ * arc-regs.h (int_vector_base): Make it available for all ARC
+ CPUs.
+
+2020-02-20 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
+ changed.
+
+2020-02-19 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
+ c.mv/c.li if rs1 is zero.
+
+2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Replace CpuABM with
+ CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
+ CPU_POPCNT_FLAGS.
+ (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
+ * i386-opc.h (CpuABM): Removed.
+ (CpuPOPCNT): New.
+ (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
+ * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
+ popcnt. Remove CpuABM from lzcnt.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2020-02-17 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
+ Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
+ VexW1 instead of open-coding them.
+ * i386-tbl.h: Re-generate.
+
+2020-02-17 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (AddrPrefixOpReg): Define.
+ (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
+ umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
+ templates. Drop NoRex64.
+ * i386-tbl.h: Re-generate.
+
+2020-02-17 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/6518
+ * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
+ vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
+ into Intel syntax instance (with Unpsecified) and AT&T one
+ (without).
+ (vcvtneps2bf16): Likewise, along with folding the two so far
+ separate ones.
+ * i386-tbl.h: Re-generate.
+
+2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
+ CPU_ANY_SSE4A_FLAGS.
+
+2020-02-17 Alan Modra <amodra@gmail.com>
+
+ * i386-gen.c (cpu_flag_init): Correct last change.
+
+2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
+ CPU_ANY_SSE4_FLAGS.
+
+2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl (movsx): Remove Intel syntax comments.
+ (movzx): Likewise.
+
+2020-02-14 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/25438
+ * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
+ destination for Cpu64-only variant.
+ (movzx): Fold patterns.
+ * i386-tbl.h: Re-generate.
+
+2020-02-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
+ CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
+ CPU_ANY_SSE4_FLAGS entry.
+ * i386-init.h: Re-generate.
+
2020-02-12 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
projects / deliverable / binutils-gdb.git / blobdiff