+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
+ OPERAND_TYPE_REGBND entry.
+ (operand_classes): Add RegMask and RegBND entries.
+ (operand_types): Drop RegMask and RegBND entry.
+ * i386-opc.h (enum operand_class): Add RegMask and RegBND.
+ (RegMask, RegBND): Delete.
+ (union i386_operand_type): Remove regmask and regbnd fields.
+ * i386-opc.tbl (RegMask, RegBND): Define.
+ * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
+ Class=RegBND.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
+ OPERAND_TYPE_REGZMM entries.
+ (operand_classes): Add RegMMX and RegSIMD entries.
+ (operand_types): Drop RegMMX and RegSIMD entries.
+ * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
+ (RegMMX, RegSIMD): Delete.
+ (union i386_operand_type): Remove regmmx and regsimd fields.
+ * i386-opc.tbl (RegMMX): Define.
+ (RegXMM, RegYMM, RegZMM): Add Class=.
+ * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
+ Class=RegSIMD.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
+ entries.
+ (operand_classes): Add RegCR, RegDR, and RegTR entries.
+ (operand_types): Drop Control, Debug, and Test entries.
+ * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
+ (Control, Debug, Test): Delete.
+ (union i386_operand_type): Remove control, debug, and test
+ fields.
+ * i386-opc.tbl (Control, Debug, Test): Define.
+ * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
+ Class=RegDR, and Test by Class=RegTR.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_SREG entry.
+ (operand_classes): Add SReg entry.
+ (operand_types): Drop SReg entry.
+ * i386-opc.h (enum operand_class): Add SReg.
+ (SReg): Delete.
+ (union i386_operand_type): Remove sreg field.
+ * i386-opc.tbl (SReg): Define.
+ * i386-reg.tbl: Replace SReg by Class=SReg.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class=. New
+ OPERAND_TYPE_ANYIMM entry.
+ (operand_classes): New.
+ (operand_types): Drop Reg entry.
+ (output_operand_type): New parameter "class". Process it.
+ (process_i386_operand_type): New local variable "class".
+ (main): Adjust static assertions.
+ * i386-opc.h (CLASS_WIDTH): Define.
+ (enum operand_class): New.
+ (Reg): Replace by Class. Adjust comment.
+ (union i386_operand_type): Replace reg by class.
+ * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
+ Class=.
+ * i386-reg.tbl: Replace Reg by Class=Reg.
+ * i386-init.h: Re-generate.
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
+ (aarch64_opcode_table): Add data gathering hint mnemonic.
+ * opcodes/aarch64-dis-2.c: Account for new instruction.
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
+
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
+ aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
+ aarch64_feature_f64mm): New feature sets.
+ (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
+ F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
+ instructions.
+ (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
+ macros.
+ (QL_MMLA64, OP_SVE_SBB): New qualifiers.
+ (OP_SVE_QQQ): New qualifier.
+ (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
+ F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
+ the movprfx constraint.
+ (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
+ (aarch64_opcode_table): Define new instructions smmla,
+ ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
+ uzip{1/2}, trn{1/2}.
+ * aarch64-opc.c (operand_general_constraint_met_p): Handle
+ AARCH64_OPND_SVE_ADDR_RI_S4x32.
+ (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
+ * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
+ Account for new instructions.
+ * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
+ S4x32 operand.
+ * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
+ Armv8.6-A.
+ (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
+ (neon_opcodes): Add bfloat SIMD instructions.
+ (print_insn_coprocessor): Add new control character %b to print
+ condition code without checking cp_num.
+ (print_insn_neon): Account for BFloat16 instructions that have no
+ special top-byte handling.
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * arm-dis.c (print_insn_coprocessor,
+ print_insn_generic_coprocessor): Create wrapper functions around
+ the implementation of the print_insn_coprocessor control codes.
+ (print_insn_coprocessor_1): Original print_insn_coprocessor
+ function that now takes which array to look at as an argument.
+ (print_insn_arm): Use both print_insn_coprocessor and
+ print_insn_generic_coprocessor.
+ (print_insn_thumb32): As above.
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
+ in reglane special case.
+ * aarch64-dis-2.c (aarch64_opcode_lookup_1,
+ aarch64_find_next_opcode): Account for new instructions.
+ * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
+ in reglane special case.
+ * aarch64-opc.c (struct operand_qualifier_data): Add data for
+ new AARCH64_OPND_QLF_S_2H qualifier.
+ * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
+ QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
+ (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
+ sets.
+ (BFLOAT_SVE, BFLOAT): New feature set macros.
+ (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
+ instructions.
+ (aarch64_opcode_table): Define new instructions bfdot,
+ bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
+ bfcvtn2, bfcvt.
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-tbl.h (ARMV8_6): New macro.
+
+2019-11-07 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (prefix_table): Add mcommit.
+ (rm_table): Add rdpru.
+ * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
+ CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
+ (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
+ * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
+ (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
+ * i386-opc.tbl (mcommit, rdpru): New.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-07 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_Mwait): Drop local variable "names", use
+ "names32" instead.
+ (OP_Monitor): Drop local variable "op1_names", re-purpose
+ "names" for it instead, and replace former "names" uses by
+ "names32" ones.
+
2019-11-07 Jan Beulich <jbeulich@suse.com>
PR/gas 25167
projects / deliverable / binutils-gdb.git / blobdiff