+2020-03-22 Alan Modra <amodra@gmail.com>
+
+ * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
+ successflly read from section.
+
+2020-03-22 Alan Modra <amodra@gmail.com>
+
+ * arc-dis.c (find_format): Use ISO C string concatenation rather
+ than line continuation within a string. Don't access needs_limm
+ before testing opcode != NULL.
+
+2020-03-22 Alan Modra <amodra@gmail.com>
+
+ * ns32k-dis.c (print_insn_arg): Update comment.
+ (print_insn_ns32k): Reduce size of index_offset array, and
+ initialize, passing -1 to print_insn_arg for args that are not
+ an index. Don't exit arg loop early. Abort on bad arg number.
+
+2020-03-22 Alan Modra <amodra@gmail.com>
+
+ * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
+ * s12z-opc.c: Formatting.
+ (operands_f): Return an int.
+ (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
+ (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
+ (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
+ (exg_sex_discrim): Likewise.
+ (create_immediate_operand, create_bitfield_operand),
+ (create_register_operand_with_size, create_register_all_operand),
+ (create_register_all16_operand, create_simple_memory_operand),
+ (create_memory_operand, create_memory_auto_operand): Don't
+ segfault on malloc failure.
+ (z_ext24_decode): Return an int status, negative on fail, zero
+ on success.
+ (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
+ (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
+ (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
+ (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
+ (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
+ (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
+ (loop_primitive_decode, shift_decode, psh_pul_decode),
+ (bit_field_decode): Similarly.
+ (z_decode_signed_value, decode_signed_value): Similarly. Add arg
+ to return value, update callers.
+ (x_opr_decode_with_size): Check all reads, returning NULL on fail.
+ Don't segfault on NULL operand.
+ (decode_operation): Return OP_INVALID on first fail.
+ (decode_s12z): Check all reads, returning -1 on fail.
+
+2020-03-20 Alan Modra <amodra@gmail.com>
+
+ * metag-dis.c (print_insn_metag): Don't ignore status from
+ read_memory_func.
+
+2020-03-20 Alan Modra <amodra@gmail.com>
+
+ * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
+ Initialize parts of buffer not written when handling a possible
+ 2-byte insn at end of section. Don't attempt decoding of such
+ an insn by the 4-byte machinery.
+
+2020-03-20 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
+ partially filled buffer. Prevent lookup of 4-byte insns when
+ only VLE 2-byte insns are possible due to section size. Print
+ ".word" rather than ".long" for 2-byte leftovers.
+
+2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25641
+ * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
+
+2020-03-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (X86_64_0D): Rename to ...
+ (X86_64_0E): ... this.
+
+2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
+ * Makefile.in: Regenerated.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
+ 3-operand pseudos.
+ * i386-tbl.h: Re-generate.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
+ vprot*, vpsha*, and vpshl*.
+ * i386-tbl.h: Re-generate.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
+ vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
+ * i386-tbl.h: Re-generate.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (set_bitfield): Ignore zero-length field names.
+ * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
+ cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
+ * i386-tbl.h: Re-generate.
+
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (struct template_arg, struct template_instance,
+ struct template_param, struct template, templates,
+ parse_template, expand_templates): New.
+ (process_i386_opcodes): Various local variables moved to
+ expand_templates. Call parse_template and expand_templates.
+ * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
+ vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
+ register and memory source templates. Replace VexW= by VexW*
+ where applicable.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
+ VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
+ (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
+ pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
+ VexW0 on SSE2AVX variants.
+ (vmovq): Drop NoRex64 from XMM/XMM variants.
+ (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
+ vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
+ applicable use VexW0.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Remove Rex64 field.
+ * i386-opc.h (Rex64): Delete.
+ (struct i386_opcode_modifier): Remove rex64 field.
+ * i386-opc.tbl (crc32): Drop Rex64.
+ Replace Rex64 with Size64 everywhere else.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_E_memory): Exclude recording of used address
+ prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
+ addressed memory operands for MPX insns.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
+ invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
+ adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
+ (ptwrite): Split into non-64-bit and 64-bit forms.
+ * i386-tbl.h: Re-generate.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
+ template.
+ * i386-tbl.h: Re-generate.
+
+2020-03-04 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
+ (prefix_table): Move vmmcall here. Add vmgexit.
+ (rm_table): Replace vmmcall entry by prefix_table[] escape.
+ * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
+ (cpu_flags): Add CpuSEV_ES entry.
+ * i386-opc.h (CpuSEV_ES): New.
+ (union i386_cpu_flags): Add cpusev_es field.
+ * i386-opc.tbl (vmgexit): New.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
+ with MnemonicSize.
+ * i386-opc.h (IGNORESIZE): New.
+ (DEFAULTSIZE): Likewise.
+ (IgnoreSize): Removed.
+ (DefaultSize): Likewise.
+ (MnemonicSize): New.
+ (i386_opcode_modifier): Replace ignoresize/defaultsize with
+ mnemonicsize.
+ * i386-opc.tbl (IgnoreSize): New.
+ (DefaultSize): Likewise.
+ * i386-tbl.h: Regenerated.
+
+2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25627
+ * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
+ instructions.
+
+2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25622
+ * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
+ vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
+ * i386-tbl.h: Regenerated.
+
+2020-02-26 Alan Modra <amodra@gmail.com>
+
+ * aarch64-asm.c: Indent labels correctly.
+ * aarch64-dis.c: Likewise.
+ * aarch64-gen.c: Likewise.
+ * aarch64-opc.c: Likewise.
+ * alpha-dis.c: Likewise.
+ * i386-dis.c: Likewise.
+ * nds32-asm.c: Likewise.
+ * nfp-dis.c: Likewise.
+ * visium-dis.c: Likewise.
+
+2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
+
+ * arc-regs.h (int_vector_base): Make it available for all ARC
+ CPUs.
+
+2020-02-20 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
+ changed.
+
+2020-02-19 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
+ c.mv/c.li if rs1 is zero.
+
+2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Replace CpuABM with
+ CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
+ CPU_POPCNT_FLAGS.
+ (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
+ * i386-opc.h (CpuABM): Removed.
+ (CpuPOPCNT): New.
+ (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
+ * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
+ popcnt. Remove CpuABM from lzcnt.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2020-02-17 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
+ Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
+ VexW1 instead of open-coding them.
+ * i386-tbl.h: Re-generate.
+
+2020-02-17 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (AddrPrefixOpReg): Define.
+ (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
+ umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
+ templates. Drop NoRex64.
+ * i386-tbl.h: Re-generate.
+
+2020-02-17 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/6518
+ * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
+ vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
+ into Intel syntax instance (with Unpsecified) and AT&T one
+ (without).
+ (vcvtneps2bf16): Likewise, along with folding the two so far
+ separate ones.
+ * i386-tbl.h: Re-generate.
+
+2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
+ CPU_ANY_SSE4A_FLAGS.
+
+2020-02-17 Alan Modra <amodra@gmail.com>
+
+ * i386-gen.c (cpu_flag_init): Correct last change.
+
+2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
+ CPU_ANY_SSE4_FLAGS.
+
+2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl (movsx): Remove Intel syntax comments.
+ (movzx): Likewise.
+
+2020-02-14 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/25438
+ * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
+ destination for Cpu64-only variant.
+ (movzx): Fold patterns.
+ * i386-tbl.h: Re-generate.
+
+2020-02-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
+ CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
+ CPU_ANY_SSE4_FLAGS entry.
+ * i386-init.h: Re-generate.
+
+2020-02-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
+ with Unspecified, making the present one AT&T syntax only.
+ * i386-tbl.h: Re-generate.
+
+2020-02-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
+ * i386-tbl.h: Re-generate.
+
+2020-02-12 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/24546
+ * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
+ * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
+ Amd64 and Intel64 templates.
+ (call, jmp): Likewise for far indirect variants. Dro
+ Unspecified.
+ * i386-tbl.h: Re-generate.
+
+2020-02-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
+ * i386-opc.h (ShortForm): Delete.
+ (struct i386_opcode_modifier): Remove shortform field.
+ * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
+ fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
+ fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
+ ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
+ Drop ShortForm.
+ * i386-tbl.h: Re-generate.
+
+2020-02-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
+ fucompi): Drop ShortForm from operand-less templates.
+ * i386-tbl.h: Re-generate.
+
+2020-02-11 Alan Modra <amodra@gmail.com>
+
+ * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
+ * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
+ * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
+ * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
+ * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
+
+2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * arm-dis.c (print_insn_cde): Define 'V' parse character.
+ (cde_opcodes): Add VCX* instructions.
+
+2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
+ Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * arm-dis.c (struct cdeopcode32): New.
+ (CDE_OPCODE): New macro.
+ (cde_opcodes): New disassembly table.
+ (regnames): New option to table.
+ (cde_coprocs): New global variable.
+ (print_insn_cde): New
+ (print_insn_thumb32): Use print_insn_cde.
+ (parse_arm_disassembler_options): Parse coprocN args.
+
+2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25516
+ * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
+ with ISA64.
+ * i386-opc.h (AMD64): Removed.
+ (Intel64): Likewose.
+ (AMD64): New.
+ (INTEL64): Likewise.
+ (INTEL64ONLY): Likewise.
+ (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
+ * i386-opc.tbl (Amd64): New.
+ (Intel64): Likewise.
+ (Intel64Only): Likewise.
+ Replace AMD64 with Amd64. Update sysenter/sysenter with
+ Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
+ * i386-tbl.h: Regenerated.
+
+2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25469
+ * z80-dis.c: Add support for GBZ80 opcodes.
+
+2020-02-04 Alan Modra <amodra@gmail.com>
+
+ * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
+
+2020-02-03 Alan Modra <amodra@gmail.com>
+
+ * m32c-ibld.c: Regenerate.
+
+2020-02-01 Alan Modra <amodra@gmail.com>
+
+ * frv-ibld.c: Regenerate.
+
+2020-01-31 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
+ (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
+ (OP_E_memory): Replace xmm_mdq_mode case label by
+ vex_scalar_w_dq_mode one.
+ * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
+
+2020-01-31 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
+ (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
+ vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
+ (intel_operand_size): Drop vex_w_dq_mode case label.
+
+2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
+ Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
+
+2020-01-30 Alan Modra <amodra@gmail.com>
+
+ * m32c-ibld.c: Regenerate.
+
+2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * bpf-opc.c: Regenerate.
+
+2020-01-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
+ (dis386): Use them to replace C2/C3 table entries.
+ (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
+ * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
+ ones. Use Size64 instead of DefaultSize on Intel64 ones.
+ * i386-tbl.h: Re-generate.
+
+2020-01-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
+ forms.
+ (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
+ DefaultSize.
+ * i386-tbl.h: Re-generate.
+
+2020-01-30 Alan Modra <amodra@gmail.com>
+
+ * tic4x-dis.c (tic4x_dp): Make unsigned.
+
+2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
+ Jan Beulich <jbeulich@suse.com>
+
+ PR binutils/25445
+ * i386-dis.c (MOVSXD_Fixup): New function.
+ (movsxd_mode): New enum.
+ (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
+ (intel_operand_size): Handle movsxd_mode.
+ (OP_E_register): Likewise.
+ (OP_G): Likewise.
+ * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
+ register on movsxd. Add movsxd with 16-bit destination register
+ for AMD64 and Intel64 ISAs.
+ * i386-tbl.h: Regenerated.
+
+2020-01-27 Tamar Christina <tamar.christina@arm.com>
+
+ PR 25403
+ * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
+ * aarch64-asm-2.c: Regenerate
+ * aarch64-dis-2.c: Likewise.
+ * aarch64-opc-2.c: Likewise.
+
+2020-01-21 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (sysret): Drop DefaultSize.
+ * i386-tbl.h: Re-generate.
+
+2020-01-21 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
+ Dword.
+ (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
+ * i386-tbl.h: Re-generate.
+
+2020-01-20 Nick Clifton <nickc@redhat.com>
+
+ * po/de.po: Updated German translation.
+ * po/pt_BR.po: Updated Brazilian Portuguese translation.
+ * po/uk.po: Updated Ukranian translation.
+
+2020-01-20 Alan Modra <amodra@gmail.com>
+
+ * hppa-dis.c (fput_const): Remove useless cast.
+
+2020-01-20 Alan Modra <amodra@gmail.com>
+
+ * arm-dis.c (print_insn_arm): Wrap 'T' value.
+
+2020-01-18 Nick Clifton <nickc@redhat.com>
+
+ * configure: Regenerate.
+ * po/opcodes.pot: Regenerate.
+
+2020-01-18 Nick Clifton <nickc@redhat.com>
+
+ Binutils 2.34 branch created.
+
+2020-01-17 Christian Biesinger <cbiesinger@google.com>
+
+ * opintl.h: Fix spelling error (seperate).
+
+2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add {vex} pseudo prefix.
+ * i386-tbl.h: Regenerated.
+
+2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ PR 25376
+ * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
+ (neon_opcodes): Likewise.
+ (select_arm_features): Make sure we enable MVE bits when selecting
+ armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
+ any architecture.
+
+2020-01-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop stale comment from XOP section.
+
+2020-01-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
+ (extractps): Add VexWIG to SSE2AVX forms.
+ * i386-tbl.h: Re-generate.
+
+2020-01-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
+ Size64 from and use VexW1 on SSE2AVX forms.
+ (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
+ VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
+ * i386-tbl.h: Re-generate.
+
+2020-01-15 Alan Modra <amodra@gmail.com>
+
+ * tic4x-dis.c (tic4x_version): Make unsigned long.
+ (optab, optab_special, registernames): New file scope vars.
+ (tic4x_print_register): Set up registernames rather than
+ malloc'd registertable.
+ (tic4x_disassemble): Delete optable and optable_special. Use
+ optab and optab_special instead. Throw away old optab,
+ optab_special and registernames when info->mach changes.
+
+2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25377
+ * z80-dis.c (suffix): Use .db instruction to generate double
+ prefix.
+
+2020-01-14 Alan Modra <amodra@gmail.com>
+
+ * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
+ values to unsigned before shifting.
+
+2020-01-13 Thomas Troeger <tstroege@gmx.de>
+
+ * arm-dis.c (print_insn_arm): Fill in insn info fields for control
+ flow instructions.
+ (print_insn_thumb16, print_insn_thumb32): Likewise.
+ (print_insn): Initialize the insn info.
+ * i386-dis.c (print_insn): Initialize the insn info fields, and
+ detect jumps.
+
+2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
+
+ * arc-opc.c (C_NE): Make it required.
+
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
projects / deliverable / binutils-gdb.git / blobdiff