+2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Mask unused extended
+ instruction bits out.
+
+2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
+ * arc-opc.c (arc_flag_operands): Add new flags.
+ (arc_flag_classes): Add new classes.
+
+2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
+
+2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
+ encode1, rflt, crc16, and crc32 instructions.
+ * arc-opc.c (arc_flag_operands): Add F_NPS_R.
+ (arc_flag_classes): Add C_NPS_R.
+ (insert_nps_bitop_size_2b): New function.
+ (extract_nps_bitop_size_2b): Likewise.
+ (insert_nps_bitop_uimm8): Likewise.
+ (extract_nps_bitop_uimm8): Likewise.
+ (arc_operands): Add new operand entries.
+
+2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-regs.h: Add a new subclass field. Add double assist
+ accumulator register values.
+ * arc-tbl.h: Use DPA subclass to mark the double assist
+ instructions. Use DPX/SPX subclas to mark the FPX instructions.
+ * arc-opc.c (RSP): Define instead of SP.
+ (arc_aux_regs): Add the subclass field.
+
+2016-04-05 Jiong Wang <jiong.wang@arm.com>
+
+ * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
+
+2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
+ NPS_R_SRC1.
+
+2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
+ issues. No functional changes.
+
+2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
+ (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
+ (RTT): Remove duplicate.
+ (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
+ (PCT_CONFIG*): Remove.
+ (D1L, D1H, D2H, D2L): Define.
+
+2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
+
+2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h (invld07): Remove.
+ * arc-ext-tbl.h: New file.
+ * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
+ * arc-opc.c (arc_opcodes): Add ext-tbl include.
+
+2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
+
+ Fix -Wstack-usage warnings.
+ * aarch64-dis.c (print_operands): Substitute size.
+ * aarch64-opc.c (print_register_offset_address): Substitute tblen.
+
+2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
+ to get a proper diagnostic when an invalid ASR register is used.
+
+2016-03-22 Nick Clifton <nickc@redhat.com>
+
+ * configure: Regenerate.
+
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: New file.
+ * arc-opc.c: Add top level comment.
+ (insert_nps_3bit_dst): New function.
+ (extract_nps_3bit_dst): New function.
+ (insert_nps_3bit_src2): New function.
+ (extract_nps_3bit_src2): New function.
+ (insert_nps_bitop_size): New function.
+ (extract_nps_bitop_size): New function.
+ (arc_flag_operands): Add nps400 entries.
+ (arc_flag_classes): Add nps400 entries.
+ (arc_operands): Add nps400 entries.
+ (arc_opcodes): Add nps400 include.
+
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (arc_flag_classes): Convert all flag classes to use
+ the new class enum values.
+
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-dis.c (print_insn_arc): Handle nps400.
+
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (BASE): Delete.
+
+2016-03-18 Nick Clifton <nickc@redhat.com>
+
+ PR target/19721
+ * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
+ of MOV insn that aliases an ORR insn.
+
+2016-03-16 Jiong Wang <jiong.wang@arm.com>
+
+ * arm-dis.c (neon_opcodes): Support new FP16 instructions.
+
+2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * mcore-opc.h: Add const qualifiers.
+ * microblaze-opc.h (struct op_code_struct): Likewise.
+ * sh-opc.h: Likewise.
+ * tic4x-dis.c (tic4x_print_indirect): Likewise.
+ (tic4x_print_op): Likewise.
+
+2016-03-02 Alan Modra <amodra@gmail.com>
+
+ * or1k-desc.h: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * rl78-decode.c: Regenerate.
+
+2016-03-01 Nick Clifton <nickc@redhat.com>
+
+ PR target/19747
+ * rl78-dis.c (print_insn_rl78_common): Fix typo.
+
+2016-02-24 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
+ (print_insn_coprocessor): Support fp16 instructions.
+
+2016-02-24 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
+ vminnm, vrint(mpna).
+
+2016-02-24 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (print_insn_coprocessor): Check co-processor number for
+ cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
+
+2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (print_insn): Parenthesize expression to prevent
+ truncated addresses.
+ (OP_J): Likewise.
+
+2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
+ Janek van Oirschot <jvanoirs@synopsys.com>
+
+ * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
+ variable.
+
+2016-02-04 Nick Clifton <nickc@redhat.com>
+
+ PR target/19561
+ * msp430-dis.c (print_insn_msp430): Add a special case for
+ decoding an RRC instruction with the ZC bit set in the extension
+ word.
+
+2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * cgen-ibld.in (insert_normal): Rework calculation of shift.
+ * epiphany-ibld.c: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * frv-ibld.c: Regenerate.
+ * ip2k-ibld.c: Regenerate.
+ * iq2000-ibld.c: Regenerate.
+ * lm32-ibld.c: Regenerate.
+ * m32c-ibld.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * mep-ibld.c: Regenerate.
+ * mt-ibld.c: Regenerate.
+ * or1k-ibld.c: Regenerate.
+ * xc16x-ibld.c: Regenerate.
+ * xstormy16-ibld.c: Regenerate.
+
+2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * epiphany-dis.c: Regenerated from latest cpu files.
+
+2016-02-01 Michael McConville <mmcco@mykolab.com>
+
+ * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
+ test bit.
+
+2016-01-25 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (mapping_symbol_for_insn): New function.
+ (find_ifthen_state): Call mapping_symbol_for_insn().
+
+2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Check validity
+ of MSR UAO immediate operand.
+
+2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
+ instruction support.
+
+2016-01-17 Alan Modra <amodra@gmail.com>
+
+ * configure: Regenerate.
+
+2016-01-14 Nick Clifton <nickc@redhat.com>
+
+ * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
+ instructions that can support stack pointer operations.
+ * rl78-decode.c: Regenerate.
+ * rl78-dis.c: Fix display of stack pointer in MOVW based
+ instructions.
+
+2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
+ testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
+ erxtatus_el1 and erxaddr_el1.
+
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
* arm-dis.c (arm_opcodes): Add "esb".
projects / deliverable / binutils-gdb.git / blobdiff