-2014-12-24 Anthony Green <green@moxielogic.com>
+2015-12-12 Alan Modra <amodra@gmail.com>
+
+ PR 19359
+ * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
+ (powerpc_opcodes): Remove single-operand mfcr.
+
+2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_hint): New.
+ * aarch64-asm.h (aarch64_ins_hint): Declare.
+ * aarch64-dis.c (aarch64_ext_hint): New.
+ * aarch64-dis.h (aarch64_ext_hint): Declare.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-opc.c (aarch64_hint_options): New.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
+
+2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
+
+2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
+ pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
+ pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
+ pmscr_el2.
+ (aarch64_sys_reg_supported_p): Add architecture feature tests for
+ the new registers.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
+ (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
+ feature test for "s1e1rp" and "s1e1wp".
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
+ (aarch64_sys_ins_reg_supported_p): New.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
+ with aarch64_sys_ins_reg_has_xt.
+ (aarch64_ext_sysins_op): Likewise.
+ * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
+ (F_HASXT): New.
+ (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
+ (aarch64_sys_regs_dc): Likewise.
+ (aarch64_sys_regs_at): Likewise.
+ (aarch64_sys_regs_tlbi): Likewise.
+ (aarch64_sys_ins_reg_has_xt): New.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add "uao".
+ (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
+ (aarch64_pstatefields): Add "uao".
+ (aarch64_pstatefield_supported_p): Add checks for "uao".
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
+ "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
+ "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
+ (aarch64_sys_reg_supported_p): Add architecture feature tests for
+ new registers.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-tbl.h (aarch64_feature_ras): New.
+ (RAS): New.
+ (aarch64_opcode_table): Add "esb".
+
+2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (MOD_0F01_REG_5): New.
+ (RM_0F01_REG_5): Likewise.
+ (reg_table): Use MOD_0F01_REG_5.
+ (mod_table): Add MOD_0F01_REG_5.
+ (rm_table): Add RM_0F01_REG_5.
+ * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
+ (cpu_flags): Add CpuOSPKE.
+ * i386-opc.h (CpuOSPKE): New.
+ (i386_cpu_flags): Add cpuospke.
+ * i386-opc.tbl: Add rdpkru and wrpkru instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
- * moxie-opc: Define mul.x and umul.x instructions. Remove
- trailing .l from add, sub, mul, div and udiv instructions.
+2015-12-07 DJ Delorie <dj@redhat.com>
-2014-12-16 Matthew Fortune <matthew.fortune@imgtec.com>
+ * rl78-decode.opc: Enable MULU for all ISAs.
+ * rl78-decode.c: Regenerate.
- * mips-opc.c (mips_builtin_opcodes): Add JALRC alias for
- JIALC. Remove the operand from NAL.
+2015-12-07 Alan Modra <amodra@gmail.com>
+
+ * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
+ major opcode/xop.
-2014-12-12 Anthony Green <green@moxielogic.com>
+2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
- * moxie-opc.c: Define zex instructions.
+ * arc-dis.c (special_flag_p): Match full mnemonic.
+ * arc-opc.c (print_insn_arc): Check section size to read
+ appropriate number of bytes. Fix printing.
+ * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
+ arguments.
-2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
+2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
- * configure.ac: Add Visium support.
- * configure: Regenerate.
- * Makefile.am (TARGET_LIBOPCODES_CFILES): Add visium-dis.c and
- visium-opc.c.
- * Makefile.in: Regenerate.
- * disassemble.c (ARCH_visium): Define if ARCH_all.
- (disassembler): Deal with bfd_arch_visium if ARCH_visium.
- * visium-dis.c: New file.
- * visium-opc.c: Likewise.
- * po/POTFILES.in: Regenerate.
+ * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
+ <ldah>: ... to this.
-2014-11-30 Alan Modra <amodra@gmail.com>
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
- * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
- power4 and later.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
+ (QL_INT2FP_H, QL_FP2INT_H): New.
+ (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
+ (QL_DST_H): New.
+ (QL_FCCMP_H): New.
+ (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
+ fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
+ fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
+ fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
+ frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
+ fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
+ fcsel.
-2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
- * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
- from descriptors.
+ * aarch64-opc.c (half_conv_t): New.
+ (expand_fp_imm): Replace is_dp flag with the parameter size to
+ specify the number of bytes for the required expansion. Treat
+ a 16-bit expansion like a 32-bit expansion. Add check for an
+ unsupported size request. Update comment.
+ (aarch64_print_operand): Update to support 16-bit floating point
+ values. Update for changes to expand_fp_imm.
-2014-11-28 Alan Modra <amodra@gmail.com>
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
- * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
- (TB): Delete.
- (insert_tbr, extract_tbr): Validate tbr number.
+ * aarch64-tbl.h (aarch64_feature_fp_f16): New.
+ (FP_F16): New.
-2014-11-24 H.J. Lu <hongjiu.lu@intel.com>
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
- * configure: Regenerated.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
+ "rev64".
-2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
-
- * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
- vpmultishiftqb.
- * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
- (cpu_flags): Add CpuAVX512VBMI.
- * i386-opc.h (enum): Add CpuAVX512VBMI.
- (i386_cpu_flags): Add cpuavx512vbmi.
- * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
- vpermt2b.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
-2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-asm.c (convert_bfc_to_bfm): New.
+ (convert_to_real): Add case for OP_BFC.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-dis.c: (convert_bfm_to_bfc): New.
+ (convert_to_alias): Add case for OP_BFC.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
+ to allow width operand in three-operand instructions.
+ * aarch64-tbl.h (QL_BF1): New.
+ (aarch64_feature_v8_2): New.
+ (ARMV8_2): New.
+ (aarch64_opcode_table): Add "bfc".
- * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
- * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
- PREFIX_EVEX_0F38B5.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
- (cpu_flags): Add CpuAVX512IFMA.
- * i386-opc.h (enum): Add CpuAVX512IFMA.
- (i386_cpu_flags): Add cpuavx512ifma.
- * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
-2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-dis.c: Weaken assert.
+ * aarch64-gen.c: Include the instruction in the list of its
+ possible aliases.
- * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
- (prefix_table): Add pcommit.
- * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
- (cpu_flags): Add CpuPCOMMIT.
- * i386-opc.h (enum): Add CpuPCOMMIT.
- (i386_cpu_flags): Add cpupcommit.
- * i386-opc.tbl: Add pcommit.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
-2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
+ * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
+ (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
+ feature test.
- * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
- (prefix_table): Add clwb.
- * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
- (cpu_flags): Add CpuCLWB.
- * i386-opc.h (enum): Add CpuCLWB.
- (i386_cpu_flags): Add cpuclwb.
- * i386-opc.tbl: Add clwb.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+2015-11-23 Tristan Gingold <gingold@adacore.com>
-2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
+ * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
- * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
- (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
+2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
-2014-11-03 Nick Clifton <nickc@redhat.com>
+ * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
+ sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
+ tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
+ amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
+ cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
+ cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
+ cnthv_ctl_el2, cnthv_cval_el2.
+ (aarch64_sys_reg_supported_p): Update for the new system
+ registers.
- * po/fi.po: Updated Finnish translation.
+2015-11-20 Nick Clifton <nickc@redhat.com>
-2014-10-31 Andrew Pinski <apinski@cavium.com>
- Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
+ PR binutils/19224
+ * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
- * mips-dis.c (mips_arch_choices): Add octeon3.
- * mips-opc.c (IOCT): Include INSN_OCTEON3.
- (IOCT2): Likewise.
- (IOCT3): New define.
- (IVIRT): New define.
- (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
- tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
- IVIRT instructions.
- Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
- operand for IOCT3.
+2015-11-20 Nick Clifton <nickc@redhat.com>
-2014-10-29 Nick Clifton <nickc@redhat.com>
+ * po/zh_CN.po: Updated simplified Chinese translation.
- * po/de.po: Updated German translation.
+2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
-2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
-
- * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
- (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. Use new
- MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers. Add
- size and format initializers. Merge 'b' arguments into 'j'.
- (NIOS2_NUM_OPCODES): Adjust definition.
- (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
- (nios2_opcodes): Adjust.
- (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
- * nios2-dis.c (INSNLEN): Update comment.
- (nios2_hash_init, nios2_hash): Delete.
- (OPCODE_HASH_SIZE): New.
- (nios2_r1_extract_opcode): New.
- (nios2_disassembler_state): New.
- (nios2_r1_disassembler_state): New.
- (nios2_init_opcode_hash): Add state parameter. Adjust to use it.
- (nios2_find_opcode_hash): Use state object.
- (bad_opcode): New.
- (nios2_print_insn_arg): Add op parameter. Use it to access
- format. Remove 'b' case.
- (nios2_disassemble): Remove special case for nop. Remove
- hard-coded instruction size.
-
-2014-10-21 Jan Beulich <jbeulich@suse.com>
+ * aarch64-opc.c (operand_general_constraint_met_p): Check validity
+ of MSR PAN immediate operand.
- * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
+2015-11-16 Nick Clifton <nickc@redhat.com>
-2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+ * rx-dis.c (condition_names): Replace always and never with
+ invalid, since the always/never conditions can never be legal.
- * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
- entries.
- Annotate several instructions with the HWCAP2_VIS3B hwcap.
-
-2014-10-15 Tristan Gingold <gingold@adacore.com>
+2015-11-13 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
-2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
- `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
- Annotate table with HWCAP2 bits.
- Add instructions xmontmul, xmontsqr, xmpmul.
- (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
- r,i,%mwait' and `rd %mwait,r' instructions.
- Add rd/wr instructions for accessing the %mcdper ancillary state
- register.
- (sparc-opcodes): Add sparc5/vis4.0 instructions:
- subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
- fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
- fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
- fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
- fpsubus16, and faligndatai.
- * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
- ancillary state register to the table.
- (print_insn_sparc): Handle the %mcdper ancillary state register.
- (print_insn_sparc): Handle new operand type '}'.
-
-2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (MOD_0F20): Removed.
- (MOD_0F21): Likewise.
- (MOD_0F22): Likewise.
- (MOD_0F23): Likewise.
- (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
- MOD_0F23 with "movZ".
- (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
- (OP_R): Check mod/rm byte and call OP_E_register.
-
-2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
-
- * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
- keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
- keyword_aridxi): Add audio ISA extension.
- (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
- keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
- keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
- for nds32-dis.c using.
- (build_opcode_syntax): Remove dead code.
- (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
- parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
- parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
- operand parser.
- * nds32-asm.h: Declare.
- * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
- decoding by switch.
-
-2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
- Matthew Fortune <matthew.fortune@imgtec.com>
-
- * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
- mips64r6.
- (parse_mips_dis_option): Allow MSA and virtualization support for
- mips64r6.
- (mips_print_arg_state): Add fields dest_regno and seen_dest.
- (mips_seen_register): New function.
- (print_insn_arg): Refactored code to use mips_seen_register
- function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
- OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
- the register rather than aborting.
- (print_insn_args): Add length argument. Add code to correctly
- calculate the instruction address for pc relative instructions.
- (validate_insn_args): New static function.
- (print_insn_mips): Prevent jalx disassembling for r6. Use
- validate_insn_args.
- (print_insn_micromips): Use validate_insn_args.
- all the arguments are valid.
- * mips-formats.h (PREV_CHECK): New define.
- * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
- -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
- (RD_pc): New define.
- (FS): New define.
- (I37): New define.
- (I69): New define.
- (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
- MIPS R6 instructions from MIPS R2 instructions.
-
-2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
- (putop): Handle "%LP".
-
-2014-09-03 Jiong Wang <jiong.wang@arm.com>
-
- * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
- * aarch64-dis-2.c: Update auto-generated file.
-
-2014-09-03 Jiong Wang <jiong.wang@arm.com>
-
- * aarch64-tbl.h (QL_R4NIL): New qualifiers.
- (aarch64_feature_lse): New feature added.
- (LSE): New Added.
- (aarch64_opcode_table): New LSE instructions added. Improve
- descriptions for ldarb/ldarh/ldar.
- (aarch64_opcode_table): Describe PAIRREG.
- * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
- * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
- (aarch64_print_operand): Recognize PAIRREG.
- (operand_general_constraint_met_p): Check reg pair constraints for CASP
+2015-11-11 Alan Modra <amodra@gmail.com>
+ Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
+ Add PPC_OPCODE_VSX3 to the vsx entry.
+ (powerpc_init_dialect): Set default dialect to power9.
+ * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
+ insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
+ extract_l1 insert_xtq6, extract_xtq6): New static functions.
+ (insert_esync): Test for illegal L operand value.
+ (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
+ XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
+ XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
+ XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
+ PPCVSX3): New defines.
+ (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
+ fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
+ <mcrxr>: Use XBFRARB_MASK.
+ <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
+ bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
+ cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
+ cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
+ lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
+ lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
+ modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
+ rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
+ stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
+ subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
+ vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
+ vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
+ vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
+ vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
+ vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
+ vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
+ vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
+ xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
+ xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
+ xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
+ xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
+ xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
+ xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
+ xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
+ xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
+ xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
+ xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
+ xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
+ xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
+ xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
+ <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
+ <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
+
+2015-11-02 Nick Clifton <nickc@redhat.com>
+
+ * rx-decode.opc (rx_decode_opcode): Decode extra NOP
instructions.
- * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
- (do_special_decoding): Recognize F_LSE_SZ.
- * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
-
-2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
-
- * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
- (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
- "sdbbp", "syscall" and "wait".
-
-2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
- Maciej W. Rozycki <macro@codesourcery.com>
-
- * arm-dis.c (print_arm_address): Negate the GPR-relative offset
- returned if the U bit is set.
-
-2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
-
- * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
- 48-bit "li" encoding.
-
-2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
-
- * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
- (s390_print_insn_with_opcode, opcode_mask_more_specific): New
- static functions, code was moved from...
- (print_insn_s390): ...here.
- (s390_extract_operand): Adjust comment. Change type of first
- parameter from 'unsigned char *' to 'const bfd_byte *'.
- (union operand_value): New.
- (s390_extract_operand): Change return type to union operand_value.
- Also avoid integer overflow in sign-extension.
- (s390_print_insn_with_opcode): Adjust to changed return value from
- s390_extract_operand(). Change "%i" printf format to "%u" for
- unsigned values.
- (init_disasm): Simplify initialization of opc_index[]. This also
- fixes an access after the last element of s390_opcodes[].
- (print_insn_s390): Simplify the opcode search loop.
- Check architecture mask against all searched opcodes, not just the
- first matching one.
- (s390_print_insn_with_opcode): Drop function pointer dereferences
- without effect.
- (print_insn_s390): Likewise.
- (s390_insn_length): Simplify formula for return value.
- (s390_print_insn_with_opcode): Avoid special handling for the
- separator before the first operand. Use new local variable
- 'flags' in place of 'operand->flags'.
-
-2014-08-14 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (struct private): Change int's to bfd_boolean's.
- (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
- decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
- Change assignment of 1 to priv->comment to TRUE.
- (print_insn_bfin): Change legal to a bfd_boolean. Change
- assignment of 0/1 with priv comment and parallel and legal
- to FALSE/TRUE.
-
-2014-08-14 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (OUT): Define.
- (decode_CC2stat_0): Declare new op_names array.
- Replace multiple if statements with a single one.
-
-2014-08-14 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (struct private): Add iw0.
- (_print_insn_bfin): Assign iw0 to priv.iw0.
- (print_insn_bfin): Drop ifetch and use priv.iw0.
-
-2014-08-13 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (comment, parallel): Move from global scope ...
- (struct private): ... to this new struct.
- (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
- decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
- decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
- decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
- decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
- decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
- decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
- print_insn_bfin): Declare private struct. Use priv's comment and
- parallel members.
-
-2014-08-13 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
- (_print_insn_bfin): Add check for unaligned pc.
-
-2014-08-13 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (ifetch): New function.
- (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
- -1 when it errors.
-
-2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
-
- * micromips-opc.c (COD): Rename throughout to...
- (CM): New define, update to use INSN_COPROC_MOVE.
- (LCD): Rename throughout to...
- (LC): New define, update to use INSN_LOAD_COPROC.
- * mips-opc.c: Likewise.
-
-2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
-
- * micromips-opc.c (COD, LCD) New macros.
- (cfc1, ctc1): Remove FP_S attribute.
- (dmfc1, mfc1, mfhc1): Add LCD attribute.
- (dmtc1, mtc1, mthc1): Add COD attribute.
- * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
-
-2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
- Alexander Ivchenko <alexander.ivchenko@intel.com>
- Maxim Kuznetsov <maxim.kuznetsov@intel.com>
- Sergey Lega <sergey.s.lega@intel.com>
- Anna Tikhonova <anna.tikhonova@intel.com>
- Ilya Tocar <ilya.tocar@intel.com>
- Andrey Turetskiy <andrey.turetskiy@intel.com>
- Ilya Verbin <ilya.verbin@intel.com>
- Kirill Yukhin <kirill.yukhin@intel.com>
- Michael Zolotukhin <michael.v.zolotukhin@intel.com>
-
- * i386-dis-evex.h: Updated.
- * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
- PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
- PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
- PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
- PREFIX_EVEX_0F3A67.
- (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
- VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
- (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
- EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
- EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
- EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
- EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
- EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
- EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
- (prefix_table): Add entries for new instructions.
- (vex_len_table): Ditto.
- (vex_w_table): Ditto.
- (OP_E_memory): Update xmmq_mode handling.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
- (cpu_flags): Add CpuAVX512DQ.
- * i386-init.h: Regenerared.
- * i386-opc.h (CpuAVX512DQ): New.
- (i386_cpu_flags): Add cpuavx512dq.
- * i386-opc.tbl: Add AVX512DQ instructions.
- * i386-tbl.h: Regenerate.
+ * rx-decode.c: Regenerate.
-2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
- Alexander Ivchenko <alexander.ivchenko@intel.com>
- Maxim Kuznetsov <maxim.kuznetsov@intel.com>
- Sergey Lega <sergey.s.lega@intel.com>
- Anna Tikhonova <anna.tikhonova@intel.com>
- Ilya Tocar <ilya.tocar@intel.com>
- Andrey Turetskiy <andrey.turetskiy@intel.com>
- Ilya Verbin <ilya.verbin@intel.com>
- Kirill Yukhin <kirill.yukhin@intel.com>
- Michael Zolotukhin <michael.v.zolotukhin@intel.com>
-
- * i386-dis-evex.h: Add new instructions (prefixes bellow).
- * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
- (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
- (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
- PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
- PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
- PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
- PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
- PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
- PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
- PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
- PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
- PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
- PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
- PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
- PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
- PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
- PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
- PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
- PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
- PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
- PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
- PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
- (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
- VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
- VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
- VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
- VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
- VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
- VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
- VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
- VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
- VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
- VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
- (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
- EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
- EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
- EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
- EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
- EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
- EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
- (prefix_table): Add entries for new instructions.
- (vex_table) : Ditto.
- (vex_len_table): Ditto.
- (vex_w_table): Ditto.
- (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
- mask_bd_mode handling.
- (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
- handling.
- (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
- handling.
- (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
- (OP_EX): Add dqw_swap_mode handling.
- (OP_VEX): Add mask_bd_mode handling.
- (OP_Mask): Add mask_bd_mode handling.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
- (cpu_flags): Add CpuAVX512BW.
- * i386-init.h: Regenerated.
- * i386-opc.h (CpuAVX512BW): New.
- (i386_cpu_flags): Add cpuavx512bw.
- * i386-opc.tbl: Add AVX512BW instructions.
- * i386-tbl.h: Regenerate.
+2015-11-02 Nick Clifton <nickc@redhat.com>
-2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
- Alexander Ivchenko <alexander.ivchenko@intel.com>
- Maxim Kuznetsov <maxim.kuznetsov@intel.com>
- Sergey Lega <sergey.s.lega@intel.com>
- Anna Tikhonova <anna.tikhonova@intel.com>
- Ilya Tocar <ilya.tocar@intel.com>
- Andrey Turetskiy <andrey.turetskiy@intel.com>
- Ilya Verbin <ilya.verbin@intel.com>
- Kirill Yukhin <kirill.yukhin@intel.com>
- Michael Zolotukhin <michael.v.zolotukhin@intel.com>
-
- * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
- * i386-tbl.h: Regenerate.
+ * rx-decode.opc (rx_disp): If the displacement is zero, set the
+ type to RX_Operand_Zero_Indirect.
+ * rx-decode.c: Regenerate.
+ * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
-2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
- Alexander Ivchenko <alexander.ivchenko@intel.com>
- Maxim Kuznetsov <maxim.kuznetsov@intel.com>
- Sergey Lega <sergey.s.lega@intel.com>
- Anna Tikhonova <anna.tikhonova@intel.com>
- Ilya Tocar <ilya.tocar@intel.com>
- Andrey Turetskiy <andrey.turetskiy@intel.com>
- Ilya Verbin <ilya.verbin@intel.com>
- Kirill Yukhin <kirill.yukhin@intel.com>
- Michael Zolotukhin <michael.v.zolotukhin@intel.com>
-
- * i386-dis.c (intel_operand_size): Support 128/256 length in
- vex_vsib_q_w_dq_mode.
- (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
- (cpu_flags): Add CpuAVX512VL.
- * i386-init.h: Regenerated.
- * i386-opc.h (CpuAVX512VL): New.
- (i386_cpu_flags): Add cpuavx512vl.
- (BROADCAST_1TO4, BROADCAST_1TO2): Define.
- * i386-opc.tbl: Add AVX512VL instructions.
- * i386-tbl.h: Regenerate.
+2015-10-28 Yao Qi <yao.qi@linaro.org>
-2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ * aarch64-dis.c (aarch64_decode_insn): Add one argument
+ noaliases_p. Update comments. Pass noaliases_p rather than
+ no_aliases to aarch64_opcode_decode.
+ (print_insn_aarch64_word): Pass no_aliases to
+ aarch64_decode_insn.
- * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
- * or1k-opinst.c: Regenerate.
+2015-10-27 Vinay <Vinay.G@kpit.com>
-2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
+ PR binutils/19159
+ * rl78-decode.opc (MOV): Added offset to DE register in index
+ addressing mode.
+ * rl78-decode.c: Regenerate.
- * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
- (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
+2015-10-27 Vinay Kumar <vinay.g@kpit.com>
-2014-07-04 Alan Modra <amodra@gmail.com>
+ PR binutils/19158
+ * rl78-decode.opc: Add 's' print operator to instructions that
+ access system registers.
+ * rl78-decode.c: Regenerate.
+ * rl78-dis.c (print_insn_rl78_common): Decode all system
+ registers.
- * configure.ac: Rename from configure.in.
- * Makefile.in: Regenerate.
- * config.in: Regenerate.
+2015-10-27 Vinay Kumar <vinay.g@kpit.com>
-2014-07-04 Alan Modra <amodra@gmail.com>
+ PR binutils/19157
+ * rl78-decode.opc: Add 'a' print operator to mov instructions
+ using stack pointer plus index addressing.
+ * rl78-decode.c: Regenerate.
- * configure.in: Include bfd/version.m4.
- (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
- (BFD_VERSION): Delete.
- * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
- * configure: Regenerate.
- * Makefile.in: Regenerate.
+2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
-2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
- Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
- Pitchumani Sivanupandi <pitchumani.s@atmel.com>
- Soundararajan <Sounderarajan.D@atmel.com>
+ * s390-opc.c: Fix comment.
+ * s390-opc.txt: Change instruction type for troo, trot, trto, and
+ trtt to RRF_U0RER since the second parameter does not need to be a
+ register pair.
- * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
- (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
- machine is not avrtiny.
+2015-10-08 Nick Clifton <nickc@redhat.com>
-2014-06-26 Philippe De Muyter <phdm@macqel.be>
+ * arc-dis.c (print_insn_arc): Initiallise insn array.
- * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
- constants.
+2015-10-07 Yao Qi <yao.qi@linaro.org>
-2014-06-12 Alan Modra <amodra@gmail.com>
+ * aarch64-dis.c (aarch64_ext_sysins_op): Access field
+ 'name' rather than 'template'.
+ * aarch64-opc.c (aarch64_print_operand): Likewise.
- * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
- * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
+2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
-2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
+ * arc-dis.c: Revamped file for ARC support
+ * arc-dis.h: Likewise.
+ * arc-ext.c: Likewise.
+ * arc-ext.h: Likewise.
+ * arc-opc.c: Likewise.
+ * arc-fxi.h: New file.
+ * arc-regs.h: Likewise.
+ * arc-tbl.h: Likewise.
- * i386-dis.c (fwait_prefix): New.
- (ckprefix): Set fwait_prefix.
- (print_insn): Properly print prefixes before fwait.
-
-2014-06-07 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
-
-2014-06-05 Joel Brobecker <brobecker@adacore.com>
-
- * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
- bfd's development.sh.
- * Makefile.in, configure: Regenerate.
-
-2014-06-03 Nick Clifton <nickc@redhat.com>
-
- * msp430-dis.c (msp430_doubleoperand): Use extension_word to
- decide when extended addressing is being used.
-
-2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
-
- * sparc-opc.c (cas): Disable for LEON.
- (casl): Likewise.
-
-2014-05-20 Alan Modra <amodra@gmail.com>
-
- * m68k-dis.c: Don't include setjmp.h.
-
-2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (ADDR16_PREFIX): Removed.
- (ADDR32_PREFIX): Likewise.
- (DATA16_PREFIX): Likewise.
- (DATA32_PREFIX): Likewise.
- (prefix_name): Updated.
- (print_insn): Simplify data and address size prefixes processing.
-
-2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-
- * or1k-desc.c: Regenerated.
- * or1k-desc.h: Likewise.
- * or1k-opc.c: Likewise.
- * or1k-opc.h: Likewise.
- * or1k-opinst.c: Likewise.
-
-2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
-
- * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
- (I34): New define.
- (I36): New define.
- (I66): New define.
- (I68): New define.
- * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
- mips64r5.
- (parse_mips_dis_option): Update MSA and virtualization support to
- allow mips64r3 and mips64r5.
-
-2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
-
- * mips-opc.c (G3): Remove I4.
-
-2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/16893
- * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
- (end_codep): Likewise.
- (mandatory_prefix): Likewise.
- (active_seg_prefix): Likewise.
- (ckprefix): Set active_seg_prefix to the active segment register
- prefix.
- (seg_prefix): Removed.
- (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
- for prefix index. Ignore the index if it is invalid and the
- mandatory prefix isn't required.
- (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
- mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
- in used_prefixes here. Don't print unused prefixes. Check
- active_seg_prefix for the active segment register prefix.
- Restore the DFLAG bit in sizeflag if the data size prefix is
- unused. Check the unused mandatory PREFIX_XXX prefixes
- (append_seg): Only print the segment register which gets used.
- (OP_E_memory): Check active_seg_prefix for the segment register
- prefix.
- (OP_OFF): Likewise.
- (OP_OFF64): Likewise.
- (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
-
-2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/16886
- * config.in: Regenerated.
- * configure: Likewise.
- * configure.in: Check if sigsetjmp is available.
- * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
- (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
- (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
- * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
- (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
- (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
- * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
- (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
- (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
- * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
- (OPCODES_SIGSETJMP): Likewise.
- (OPCODES_SIGLONGJMP): Likewise.
- * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
- (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
- (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
- * xtensa-dis.c (dis_private): Replace jmp_buf with
- OPCODES_SIGJMP_BUF.
- (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
- (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
- * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
- (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
- (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
-
-2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/16891
- * i386-dis.c (print_insn): Handle prefixes before fwait.
-
-2014-04-26 Alan Modra <amodra@gmail.com>
+2015-10-02 Yao Qi <yao.qi@linaro.org>
- * po/POTFILES.in: Regenerate.
+ * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
+ argument insn type to aarch64_insn. Rename to ...
+ (aarch64_decode_insn): ... it.
+ (print_insn_aarch64_word): Caller updated.
-2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
-
- * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
- to allow the MIPS XPA ASE.
- (parse_mips_dis_option): Process the -Mxpa option.
- * mips-opc.c (XPA): New define.
- (mips_builtin_opcodes): Add MIPS XPA instructions and move the
- locations of the ctc0 and cfc0 instructions.
-
-2014-04-22 Christian Svensson <blue@cmd.nu>
-
- * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
- * configure.in: Likewise.
- * disassemble.c: Likewise.
- * or1k-asm.c: New file.
- * or1k-desc.c: New file.
- * or1k-desc.h: New file.
- * or1k-dis.c: New file.
- * or1k-ibld.c: New file.
- * or1k-opc.c: New file.
- * or1k-opc.h: New file.
- * or1k-opinst.c: New file.
- * Makefile.in: Regenerate.
- * configure: Regenerate.
- * openrisc-asm.c: Delete.
- * openrisc-desc.c: Delete.
- * openrisc-desc.h: Delete.
- * openrisc-dis.c: Delete.
- * openrisc-ibld.c: Delete.
- * openrisc-opc.c: Delete.
- * openrisc-opc.h: Delete.
- * or32-dis.c: Delete.
- * or32-opc.c: Delete.
-
-2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
-
- * i386-dis.c (rm_table): Add encls, enclu.
- * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
- (cpu_flags): Add CpuSE1.
- * i386-opc.h (enum): Add CpuSE1.
- (i386_cpu_flags): Add cpuse1.
- * i386-opc.tbl: Add encls, enclu.
+2015-10-02 Yao Qi <yao.qi@linaro.org>
+
+ * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
+ (print_insn_aarch64_word): Caller updated.
+
+2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
+
+ * s390-mkopc.c (main): Parse htm and vx flag.
+ * s390-opc.txt: Mark instructions from the hardware transactional
+ memory and vector facilities with the "htm"/"vx" flag.
+
+2015-09-28 Nick Clifton <nickc@redhat.com>
+
+ * po/de.po: Updated German translation.
+
+2015-09-28 Tom Rix <tom@bumblecow.com>
+
+ * ppc-opc.c (PPC500): Mark some opcodes as invalid
+
+2015-09-23 Nick Clifton <nickc@redhat.com>
+
+ * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
+ function.
+ * tic30-dis.c (print_branch): Likewise.
+ * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
+ value before left shifting.
+ * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
+ * hppa-dis.c (print_insn_hppa): Likewise.
+ * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
+ array.
+ * msp430-dis.c (msp430_singleoperand): Likewise.
+ (msp430_doubleoperand): Likewise.
+ (print_insn_msp430): Likewise.
+ * nds32-asm.c (parse_operand): Likewise.
+ * sh-opc.h (MASK): Likewise.
+ * v850-dis.c (get_operand_value): Likewise.
+
+2015-09-22 Nick Clifton <nickc@redhat.com>
+
+ * rx-decode.opc (bwl): Use RX_Bad_Size.
+ (sbwl): Likewise.
+ (ubwl): Likewise. Rename to ubw.
+ (uBWL): Rename to uBW.
+ Replace all references to uBWL with uBW.
+ * rx-decode.c: Regenerate.
+ * rx-dis.c (size_names): Add entry for RX_Bad_Size.
+ (opsize_names): Likewise.
+ (print_insn_rx): Detect and report RX_Bad_Size.
+
+2015-09-22 Anton Blanchard <anton@samba.org>
+
+ * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
+
+2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-dis.c (print_insn_sparc): Handle the privileged register
+ %pmcdper.
+
+2015-08-24 Jan Stancek <jstancek@redhat.com>
+
+ * i386-dis.c (print_insn): Fix decoding of three byte operands.
+
+2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
+
+ PR binutils/18257
+ * i386-dis.c: Use MOD_TABLE for most of mask instructions.
+ (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
+ MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
+ MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
+ MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
+ MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
+ MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
+ MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
+ MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
+ MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
+ MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
+ MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
+ MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
+ MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
+ MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
+ MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
+ MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
+ MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
+ MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
+ MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
+ MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
+ MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
+ MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
+ MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
+ MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
+ MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
+ MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
+ (vex_w_table): Replace terminals with MOD_TABLE entries for
+ most of mask instructions.
+
+2015-08-17 Alan Modra <amodra@gmail.com>
+
+ * cgen.sh: Trim trailing space from cgen output.
+ * ia64-gen.c (print_dependency_table): Don't generate trailing space.
+ (print_dis_table): Likewise.
+ * opc2c.c (dump_lines): Likewise.
+ (orig_filename): Warning fix.
+ * ia64-asmtab.c: Regenerate.
+
+2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * arm-dis.c (print_insn_arm): Disassembling for all targets V6
+ and higher with ARM instruction set will now mark the 26-bit
+ versions of teq,tst,cmn and cmp as UNPREDICTABLE.
+ (arm_opcodes): Fix for unpredictable nop being recognized as a
+ teq.
+
+2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
+
+ * micromips-opc.c (micromips_opcodes): Re-order table so that move
+ based on 'or' is first.
+ * mips-opc.c (mips_builtin_opcodes): Ditto.
+
+2015-08-11 Nick Clifton <nickc@redhat.com>
+
+ PR 18800
+ * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
+ instruction.
+
+2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
+
+2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
+
+ * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
+ * i386-init.h: Regenerated.
+
+2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/13571
+ * i386-dis.c (MOD_0FC3): New.
+ (PREFIX_0FC3): Renamed to ...
+ (PREFIX_MOD_0_0FC3): This.
+ (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
+ (prefix_table): Replace Ma with Ev on movntiS.
+ (mod_table): Add MOD_0FC3.
+
+2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+
+2015-07-23 Alan Modra <amodra@gmail.com>
+
+ PR 18708
+ * i386-dis.c (get64): Avoid signed integer overflow.
+
+2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
+
+ PR binutils/18631
+ * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
+ "EXEvexHalfBcstXmmq" for the second operand.
+ (EVEX_W_0F79_P_2): Likewise.
+ (EVEX_W_0F7A_P_2): Likewise.
+ (EVEX_W_0F7B_P_2): Likewise.
+
+2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
+
+ * arm-dis.c (print_insn_coprocessor): Added support for quarter
+ float bitfield format.
+ (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
+ quarter float bitfield format.
+
+2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+
+2015-07-03 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
+ * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
+ PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
+
+2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
+ Cesar Philippidis <cesar@codesourcery.com>
+
+ * nios2-dis.c (nios2_extract_opcode): New.
+ (nios2_disassembler_state): New.
+ (nios2_find_opcode_hash): Use mach parameter to select correct
+ disassembler state.
+ (nios2_print_insn_arg): Extend to support new R2 argument letters
+ and formats.
+ (print_insn_nios2): Check for 16-bit instruction at end of memory.
+ * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
+ (NIOS2_NUM_OPCODES): Rename to...
+ (NIOS2_NUM_R1_OPCODES): This.
+ (nios2_r2_opcodes): New.
+ (NIOS2_NUM_R2_OPCODES): New.
+ (nios2_num_r2_opcodes): New.
+ (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
+ (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
+ (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
+ (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
+ (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
+
+2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
+
+ * i386-dis.c (OP_Mwaitx): New.
+ (rm_table): Add monitorx/mwaitx.
+ * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
+ and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
+ (operand_type_init): Add CpuMWAITX.
+ * i386-opc.h (CpuMWAITX): New.
+ (i386_cpu_flags): Add cpumwaitx.
+ * i386-opc.tbl: Add monitorx and mwaitx.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
-2014-04-02 Anthony Green <green@moxielogic.com>
+2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
- * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
- instructions, sex.b and sex.s.
+ * ppc-opc.c (insert_ls): Test for invalid LS operands.
+ (insert_esync): New function.
+ (LS, WC): Use insert_ls.
+ (ESYNC): Use insert_esync.
-2014-03-26 Jiong Wang <jiong.wang@arm.com>
+2015-06-22 Nick Clifton <nickc@redhat.com>
- * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
- instructions.
+ * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
+ requested region lies beyond it.
+ * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
+ looking for 32-bit insns.
+ * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
+ data.
+ * sh-dis.c (print_insn_sh): Likewise.
+ * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
+ blocks of instructions.
+ * vax-dis.c (print_insn_vax): Check that the requested address
+ does not clash with the stop_vma.
-2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
+2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
- * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
- vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
- vscatterqps.
- * i386-tbl.h: Regenerate.
+ * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
+ * ppc-opc.c (FXM4): Add non-zero optional value.
+ (TBR): Likewise.
+ (SXL): Likewise.
+ (insert_fxm): Handle new default operand value.
+ (extract_fxm): Likewise.
+ (insert_tbr): Likewise.
+ (extract_tbr): Likewise.
-2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
+2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
- * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
- %hstick_enable added.
+ * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
-2014-03-19 Nick Clifton <nickc@redhat.com>
+2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
- * rx-decode.opc (bwl): Allow for bogus instructions with a size
- field of 3.
- (sbwl, ubwl, SCALE): Likewise.
- * rx-decode.c: Regenerate.
+ * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
-2014-03-12 Alan Modra <amodra@gmail.com>
+2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
- * Makefile.in: Regenerate.
+ * ppc-opc.c: Add comment accidentally removed by old commit.
+ (MTMSRD_L): Delete.
-2014-03-05 Alan Modra <amodra@gmail.com>
+2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
- Update copyright years.
+ * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
-2014-03-04 Heiher <r@hev.cc>
+2015-06-04 Nick Clifton <nickc@redhat.com>
- * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
+ PR 18474
+ * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
-2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
- * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
- so that they come after the Loongson extensions.
+ * arm-dis.c (arm_opcodes): Add "setpan".
+ (thumb_opcodes): Add "setpan".
-2014-03-03 Alan Modra <amodra@gmail.com>
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
- * i386-gen.c (process_copyright): Emit copyright notice on one line.
+ * arm-dis.c (select_arm_features): Rework to avoid used of redefined
+ macros.
-2014-02-28 Alan Modra <amodra@gmail.com>
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
- * msp430-decode.c: Regenerate.
+ * aarch64-tbl.h (aarch64_feature_rdma): New.
+ (RDMA): New.
+ (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
-2014-02-27 Jiong Wang <jiong.wang@arm.com>
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
- * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
- FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
+ * aarch64-tbl.h (aarch64_feature_lor): New.
+ (LOR): New.
+ (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
+ "stllrb", "stllrh".
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
-2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
+2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
- * aarch64-opc.c (print_register_offset_address): Call
- get_int_reg_name to prepare the register name.
+ * aarch64-opc.c (F_ARCHEXT): New.
+ (aarch64_sys_regs): Add "pan".
+ (aarch64_sys_reg_supported_p): New.
+ (aarch64_pstatefields): Add "pan".
+ (aarch64_pstatefield_supported_p): New.
-2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
+2015-06-01 Jan Beulich <jbeulich@suse.com>
- * i386-opc.tbl: Remove wrong variant of vcvtps2ph
* i386-tbl.h: Regenerate.
-2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
+2015-06-01 Jan Beulich <jbeulich@suse.com>
- * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
- (cpu_flags): Add CpuPREFETCHWT1.
- * i386-init.h: Regenerate.
- * i386-opc.h (CpuPREFETCHWT1): New.
- (i386_cpu_flags): Add cpuprefetchwt1.
- * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
- * i386-tbl.h: Regenerate.
+ * i386-dis.c (print_insn): Swap rounding mode specifier and
+ general purpose register in Intel mode.
-2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
+2015-06-01 Jan Beulich <jbeulich@suse.com>
- * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
- to CpuAVX512F.
+ * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
* i386-tbl.h: Regenerate.
-2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
+2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
- * i386-gen.c (output_cpu_flags): Don't output trailing space.
- (output_opcode_modifier): Likewise.
- (output_operand_type): Likewise.
+ * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
+ * i386-init.h: Regenerated.
+
+2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/18386
+ * i386-dis.c: Add comments for '@'.
+ (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
+ (enum x86_64_isa): New.
+ (isa64): Likewise.
+ (print_i386_disassembler_options): Add amd64 and intel64.
+ (print_insn): Handle amd64 and intel64.
+ (putop): Handle '@'.
+ (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
+ * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
+ * i386-opc.h (AMD64): New.
+ (CpuIntel64): Likewise.
+ (i386_cpu_flags): Add cpuamd64 and cpuintel64.
+ * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
+ Mark direct call/jmp without Disp16|Disp32 as Intel64.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
-2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
-
- * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
- MOD_0FC7_REG_5.
- (PREFIX enum): Add PREFIX_0FAE_REG_7.
- (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
- (prefix_table): Add clflusopt.
- (mod_table): Add xrstors, xsavec, xsaves.
- * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
- CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
- (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
- * i386-init.h: Regenerate.
- * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
- xsaves64, xsavec, xsavec64.
- * i386-tbl.h: Regenerate.
+2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
-2014-02-10 Alan Modra <amodra@gmail.com>
+ * ppc-opc.c (IH) New define.
+ (powerpc_opcodes) <wait>: Do not enable for POWER7.
+ <tlbie>: Add RS operand for POWER7.
+ <slbia>: Add IH operand for POWER6.
- * po/POTFILES.in: Regenerate.
- * po/opcodes.pot: Regenerate.
+2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
+ direct branch.
+ (jmp): Likewise.
+ * i386-tbl.h: Regenerated.
+
+2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure.ac: Support bfd_iamcu_arch.
+ * disassemble.c (disassembler): Support bfd_iamcu_arch.
+ * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
+ CPU_IAMCU_COMPAT_FLAGS.
+ (cpu_flags): Add CpuIAMCU.
+ * i386-opc.h (CpuIAMCU): New.
+ (i386_cpu_flags): Add cpuiamcu.
+ * configure: Regenerated.
+ * i386-init.h: Likewise.
+ * i386-tbl.h: Likewise.
+
+2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/18386
+ * i386-dis.c (X86_64_E8): New.
+ (X86_64_E9): Likewise.
+ Update comments on 'T', 'U', 'V'. Add comments for '^'.
+ (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
+ (x86_64_table): Add X86_64_E8 and X86_64_E9.
+ (mod_table): Replace {T|} with ^ on Jcall/Jmp.
+ (putop): Handle '^'.
+ (OP_J): Ignore the operand size prefix in 64-bit. Don't check
+ REX_W.
+
+2015-04-30 DJ Delorie <dj@redhat.com>
+
+ * disassemble.c (disassembler): Choose suitable disassembler based
+ on E_ABI.
+ * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
+ it to decode mul/div insns.
+ * rl78-decode.c: Regenerate.
+ * rl78-dis.c (print_insn_rl78): Rename to...
+ (print_insn_rl78_common): ...this, take ISA parameter.
+ (print_insn_rl78): New.
+ (print_insn_rl78_g10): New.
+ (print_insn_rl78_g13): New.
+ (print_insn_rl78_g14): New.
+ (rl78_get_disassembler): New.
+
+2015-04-29 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+
+2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (DCBT_EO): New define.
+ (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
+ <lharx>: Likewise.
+ <stbcx.>: Likewise.
+ <sthcx.>: Likewise.
+ <waitrsv>: Do not enable for POWER7 and later.
+ <waitimpl>: Likewise.
+ <dcbt>: Default to the two operand form of the instruction for all
+ "old" cpus. For "new" cpus, use the operand ordering that matches
+ whether the cpu is server or embedded.
+ <dcbtst>: Likewise.
+
+2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390-opc.c: New instruction type VV0UU2.
+ * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
+ and WFC.
+
+2015-04-23 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
+ * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
+ vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
+ (vfpclasspd, vfpclassps): Add %XZ.
+
+2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (PREFIX_UD_SHIFT): Removed.
+ (PREFIX_UD_REPZ): Likewise.
+ (PREFIX_UD_REPNZ): Likewise.
+ (PREFIX_UD_DATA): Likewise.
+ (PREFIX_UD_ADDR): Likewise.
+ (PREFIX_UD_LOCK): Likewise.
+
+2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (prefix_requirement): Removed.
+ (print_insn): Don't set prefix_requirement. Check
+ dp->prefix_requirement instead of prefix_requirement.
+
+2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/17898
+ * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
+ (PREFIX_MOD_0_0FC7_REG_6): This.
+ (PREFIX_MOD_3_0FC7_REG_6): New.
+ (PREFIX_MOD_3_0FC7_REG_7): Likewise.
+ (prefix_table): Replace PREFIX_0FC7_REG_6 with
+ PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
+ PREFIX_MOD_3_0FC7_REG_7.
+ (mod_table): Replace PREFIX_0FC7_REG_6 with
+ PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
+ PREFIX_MOD_3_0FC7_REG_7.
+
+2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
+ (PREFIX_MANDATORY_REPNZ): Likewise.
+ (PREFIX_MANDATORY_DATA): Likewise.
+ (PREFIX_MANDATORY_ADDR): Likewise.
+ (PREFIX_MANDATORY_LOCK): Likewise.
+ (PREFIX_MANDATORY): Likewise.
+ (PREFIX_UD_SHIFT): Set to 8
+ (PREFIX_UD_REPZ): Updated.
+ (PREFIX_UD_REPNZ): Likewise.
+ (PREFIX_UD_DATA): Likewise.
+ (PREFIX_UD_ADDR): Likewise.
+ (PREFIX_UD_LOCK): Likewise.
+ (PREFIX_IGNORED_SHIFT): New.
+ (PREFIX_IGNORED_REPZ): Likewise.
+ (PREFIX_IGNORED_REPNZ): Likewise.
+ (PREFIX_IGNORED_DATA): Likewise.
+ (PREFIX_IGNORED_ADDR): Likewise.
+ (PREFIX_IGNORED_LOCK): Likewise.
+ (PREFIX_OPCODE): Likewise.
+ (PREFIX_IGNORED): Likewise.
+ (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
+ (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
+ (three_byte_table): Likewise.
+ (mod_table): Likewise.
+ (mandatory_prefix): Renamed to ...
+ (prefix_requirement): This.
+ (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
+ Update PREFIX_90 entry.
+ (get_valid_dis386): Check prefix_requirement to see if a prefix
+ should be ignored.
+ (print_insn): Replace mandatory_prefix with prefix_requirement.
+
+2015-04-15 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
+ use it for ssat and ssat16.
+ (print_insn_thumb32): Add handle case for 'D' control code.
+
+2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
+ H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
+ * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
+ PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
+ PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
+ PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
+ (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
+ Fill prefix_requirement field.
+ (struct dis386): Add prefix_requirement field.
+ (dis386): Fill prefix_requirement field.
+ (dis386_twobyte): Ditto.
+ (twobyte_has_mandatory_prefix_: Remove.
+ (reg_table): Fill prefix_requirement field.
+ (prefix_table): Ditto.
+ (x86_64_table): Ditto.
+ (three_byte_table): Ditto.
+ (xop_table): Ditto.
+ (vex_table): Ditto.
+ (vex_len_table): Ditto.
+ (vex_w_table): Ditto.
+ (mod_table): Ditto.
+ (bad_opcode): Ditto.
+ (print_insn): Use prefix_requirement.
+ (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
+ FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
+ (float_reg): Ditto.
+
+2015-03-30 Mike Frysinger <vapier@gentoo.org>
+
+ * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
+
+2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ * Makefile.in: Regenerated.
+
+2015-03-25 Anton Blanchard <anton@samba.org>
-2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
- Jan Beulich <jbeulich@suse.com>
+ * ppc-dis.c (disassemble_init_powerpc): Only initialise
+ powerpc_opcd_indices and vle_opcd_indices once.
- PR binutils/16490
- * i386-dis.c (OP_E_memory): Fix shift computation for
- vex_vsib_q_w_dq_mode.
+2015-03-25 Anton Blanchard <anton@samba.org>
+
+ * ppc-opc.c (powerpc_opcodes): Add slbfee.
+
+2015-03-24 Terry Guo <terry.guo@arm.com>
+
+ * arm-dis.c (opcode32): Updated to use new arm feature struct.
+ (opcode16): Likewise.
+ (coprocessor_opcodes): Replace bit with feature struct.
+ (neon_opcodes): Likewise.
+ (arm_opcodes): Likewise.
+ (thumb_opcodes): Likewise.
+ (thumb32_opcodes): Likewise.
+ (print_insn_coprocessor): Likewise.
+ (print_insn_arm): Likewise.
+ (select_arm_features): Follow new feature struct.
+
+2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ * i386-dis.c (rm_table): Add clzero.
+ * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
+ Add CPU_CLZERO_FLAGS.
+ (cpu_flags): Add CpuCLZERO.
+ * i386-opc.h: Add CpuCLZERO.
+ * i386-opc.tbl: Add clzero.
+ * i386-init.h: Re-generated.
+ * i386-tbl.h: Re-generated.
+
+2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-opc.c (decode_mips_operand): Fix constraint issues
+ with u and y operands.
+
+2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
+
+2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390-opc.c: Add new IBM z13 instructions.
+ * s390-opc.txt: Likewise.
+
+2015-03-10 Renlin Li <renlin.li@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
+ stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
+ related alias.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Likewise.
+ * aarch64-opc-2.c: Likewise.
+
+2015-03-03 Jiong Wang <jiong.wang@arm.com>
+
+ * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
+
+2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
+
+ * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
+ arch_sh_up.
+ (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
+ arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
+
+2015-02-23 Vinay <Vinay.G@kpit.com>
+
+ * rl78-decode.opc (MOV): Added space between two operands for
+ 'mov' instruction in index addressing mode.
+ * rl78-decode.c: Regenerate.
+
+2015-02-19 Pedro Alves <palves@redhat.com>
+
+ * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
+
+2015-02-10 Pedro Alves <palves@redhat.com>
+ Tom Tromey <tromey@redhat.com>
+
+ * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
+ microblaze_and, microblaze_xor.
+ * microblaze-opc.h (opcodes): Adjust.
+
+2015-01-28 James Bowman <james.bowman@ftdichip.com>
+
+ * Makefile.am: Add FT32 files.
+ * configure.ac: Handle FT32.
+ * disassemble.c (disassembler): Call print_insn_ft32.
+ * ft32-dis.c: New file.
+ * ft32-opc.c: New file.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
-2014-01-09 Bradley Nelson <bradnelson@google.com>
- Roland McGrath <mcgrathr@google.com>
+2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
- * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
- last_rex_prefix is -1.
+ * nds32-asm.c (keyword_sr): Add new system registers.
-2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
+2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
- * i386-gen.c (process_copyright): Update copyright year to 2014.
+ * s390-dis.c (s390_extract_operand): Support vector register
+ operands.
+ (s390_print_insn_with_opcode): Support new operands types and add
+ new handling of optional operands.
+ * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
+ and include opcode/s390.h instead.
+ (struct op_struct): New field `flags'.
+ (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
+ (dumpTable): Dump flags.
+ (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
+ string.
+ * s390-opc.c: Add new operands types, instruction formats, and
+ instruction masks.
+ (s390_opformats): Add new formats for .insn.
+ * s390-opc.txt: Add new instructions.
-2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
+2015-01-01 Alan Modra <amodra@gmail.com>
- * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
+ Update year range in copyright notice of all files.
-For older changes see ChangeLog-2013
+For older changes see ChangeLog-2014
\f
-Copyright (C) 2014 Free Software Foundation, Inc.
+Copyright (C) 2015 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / deliverable / binutils-gdb.git / blobdiff